1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1992 - 1997 Silicon Graphics, Inc. 7 */ 8 #ifndef __ASM_SN_INTR_PUBLIC_H 9 #define __ASM_SN_INTR_PUBLIC_H 10 11 12 /* REMEMBER: If you change these, the whole world needs to be recompiled. 13 * It would also require changing the hubspl.s code and SN0/intr.c 14 * Currently, the spl code has no support for multiple INTPEND1 masks. 15 */ 16 17 #define N_INTPEND0_MASKS 1 18 #define N_INTPEND1_MASKS 1 19 20 #define INTPEND0_MAXMASK (N_INTPEND0_MASKS - 1) 21 #define INTPEND1_MAXMASK (N_INTPEND1_MASKS - 1) 22 23 #ifndef __ASSEMBLY__ 24 #include <asm/sn/arch.h> 25 26 struct intr_vecblk_s; /* defined in asm/sn/intr.h */ 27 28 /* 29 * The following are necessary to create the illusion of a CEL 30 * on the SN0 hub. We'll add more priority levels soon, but for 31 * now, any interrupt in a particular band effectively does an spl. 32 * These must be in the PDA since they're different for each processor. 33 * Users of this structure must hold the vector_lock in the appropriate vector 34 * block before modifying the mask arrays. There's only one vector block 35 * for each Hub so a lock in the PDA wouldn't be adequate. 36 */ 37 typedef struct hub_intmasks_s { 38 /* 39 * The masks are stored with the lowest-priority (most inclusive) 40 * in the lowest-numbered masks (i.e., 0, 1, 2...). 41 */ 42 /* INT_PEND0: */ 43 hubreg_t intpend0_masks[N_INTPEND0_MASKS]; 44 /* INT_PEND1: */ 45 hubreg_t intpend1_masks[N_INTPEND1_MASKS]; 46 /* INT_PEND0: */ 47 struct intr_vecblk_s *dispatch0; 48 /* INT_PEND1: */ 49 struct intr_vecblk_s *dispatch1; 50 } hub_intmasks_t; 51 52 #endif /* !__ASSEMBLY__ */ 53 #endif /* __ASM_SN_INTR_PUBLIC_H */ 54