1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1999 by Ralf Baechle 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 */ 9 #ifndef _ASM_SERIAL_H 10 #define _ASM_SERIAL_H 11 12 #include <linux/config.h> 13 14 /* 15 * This assumes you have a 1.8432 MHz clock for your UART. 16 * 17 * It'd be nice if someone built a serial card with a 24.576 MHz 18 * clock, since the 16550A is capable of handling a top speed of 1.5 19 * megabits/second; but this requires the faster clock. 20 */ 21 #define BASE_BAUD (1843200 / 16) 22 23 /* Standard COM flags (except for COM4, because of the 8514 problem) */ 24 #ifdef CONFIG_SERIAL_DETECT_IRQ 25 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) 26 #define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) 27 #else 28 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) 29 #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 30 #endif 31 32 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT 33 34 #define STD_SERIAL_PORT_DEFNS \ 35 /* UART CLK PORT IRQ FLAGS */ \ 36 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 37 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 38 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 39 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 40 41 #else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ 42 #define STD_SERIAL_PORT_DEFNS 43 #endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ 44 45 #ifdef CONFIG_MIPS_SEAD 46 #include <asm/mips-boards/sead.h> 47 #include <asm/mips-boards/seadint.h> 48 #define SEAD_SERIAL_PORT_DEFNS \ 49 /* UART CLK PORT IRQ FLAGS */ \ 50 { 0, SEAD_BASE_BAUD, SEAD_UART0_REGS_BASE, SEADINT_UART0, STD_COM_FLAGS }, /* ttyS0 */ 51 #else 52 #define SEAD_SERIAL_PORT_DEFNS 53 #endif 54 55 #ifdef CONFIG_MOMENCO_OCELOT_C 56 /* Ordinary NS16552 duart with a 20MHz crystal. */ 57 #define OCELOT_C_BASE_BAUD ( 20000000 / 16 ) 58 59 #define OCELOT_C_SERIAL1_IRQ 80 60 #define OCELOT_C_SERIAL1_BASE 0xfffffffffd000020 61 62 #define OCELOT_C_SERIAL2_IRQ 81 63 #define OCELOT_C_SERIAL2_BASE 0xfffffffffd000000 64 65 #define _OCELOT_C_SERIAL_INIT(int, base) \ 66 { baud_base: OCELOT_C_BASE_BAUD, irq: int, flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),\ 67 iomem_base: (u8 *) base, iomem_reg_shift: 2, \ 68 io_type: SERIAL_IO_MEM } 69 #define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ 70 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \ 71 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE) 72 #else 73 #define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS 74 #endif 75 76 #ifdef CONFIG_MOMENCO_JAGUAR_ATX 77 /* Ordinary NS16552 duart with a 20MHz crystal. */ 78 #define JAGUAR_ATX_BASE_BAUD ( 20000000 / 16 ) 79 80 #define JAGUAR_ATX_SERIAL1_IRQ 7 81 #define JAGUAR_ATX_SERIAL1_BASE 0xfffffffffd000020 82 83 #define _JAGUAR_ATX_SERIAL_INIT(int, base) \ 84 { baud_base: JAGUAR_ATX_BASE_BAUD, irq: int, flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),\ 85 iomem_base: (u8 *) base, iomem_reg_shift: 2, \ 86 io_type: SERIAL_IO_MEM } 87 #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \ 88 _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE) 89 #else 90 #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS 91 #endif 92 93 #ifdef CONFIG_TITAN_SERIAL 94 /* 16552 20 MHz crystal */ 95 #define TITAN_SERIAL_BASE_BAUD ( 20000000 / 16 ) 96 #define TITAN_SERIAL_IRQ XXX 97 #define TITAN_SERIAL_BASE 0xffffffff 98 99 #define _TITAN_SERIAL_INIT(int, base) \ 100 { baud_base: TITAN_SERIAL_BASE_BAUD, irq: int, \ 101 flags: STD_COM_FLAGS, iomem_base: (u8 *) base, \ 102 iomem_reg_shift: 2, io_type: SERIAL_IO_MEM \ 103 } 104 105 #define TITAN_SERIAL_PORT_DEFNS \ 106 _TITAN_SERIAL_INIT(TITAN_SERIAL_IRQ, TITAN_SERIAL_BASE) 107 #else 108 #define TITAN_SERIAL_PORT_DEFNS 109 #endif 110 111 #ifdef CONFIG_SGI_IP27 112 113 /* 114 * Note about serial ports and consoles: 115 * For console output, everyone uses the IOC3 UARTA (offset 0x178) 116 * connected to the master node (look in ip27_setup_console() and 117 * ip27prom_console_write()). 118 * 119 * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port 120 * addresses on a partitioned machine. Since we currently use the ioc3 121 * serial ports, we use dynamic serial port discovery that the serial.c 122 * driver uses for pci/pnp ports (there is an entry for the SGI ioc3 123 * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater 124 * than UARTB's, although UARTA on o200s has traditionally been known as 125 * port 0. So, we just use one serial port from each ioc3 (since the 126 * serial driver adds addresses to get to higher ports). 127 * 128 * The first one to do a register_console becomes the preferred console 129 * (if there is no kernel command line console= directive). /dev/console 130 * (ie 5, 1) is then "aliased" into the device number returned by the 131 * "device" routine referred to in this console structure 132 * (ip27prom_console_dev). 133 * 134 * Also look in ip27-pci.c:pci_fixuop_ioc3() for some comments on working 135 * around ioc3 oddities in this respect. 136 * 137 * The IOC3 serials use a 22MHz clock rate with an additional divider by 3. 138 * (IOC3_BAUD = (22000000 / (3*16))) 139 * 140 * At the moment this is only a skeleton definition as we register all serials 141 * at runtime. 142 */ 143 144 #define IP27_SERIAL_PORT_DEFNS 145 #else 146 #define IP27_SERIAL_PORT_DEFNS 147 #endif /* CONFIG_SGI_IP27 */ 148 149 #define SERIAL_PORT_DFNS \ 150 IP27_SERIAL_PORT_DEFNS \ 151 MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ 152 MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \ 153 SEAD_SERIAL_PORT_DEFNS \ 154 STD_SERIAL_PORT_DEFNS \ 155 TITAN_SERIAL_PORT_DEFNS 156 157 #define RS_TABLE_SIZE 64 158 159 #endif /* _ASM_SERIAL_H */ 160