1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 */
11 #ifndef _ASM_PROCESSOR_H
12 #define _ASM_PROCESSOR_H
13
14 #include <linux/config.h>
15 #include <linux/cache.h>
16
17 /*
18 * Return current * instruction pointer ("program counter").
19 */
20 #define current_text_addr() \
21 ({ \
22 void *_a; \
23 \
24 __asm__ ("bal\t1f\t\t\t# current_text_addr\n" \
25 "1:\tmove\t%0, $31" \
26 : "=r" (_a) \
27 : \
28 : "$31"); \
29 \
30 _a; \
31 })
32
33 #ifndef __ASSEMBLY__
34 #include <linux/smp.h>
35
36 #include <asm/cachectl.h>
37 #include <asm/cpu.h>
38 #include <asm/mipsregs.h>
39 #include <asm/reg.h>
40 #include <asm/system.h>
41
42 #if defined(CONFIG_SGI_IP27)
43 #include <asm/sn/types.h>
44 #include <asm/sn/intr_public.h>
45 #endif
46
47 /*
48 * Descriptor for a cache
49 */
50 struct cache_desc {
51 unsigned short linesz; /* Size of line in bytes */
52 unsigned short ways; /* Number of ways */
53 unsigned short sets; /* Number of lines per set */
54 unsigned int waysize; /* Bytes per way */
55 unsigned int waybit; /* Bits to select in a cache set */
56 unsigned int flags; /* Flags describing cache properties */
57 };
58
59 /*
60 * Flag definitions
61 */
62 #define MIPS_CACHE_NOT_PRESENT 0x00000001
63 #define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
64 #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
65 #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
66
67 struct cpuinfo_mips {
68 unsigned long udelay_val;
69 unsigned long *pgd_quick;
70 unsigned long *pmd_quick;
71 unsigned long *pte_quick;
72 unsigned long pgtable_cache_sz;
73 unsigned long asid_cache;
74 #if defined(CONFIG_SGI_IP27)
75 cpuid_t p_cpuid; /* PROM assigned cpuid */
76 cnodeid_t p_nodeid; /* my node ID in compact-id-space */
77 nasid_t p_nasid; /* my node ID in numa-as-id-space */
78 unsigned char p_slice; /* Physical position on node board */
79 hub_intmasks_t p_intmasks; /* SN0 per-CPU interrupt masks */
80 #endif
81 #if 0
82 unsigned long loops_per_sec;
83 unsigned long pgtable_cache_sz;
84 unsigned long ipi_count;
85 unsigned long irq_attempt[NR_IRQS];
86 unsigned long smp_local_irq_count;
87 unsigned long prof_multiplier;
88 unsigned long prof_counter;
89 #endif
90
91 /*
92 * Capability and feature descriptor structure for MIPS CPU
93 */
94 unsigned long options;
95 unsigned int processor_id;
96 unsigned int fpu_id;
97 unsigned int cputype;
98 int isa_level;
99 int tlbsize;
100 struct cache_desc icache; /* Primary I-cache */
101 struct cache_desc dcache; /* Primary D or combined I/D cache */
102 struct cache_desc scache; /* Secondary cache */
103 struct cache_desc tcache; /* Tertiary/split secondary cache */
104 } __attribute__((aligned(SMP_CACHE_BYTES)));
105
106 /*
107 * Assumption: Options of CPU 0 are a superset of all processors.
108 * This is true for all known MIPS systems.
109 */
110 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
111 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
112 #define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB)
113 #define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
114 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
115 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
116 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
117 #define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16)
118 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
119 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
120 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
121 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
122 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
123 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
124 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
125 #define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
126 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
127 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
128 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
129 #define cpu_has_ic_fills_f_dc (cpu_data[0].dcache.flags & MIPS_CACHE_IC_F_DC)
130 #define cpu_has_64bits 1
131 #define cpu_has_64bit_zero_reg 1
132 #define cpu_has_64bit_gp_regs 1
133 #define cpu_has_64bit_addresses 1
134 #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
135
136 #define cpu_dcache_line_size() current_cpu_data.dcache.linesz
137 #define cpu_icache_line_size() current_cpu_data.icache.linesz
138 #define cpu_scache_line_size() current_cpu_data.scache.linesz
139
140 extern struct cpuinfo_mips cpu_data[];
141 #define current_cpu_data cpu_data[smp_processor_id()]
142
143 extern void cpu_probe(void);
144 extern void cpu_report(void);
145
146 /*
147 * System setup and hardware flags..
148 */
149 extern void (*cpu_wait)(void);
150
151 extern unsigned int vced_count, vcei_count;
152
153 /*
154 * Bus types (default is ISA, but people can check others with these..)
155 */
156 #ifdef CONFIG_EISA
157 extern int EISA_bus;
158 #else
159 #define EISA_bus (0)
160 #endif
161
162 #define MCA_bus 0
163 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
164
165 /*
166 * User space process size: 1TB. This is hardcoded into a few places,
167 * so don't change it unless you know what you are doing. TASK_SIZE
168 * is limited to 1TB by the R4000 architecture; R10000 and better can
169 * support 16TB.
170 */
171 #define TASK_SIZE32 0x7fff8000UL
172 #define TASK_SIZE 0x10000000000UL
173
174 /* This decides where the kernel will search for a free chunk of vm
175 * space during mmap's.
176 */
177 #define TASK_UNMAPPED_BASE ((current->thread.mflags & MF_32BIT_ADDR) ? \
178 (TASK_SIZE32 / 3) : (TASK_SIZE / 3))
179
180 /*
181 * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
182 */
183 #define IO_BITMAP_SIZE 32
184
185 #define NUM_FPU_REGS 32
186
187 struct mips_fpu_hard_struct {
188 unsigned long fp_regs[NUM_FPU_REGS];
189 unsigned int control;
190 };
191
192 /*
193 * It would be nice to add some more fields for emulator statistics, but there
194 * are a number of fixed offsets in offset.h and elsewhere that would have to
195 * be recalculated by hand. So the additional information will be private to
196 * the FPU emulator for now. See asm-mips/fpu_emulator.h.
197 */
198 typedef u64 fpureg_t;
199 struct mips_fpu_soft_struct {
200 fpureg_t regs[NUM_FPU_REGS];
201 unsigned int sr;
202 };
203
204 union mips_fpu_union {
205 struct mips_fpu_hard_struct hard;
206 struct mips_fpu_soft_struct soft;
207 };
208
209 #define INIT_FPU { \
210 {{0,},} \
211 }
212
213 typedef struct {
214 unsigned long seg;
215 } mm_segment_t;
216
217 /*
218 * If you change thread_struct remember to change the #defines below too!
219 */
220 struct thread_struct {
221 /* Saved main processor registers. */
222 unsigned long reg16;
223 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
224 unsigned long reg29, reg30, reg31;
225
226 /* Saved cp0 stuff. */
227 unsigned long cp0_status;
228
229 /* Saved fpu/fpu emulator stuff. */
230 union mips_fpu_union fpu;
231
232 /* Other stuff associated with the thread. */
233 unsigned long cp0_badvaddr; /* Last user fault */
234 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
235 unsigned long error_code;
236 unsigned long trap_no;
237 #define MF_FIXADE 1 /* Fix address errors in software */
238 #define MF_LOGADE 2 /* Log address errors to syslog */
239 #define MF_32BIT_REGS 4 /* also implies 16/32 fprs */
240 #define MF_32BIT_ADDR 8 /* 32-bit address space (o32/n32) */
241 unsigned long mflags;
242 mm_segment_t current_ds;
243 unsigned long irix_trampoline; /* Wheee... */
244 unsigned long irix_oldctx;
245 };
246
247 #define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR)
248 #define MF_O32 (MF_32BIT_REGS | MF_32BIT_ADDR)
249 #define MF_N32 MF_32BIT_ADDR
250 #define MF_N64 0
251
252 #endif /* !__ASSEMBLY__ */
253
254 #define INIT_THREAD { \
255 /* \
256 * saved main processor registers \
257 */ \
258 0, 0, 0, 0, 0, 0, 0, 0, \
259 0, 0, 0, \
260 /* \
261 * saved cp0 stuff \
262 */ \
263 0, \
264 /* \
265 * saved fpu/fpu emulator stuff \
266 */ \
267 INIT_FPU, \
268 /* \
269 * Other stuff associated with the process \
270 */ \
271 0, 0, 0, 0, \
272 /* \
273 * For now the default is to fix address errors \
274 */ \
275 MF_FIXADE, KERNEL_DS, 0, 0 \
276 }
277
278 #ifdef __KERNEL__
279
280 #define KERNEL_STACK_SIZE 0x4000
281
282 #ifndef __ASSEMBLY__
283
284 /* Free all resources held by a thread. */
285 #define release_thread(thread) do { } while(0)
286
287 extern int arch_kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
288
289 /* Copy and release all segment info associated with a VM */
290 #define copy_segments(p, mm) do { } while(0)
291 #define release_segments(mm) do { } while(0)
292
293 struct mips_frame_info {
294 int frame_offset;
295 int pc_offset;
296 };
297 extern struct mips_frame_info schedule_frame;
298 /*
299 * Return saved PC of a blocked thread.
300 */
thread_saved_pc(struct thread_struct * t)301 static inline unsigned long thread_saved_pc(struct thread_struct *t)
302 {
303 extern void ret_from_sys_call(void);
304
305 /* New born processes are a special case */
306 if (t->reg31 == (unsigned long) ret_from_sys_call)
307 return t->reg31;
308
309 if (schedule_frame.pc_offset < 0)
310 return 0;
311 return ((unsigned long *)t->reg29)[schedule_frame.pc_offset];
312 }
313
314 #define user_mode(regs) (((regs)->cp0_status & ST0_KSU) == KSU_USER)
315
316 /*
317 * Do necessary setup to start up a newly executed thread.
318 */
319 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
320
321 struct task_struct;
322 unsigned long get_wchan(struct task_struct *p);
323
324 #define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs))
325 #define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32)
326 #define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc)))
327 #define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29])))
328 #define KSTK_STATUS(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_status)))
329
330 /* Allocation and freeing of basic task resources. */
331 /*
332 * NOTE! The task struct and the stack go together
333 */
334 #define THREAD_ORDER (PAGE_SHIFT >= 14 ? 0 : 2)
335 #define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER)
336 #define THREAD_MASK (THREAD_SIZE - 1UL)
337 #define alloc_task_struct() \
338 ((struct task_struct *) __get_free_pages(GFP_KERNEL, THREAD_ORDER))
339 #define free_task_struct(p) free_pages((unsigned long)(p), THREAD_ORDER)
340 #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
341
342 #define init_task (init_task_union.task)
343 #define init_stack (init_task_union.stack)
344
345 #define cpu_relax() barrier()
346
347 #endif /* !__ASSEMBLY__ */
348 #endif /* __KERNEL__ */
349
350 /*
351 * Return_address is a replacement for __builtin_return_address(count)
352 * which on certain architectures cannot reasonably be implemented in GCC
353 * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
354 * Note that __builtin_return_address(x>=1) is forbidden because GCC
355 * aborts compilation on some CPUs. It's simply not possible to unwind
356 * some CPU's stackframes.
357 *
358 * __builtin_return_address works only for non-leaf functions. We avoid the
359 * overhead of a function call by forcing the compiler to save the return
360 * address register on the stack.
361 */
362 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
363
364 #endif /* _ASM_PROCESSOR_H */
365