1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 2002 by Ralf Baechle 7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. 8 * Copyright (C) 2002 Maciej W. Rozycki 9 */ 10 #ifndef _ASM_PGTABLE_BITS_H 11 #define _ASM_PGTABLE_BITS_H 12 13 #include <linux/config.h> 14 15 /* 16 * Note that we shift the lower 32bits of each EntryLo[01] entry 17 * 6 bits to the left. That way we can convert the PFN into the 18 * physical address by a single 'and' operation and gain 6 additional 19 * bits for storing information which isn't present in a normal 20 * MIPS page table. 21 * 22 * Similar to the Alpha port, we need to keep track of the ref 23 * and mod bits in software. We have a software "yeah you can read 24 * from this page" bit, and a hardware one which actually lets the 25 * process read from the page. On the same token we have a software 26 * writable bit and the real hardware one which actually lets the 27 * process write to the page, this keeps a mod bit via the hardware 28 * dirty bit. 29 * 30 * Certain revisions of the R4000 and R5000 have a bug where if a 31 * certain sequence occurs in the last 3 instructions of an executable 32 * page, and the following page is not mapped, the cpu can do 33 * unpredictable things. The code (when it is written) to deal with 34 * this problem will be in the update_mmu_cache() code for the r4k. 35 */ 36 #define _PAGE_PRESENT (1<<0) /* implemented in software */ 37 #define _PAGE_READ (1<<1) /* implemented in software */ 38 #define _PAGE_WRITE (1<<2) /* implemented in software */ 39 #define _PAGE_ACCESSED (1<<3) /* implemented in software */ 40 #define _PAGE_MODIFIED (1<<4) /* implemented in software */ 41 42 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 43 44 #define _PAGE_GLOBAL (1<<8) 45 #define _PAGE_VALID (1<<9) 46 #define _PAGE_SILENT_READ (1<<9) /* synonym */ 47 #define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */ 48 #define _PAGE_SILENT_WRITE (1<<10) 49 #define _CACHE_UNCACHED (1<<11) 50 #define _CACHE_MASK (1<<11) 51 #define _CACHE_CACHABLE_NONCOHERENT 0 52 53 #else 54 #define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ 55 #define _PAGE_GLOBAL (1<<6) 56 #define _PAGE_VALID (1<<7) 57 #define _PAGE_SILENT_READ (1<<7) /* synonym */ 58 #define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ 59 #define _PAGE_SILENT_WRITE (1<<8) 60 #define _CACHE_MASK (7<<9) 61 62 #if defined(CONFIG_CPU_SB1) 63 64 /* No penalty for being coherent on the SB1, so just 65 use it for "noncoherent" spaces, too. Shouldn't hurt. */ 66 67 #define _CACHE_UNCACHED (2<<9) 68 #define _CACHE_CACHABLE_COW (5<<9) 69 #define _CACHE_CACHABLE_NONCOHERENT (5<<9) 70 #define _CACHE_UNCACHED_ACCELERATED (7<<9) 71 72 #else 73 74 #define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */ 75 #define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ 76 #define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ 77 #define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ 78 #define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */ 79 #define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */ 80 #define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */ 81 #define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ 82 83 #endif 84 #endif 85 86 #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) 87 #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 88 89 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) 90 91 #ifdef CONFIG_MIPS_UNCACHED 92 #define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED 93 #elif defined(CONFIG_NONCOHERENT_IO) 94 #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT 95 #else 96 #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW 97 #endif 98 99 #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) 100 101 #endif /* _ASM_PGTABLE_BITS_H */ 102