1 /*
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 *
7 * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
8 * and can only be used for expansion cards. Onboard DMA controllers, such
9 * as the R4030 on Jazz boards behave totally different!
10 */
11
12 #ifndef _ASM_DMA_H
13 #define _ASM_DMA_H
14
15 #include <linux/config.h>
16 #include <asm/io.h> /* need byte IO */
17 #include <linux/spinlock.h> /* And spinlocks */
18 #include <linux/delay.h>
19 #include <asm/system.h>
20
21
22 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
23 #define dma_outb outb_p
24 #else
25 #define dma_outb outb
26 #endif
27
28 #define dma_inb inb
29
30 /*
31 * NOTES about DMA transfers:
32 *
33 * controller 1: channels 0-3, byte operations, ports 00-1F
34 * controller 2: channels 4-7, word operations, ports C0-DF
35 *
36 * - ALL registers are 8 bits only, regardless of transfer size
37 * - channel 4 is not used - cascades 1 into 2.
38 * - channels 0-3 are byte - addresses/counts are for physical bytes
39 * - channels 5-7 are word - addresses/counts are for physical words
40 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
41 * - transfer count loaded to registers is 1 less than actual count
42 * - controller 2 offsets are all even (2x offsets for controller 1)
43 * - page registers for 5-7 don't use data bit 0, represent 128K pages
44 * - page registers for 0-3 use bit 0, represent 64K pages
45 *
46 * DMA transfers are limited to the lower 16MB of _physical_ memory.
47 * Note that addresses loaded into registers must be _physical_ addresses,
48 * not logical addresses (which may differ if paging is active).
49 *
50 * Address mapping for channels 0-3:
51 *
52 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
53 * | ... | | ... | | ... |
54 * | ... | | ... | | ... |
55 * | ... | | ... | | ... |
56 * P7 ... P0 A7 ... A0 A7 ... A0
57 * | Page | Addr MSB | Addr LSB | (DMA registers)
58 *
59 * Address mapping for channels 5-7:
60 *
61 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
62 * | ... | \ \ ... \ \ \ ... \ \
63 * | ... | \ \ ... \ \ \ ... \ (not used)
64 * | ... | \ \ ... \ \ \ ... \
65 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
66 * | Page | Addr MSB | Addr LSB | (DMA registers)
67 *
68 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
69 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
70 * the hardware level, so odd-byte transfers aren't possible).
71 *
72 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
73 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
74 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
75 *
76 */
77
78 #define MAX_DMA_CHANNELS 8
79
80 /*
81 * The maximum address in KSEG0 that we can perform a DMA transfer to on this
82 * platform. This describes only the PC style part of the DMA logic like on
83 * Deskstations or Acer PICA but not the much more versatile DMA logic used
84 * for the local devices on Acer PICA or Magnums.
85 */
86 #ifdef CONFIG_SGI_IP22
87 /* Horrible hack to have a correct DMA window on IP22 */
88 #include <asm/sgi/mc.h>
89 #define MAX_DMA_ADDRESS (PAGE_OFFSET + SGIMC_SEG0_BADDR + 0x01000000)
90 #else
91 #define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
92 #endif
93
94 /* 8237 DMA controllers */
95 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
96 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
97
98 /* DMA controller registers */
99 #define DMA1_CMD_REG 0x08 /* command register (w) */
100 #define DMA1_STAT_REG 0x08 /* status register (r) */
101 #define DMA1_REQ_REG 0x09 /* request register (w) */
102 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
103 #define DMA1_MODE_REG 0x0B /* mode register (w) */
104 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
105 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
106 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
107 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
108 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
109
110 #define DMA2_CMD_REG 0xD0 /* command register (w) */
111 #define DMA2_STAT_REG 0xD0 /* status register (r) */
112 #define DMA2_REQ_REG 0xD2 /* request register (w) */
113 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
114 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
115 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
116 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
117 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
118 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
119 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
120
121 #define DMA_ADDR_0 0x00 /* DMA address registers */
122 #define DMA_ADDR_1 0x02
123 #define DMA_ADDR_2 0x04
124 #define DMA_ADDR_3 0x06
125 #define DMA_ADDR_4 0xC0
126 #define DMA_ADDR_5 0xC4
127 #define DMA_ADDR_6 0xC8
128 #define DMA_ADDR_7 0xCC
129
130 #define DMA_CNT_0 0x01 /* DMA count registers */
131 #define DMA_CNT_1 0x03
132 #define DMA_CNT_2 0x05
133 #define DMA_CNT_3 0x07
134 #define DMA_CNT_4 0xC2
135 #define DMA_CNT_5 0xC6
136 #define DMA_CNT_6 0xCA
137 #define DMA_CNT_7 0xCE
138
139 #define DMA_PAGE_0 0x87 /* DMA page registers */
140 #define DMA_PAGE_1 0x83
141 #define DMA_PAGE_2 0x81
142 #define DMA_PAGE_3 0x82
143 #define DMA_PAGE_5 0x8B
144 #define DMA_PAGE_6 0x89
145 #define DMA_PAGE_7 0x8A
146
147 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
148 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
149 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
150
151 #define DMA_AUTOINIT 0x10
152
153 extern spinlock_t dma_spin_lock;
154
claim_dma_lock(void)155 static __inline__ unsigned long claim_dma_lock(void)
156 {
157 unsigned long flags;
158 spin_lock_irqsave(&dma_spin_lock, flags);
159 return flags;
160 }
161
release_dma_lock(unsigned long flags)162 static __inline__ void release_dma_lock(unsigned long flags)
163 {
164 spin_unlock_irqrestore(&dma_spin_lock, flags);
165 }
166
167 /* enable/disable a specific DMA channel */
enable_dma(unsigned int dmanr)168 static __inline__ void enable_dma(unsigned int dmanr)
169 {
170 if (dmanr<=3)
171 dma_outb(dmanr, DMA1_MASK_REG);
172 else
173 dma_outb(dmanr & 3, DMA2_MASK_REG);
174 }
175
disable_dma(unsigned int dmanr)176 static __inline__ void disable_dma(unsigned int dmanr)
177 {
178 if (dmanr<=3)
179 dma_outb(dmanr | 4, DMA1_MASK_REG);
180 else
181 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
182 }
183
184 /* Clear the 'DMA Pointer Flip Flop'.
185 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
186 * Use this once to initialize the FF to a known state.
187 * After that, keep track of it. :-)
188 * --- In order to do that, the DMA routines below should ---
189 * --- only be used while holding the DMA lock ! ---
190 */
clear_dma_ff(unsigned int dmanr)191 static __inline__ void clear_dma_ff(unsigned int dmanr)
192 {
193 if (dmanr<=3)
194 dma_outb(0, DMA1_CLEAR_FF_REG);
195 else
196 dma_outb(0, DMA2_CLEAR_FF_REG);
197 }
198
199 /* set mode (above) for a specific DMA channel */
set_dma_mode(unsigned int dmanr,char mode)200 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
201 {
202 if (dmanr<=3)
203 dma_outb(mode | dmanr, DMA1_MODE_REG);
204 else
205 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
206 }
207
208 /* Set only the page register bits of the transfer address.
209 * This is used for successive transfers when we know the contents of
210 * the lower 16 bits of the DMA current address register, but a 64k boundary
211 * may have been crossed.
212 */
set_dma_page(unsigned int dmanr,char pagenr)213 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
214 {
215 switch(dmanr) {
216 case 0:
217 dma_outb(pagenr, DMA_PAGE_0);
218 break;
219 case 1:
220 dma_outb(pagenr, DMA_PAGE_1);
221 break;
222 case 2:
223 dma_outb(pagenr, DMA_PAGE_2);
224 break;
225 case 3:
226 dma_outb(pagenr, DMA_PAGE_3);
227 break;
228 case 5:
229 dma_outb(pagenr & 0xfe, DMA_PAGE_5);
230 break;
231 case 6:
232 dma_outb(pagenr & 0xfe, DMA_PAGE_6);
233 break;
234 case 7:
235 dma_outb(pagenr & 0xfe, DMA_PAGE_7);
236 break;
237 }
238 }
239
240
241 /* Set transfer address & page bits for specific DMA channel.
242 * Assumes dma flipflop is clear.
243 */
set_dma_addr(unsigned int dmanr,unsigned int a)244 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
245 {
246 set_dma_page(dmanr, a>>16);
247 if (dmanr <= 3) {
248 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
249 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
250 } else {
251 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
252 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
253 }
254 }
255
256
257 /* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
258 * a specific DMA channel.
259 * You must ensure the parameters are valid.
260 * NOTE: from a manual: "the number of transfers is one more
261 * than the initial word count"! This is taken into account.
262 * Assumes dma flip-flop is clear.
263 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
264 */
set_dma_count(unsigned int dmanr,unsigned int count)265 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
266 {
267 count--;
268 if (dmanr <= 3) {
269 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
270 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
271 } else {
272 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
273 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
274 }
275 }
276
277
278 /* Get DMA residue count. After a DMA transfer, this
279 * should return zero. Reading this while a DMA transfer is
280 * still in progress will return unpredictable results.
281 * If called before the channel has been used, it may return 1.
282 * Otherwise, it returns the number of _bytes_ left to transfer.
283 *
284 * Assumes DMA flip-flop is clear.
285 */
get_dma_residue(unsigned int dmanr)286 static __inline__ int get_dma_residue(unsigned int dmanr)
287 {
288 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
289 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
290
291 /* using short to get 16-bit wrap around */
292 unsigned short count;
293
294 count = 1 + dma_inb(io_port);
295 count += dma_inb(io_port) << 8;
296
297 return (dmanr<=3)? count : (count<<1);
298 }
299
300
301 /* These are in kernel/dma.c: */
302 extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
303 extern void free_dma(unsigned int dmanr); /* release it again */
304
305 /* From PCI */
306
307 #ifdef CONFIG_PCI
308 extern int isa_dma_bridge_buggy;
309 #else
310 #define isa_dma_bridge_buggy (0)
311 #endif
312
313 #endif /* _ASM_DMA_H */
314