1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 */
11 #ifndef _ASM_PROCESSOR_H
12 #define _ASM_PROCESSOR_H
13
14 #include <linux/config.h>
15 #include <linux/cache.h>
16 #include <asm/isadep.h>
17
18 /*
19 * Return current * instruction pointer ("program counter").
20 */
21 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
22
23 #ifndef __ASSEMBLY__
24 #include <linux/smp.h>
25 #include <linux/threads.h>
26
27 #include <asm/cachectl.h>
28 #include <asm/cpu.h>
29 #include <asm/mipsregs.h>
30 #include <asm/reg.h>
31 #include <asm/system.h>
32
33 /*
34 * Descriptor for a cache
35 */
36 struct cache_desc {
37 unsigned short linesz; /* Size of line in bytes */
38 unsigned short ways; /* Number of ways */
39 unsigned short sets; /* Number of lines per set */
40 unsigned int waysize; /* Bytes per way */
41 unsigned int waybit; /* Bits to select in a cache set */
42 unsigned int flags; /* Flags describing cache properties */
43 };
44
45 /*
46 * Flag definitions
47 */
48 #define MIPS_CACHE_NOT_PRESENT 0x00000001
49 #define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
50 #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
51 #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
52
53 struct cpuinfo_mips {
54 unsigned long udelay_val;
55 unsigned long *pgd_quick;
56 unsigned long *pte_quick;
57 unsigned long pgtable_cache_sz;
58 unsigned long asid_cache;
59 /*
60 * Capability and feature descriptor structure for MIPS CPU
61 */
62 unsigned long options;
63 unsigned int processor_id;
64 unsigned int fpu_id;
65 unsigned int cputype;
66 int isa_level;
67 int tlbsize;
68 struct cache_desc icache; /* Primary I-cache */
69 struct cache_desc dcache; /* Primary D or combined I/D cache */
70 struct cache_desc scache; /* Secondary cache */
71 struct cache_desc tcache; /* Tertiary/split secondary cache */
72 } __attribute__((aligned(SMP_CACHE_BYTES)));
73
74 /*
75 * Assumption: Options of CPU 0 are a superset of all processors.
76 * This is true for all known MIPS systems.
77 */
78 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
79 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
80 #define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB)
81 #define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
82 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
83 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
84 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
85 #define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16)
86 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
87 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
88 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
89 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
90 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
91 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
92 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
93 #define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
94 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
95 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
96 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
97 #define cpu_has_ic_fills_f_dc (cpu_data[0].dcache.flags & MIPS_CACHE_IC_F_DC)
98 #define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
99 #define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
100 #define cpu_has_64bit_gp_regs 0
101 #define cpu_has_64bit_addresses 0
102 #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
103
104 #define cpu_dcache_line_size() current_cpu_data.dcache.linesz
105 #define cpu_icache_line_size() current_cpu_data.icache.linesz
106 #define cpu_scache_line_size() current_cpu_data.scache.linesz
107
108 extern struct cpuinfo_mips cpu_data[];
109 #define current_cpu_data cpu_data[smp_processor_id()]
110
111 extern void cpu_probe(void);
112 extern void cpu_report(void);
113
114 /*
115 * System setup and hardware flags..
116 */
117 extern void (*cpu_wait)(void);
118
119 extern unsigned int vced_count, vcei_count;
120
121 /*
122 * Bus types (default is ISA, but people can check others with these..)
123 */
124 #ifdef CONFIG_EISA
125 extern int EISA_bus;
126 #else
127 #define EISA_bus (0)
128 #endif
129
130 #define MCA_bus 0
131 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
132
133 /*
134 * User space process size: 2GB. This is hardcoded into a few places,
135 * so don't change it unless you know what you are doing. TASK_SIZE
136 * for a 64 bit kernel expandable to 8192EB, of which the current MIPS
137 * implementations will "only" be able to use 1TB ...
138 */
139 #define TASK_SIZE 0x7fff8000UL
140
141 /* This decides where the kernel will search for a free chunk of vm
142 * space during mmap's.
143 */
144 #define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
145
146 /*
147 * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
148 */
149 #define IO_BITMAP_SIZE 32
150
151 #define NUM_FPU_REGS 32
152
153 struct mips_fpu_hard_struct {
154 double fp_regs[NUM_FPU_REGS];
155 unsigned int control;
156 };
157
158 /*
159 * It would be nice to add some more fields for emulator statistics, but there
160 * are a number of fixed offsets in offset.h and elsewhere that would have to
161 * be recalculated by hand. So the additional information will be private to
162 * the FPU emulator for now. See asm-mips/fpu_emulator.h.
163 */
164 typedef u64 fpureg_t;
165 struct mips_fpu_soft_struct {
166 fpureg_t regs[NUM_FPU_REGS];
167 unsigned int sr;
168 };
169
170 union mips_fpu_union {
171 struct mips_fpu_hard_struct hard;
172 struct mips_fpu_soft_struct soft;
173 };
174
175 #define INIT_FPU { \
176 {{0,},} \
177 }
178
179 typedef struct {
180 unsigned long seg;
181 } mm_segment_t;
182
183 /*
184 * If you change thread_struct remember to change the #defines below too!
185 */
186 struct thread_struct {
187 /* Saved main processor registers. */
188 unsigned long reg16;
189 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
190 unsigned long reg29, reg30, reg31;
191
192 /* Saved cp0 stuff. */
193 unsigned long cp0_status;
194
195 /* Saved fpu/fpu emulator stuff. */
196 union mips_fpu_union fpu;
197
198 /* Other stuff associated with the thread. */
199 unsigned long cp0_badvaddr; /* Last user fault */
200 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
201 unsigned long error_code;
202 unsigned long trap_no;
203 #define MF_FIXADE 1 /* Fix address errors in software */
204 #define MF_LOGADE 2 /* Log address errors to syslog */
205 unsigned long mflags;
206 mm_segment_t current_ds;
207 unsigned long irix_trampoline; /* Wheee... */
208 unsigned long irix_oldctx;
209 };
210
211 #endif /* !__ASSEMBLY__ */
212
213 #define INIT_THREAD { \
214 /* \
215 * saved main processor registers \
216 */ \
217 0, 0, 0, 0, 0, 0, 0, 0, \
218 0, 0, 0, \
219 /* \
220 * saved cp0 stuff \
221 */ \
222 0, \
223 /* \
224 * saved fpu/fpu emulator stuff \
225 */ \
226 INIT_FPU, \
227 /* \
228 * Other stuff associated with the process \
229 */ \
230 0, 0, 0, 0, \
231 /* \
232 * For now the default is to fix address errors \
233 */ \
234 MF_FIXADE, { 0 }, 0, 0 \
235 }
236
237 #ifdef __KERNEL__
238
239 #define KERNEL_STACK_SIZE 0x2000
240
241 #ifndef __ASSEMBLY__
242
243 /* Free all resources held by a thread. */
244 #define release_thread(thread) do { } while(0)
245
246 extern int arch_kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
247
248 /* Copy and release all segment info associated with a VM */
249 #define copy_segments(p, mm) do { } while(0)
250 #define release_segments(mm) do { } while(0)
251
252 struct mips_frame_info {
253 int frame_offset;
254 int pc_offset;
255 };
256 extern struct mips_frame_info schedule_frame;
257 /*
258 * Return saved PC of a blocked thread.
259 */
thread_saved_pc(struct thread_struct * t)260 static inline unsigned long thread_saved_pc(struct thread_struct *t)
261 {
262 extern void ret_from_fork(void);
263
264 /* New born processes are a special case */
265 if (t->reg31 == (unsigned long) ret_from_fork)
266 return t->reg31;
267
268 if (schedule_frame.pc_offset < 0)
269 return 0;
270 return ((unsigned long *)t->reg29)[schedule_frame.pc_offset];
271 }
272
273 /*
274 * Do necessary setup to start up a newly executed thread.
275 */
276 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
277
278 struct task_struct;
279 unsigned long get_wchan(struct task_struct *p);
280
281 #define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs))
282 #define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32)
283 #define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc)))
284 #define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29])))
285 #define KSTK_STATUS(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_status)))
286
287 /* Allocation and freeing of basic task resources. */
288 /*
289 * NOTE! The task struct and the stack go together
290 */
291 #define THREAD_ORDER (PAGE_SHIFT >= 14 ? 0 : 1)
292 #define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER)
293 #define THREAD_MASK (THREAD_SIZE - 1UL)
294 #define alloc_task_struct() \
295 ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
296 #define free_task_struct(p) free_pages((unsigned long)(p),1)
297 #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
298
299 #define init_task (init_task_union.task)
300 #define init_stack (init_task_union.stack)
301
302 #define cpu_relax() barrier()
303
304 #endif /* !__ASSEMBLY__ */
305 #endif /* __KERNEL__ */
306
307 /*
308 * Return_address is a replacement for __builtin_return_address(count)
309 * which on certain architectures cannot reasonably be implemented in GCC
310 * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
311 * Note that __builtin_return_address(x>=1) is forbidden because GCC
312 * aborts compilation on some CPUs. It's simply not possible to unwind
313 * some CPU's stackframes.
314 *
315 * __builtin_return_address works only for non-leaf functions. We avoid the
316 * overhead of a function call by forcing the compiler to save the return
317 * address register on the stack.
318 */
319 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
320
321 #endif /* _ASM_PROCESSOR_H */
322