1 #ifndef _MIPS_PGTABLE_64_H
2 #define _MIPS_PGTABLE_64_H
3
4 /*
5 * Not really a 3 level page table but we follow most of the x86 PAE code.
6 */
7
8 #define PMD_SHIFT 21
9 #define PGD_ORDER 1
10 #define PTE_ORDER 0
11
12 #if !defined (_LANGUAGE_ASSEMBLY)
13 #define pte_ERROR(e) \
14 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, (e).pte_low)
15 #define pmd_ERROR(e) \
16 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
17 #define pgd_ERROR(e) \
18 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
19
pte_none(pte_t pte)20 static inline int pte_none(pte_t pte) { return !(pte_val(pte) & ~_PAGE_GLOBAL); }
21
pte_same(pte_t a,pte_t b)22 static inline int pte_same(pte_t a, pte_t b)
23 {
24 return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
25 }
26
27
pte_wrprotect(pte_t pte)28 static inline pte_t pte_wrprotect(pte_t pte)
29 {
30 (pte).pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
31 (pte).pte_high &= ~_PAGE_SILENT_WRITE;
32 return pte;
33 }
34
pte_rdprotect(pte_t pte)35 static inline pte_t pte_rdprotect(pte_t pte)
36 {
37 (pte).pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ);
38 (pte).pte_high &= ~_PAGE_SILENT_READ;
39 return pte;
40 }
41
pte_mkclean(pte_t pte)42 static inline pte_t pte_mkclean(pte_t pte)
43 {
44 (pte).pte_low &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
45 (pte).pte_high &= ~_PAGE_SILENT_WRITE;
46 return pte;
47 }
48
pte_mkold(pte_t pte)49 static inline pte_t pte_mkold(pte_t pte)
50 {
51 (pte).pte_low &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
52 (pte).pte_high &= ~_PAGE_SILENT_READ;
53 return pte;
54 }
55
pte_mkwrite(pte_t pte)56 static inline pte_t pte_mkwrite(pte_t pte)
57 {
58 (pte).pte_low |= _PAGE_WRITE;
59 if ((pte).pte_low & _PAGE_MODIFIED) {
60 (pte).pte_low |= _PAGE_SILENT_WRITE;
61 (pte).pte_high |= _PAGE_SILENT_WRITE;
62 }
63 return pte;
64 }
65
pte_mkread(pte_t pte)66 static inline pte_t pte_mkread(pte_t pte)
67 {
68 (pte).pte_low |= _PAGE_READ;
69 if ((pte).pte_low & _PAGE_ACCESSED) {
70 (pte).pte_low |= _PAGE_SILENT_READ;
71 (pte).pte_high |= _PAGE_SILENT_READ;
72 }
73 return pte;
74 }
75
pte_mkdirty(pte_t pte)76 static inline pte_t pte_mkdirty(pte_t pte)
77 {
78 (pte).pte_low |= _PAGE_MODIFIED;
79 if ((pte).pte_low & _PAGE_WRITE) {
80 (pte).pte_low |= _PAGE_SILENT_WRITE;
81 (pte).pte_high |= _PAGE_SILENT_WRITE;
82 }
83 return pte;
84 }
85
86 /*
87 * Macro to make mark a page protection value as "uncacheable". Note
88 * that "protection" is really a misnomer here as the protection value
89 * contains the memory attribute bits, dirty bits, and various other
90 * bits as well.
91 */
92 #define pgprot_noncached pgprot_noncached
93
pgprot_noncached(pgprot_t _prot)94 static inline pgprot_t pgprot_noncached(pgprot_t _prot)
95 {
96 unsigned long prot = pgprot_val(_prot);
97
98 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
99
100 return __pgprot(prot);
101 }
102
pte_mkyoung(pte_t pte)103 static inline pte_t pte_mkyoung(pte_t pte)
104 {
105 (pte).pte_low |= _PAGE_ACCESSED;
106 if ((pte).pte_low & _PAGE_READ)
107 (pte).pte_low |= _PAGE_SILENT_READ;
108 (pte).pte_high |= _PAGE_SILENT_READ;
109 return pte;
110 }
111
112 /*
113 * Conversion functions: convert a page and protection to a page entry,
114 * and a page entry and page directory to the page they refer to.
115 */
116 #define mk_pte(page, pgprot) __mk_pte((page) - mem_map, (pgprot))
117 #define mk_pte_phys(physpage, pgprot) __mk_pte((physpage) >> PAGE_SHIFT, pgprot)
118
pte_modify(pte_t pte,pgprot_t newprot)119 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
120 {
121 pte.pte_low &= _PAGE_CHG_MASK;
122 pte.pte_low |= pgprot_val(newprot);
123 pte.pte_high |= pgprot_val(newprot) & 0x3f;
124 return pte;
125 }
126
127 #define pte_page(x) (mem_map+(((x).pte_high >> 6)))
128
129 /*
130 * MIPS32 Note
131 * pte_low contains the 12 low bits only. This includes the 6 lsb bits
132 * which contain software control bits, and the next 6 attribute bits
133 * which are actually written in the entrylo[0,1] registers (G,V,D,Cache Mask).
134 * pte_high contains the 36 bit physical address and the 6 hardware
135 * attribute bits (G,V,D, Cache Mask). The entry is already fully setup
136 * so in the tlb refill handler we do not need to shift right 6.
137 */
138
139 /* Rules for using set_pte: the pte being assigned *must* be
140 * either not present or in a state where the hardware will
141 * not attempt to update the pte. In places where this is
142 * not possible, use pte_get_and_clear to obtain the old pte
143 * value and then use set_pte to update it. -ben
144 */
set_pte(pte_t * ptep,pte_t pte)145 static inline void set_pte(pte_t *ptep, pte_t pte)
146 {
147 ptep->pte_high = pte.pte_high;
148 smp_wmb();
149 ptep->pte_low = pte.pte_low;
150
151 if (pte_val(pte) & _PAGE_GLOBAL) {
152 pte_t *buddy = ptep_buddy(ptep);
153 /*
154 * Make sure the buddy is global too (if it's !none,
155 * it better already be global)
156 */
157 if (pte_none(*buddy))
158 buddy->pte_low |= _PAGE_GLOBAL;
159 }
160 }
161
162 static inline pte_t
__mk_pte(unsigned long page_nr,pgprot_t pgprot)163 __mk_pte(unsigned long page_nr, pgprot_t pgprot)
164 {
165 pte_t pte;
166
167 pte.pte_high = (page_nr << 6) | (pgprot_val(pgprot) & 0x3f);
168 pte.pte_low = pgprot_val(pgprot);
169 return pte;
170 }
171
pte_clear(pte_t * ptep)172 static inline void pte_clear(pte_t *ptep)
173 {
174 /* Preserve global status for the pair */
175 if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
176 set_pte(ptep, __pte(_PAGE_GLOBAL));
177 else
178 set_pte(ptep, __pte(0));
179 }
180
181 #endif
182
183 #endif /* _MIPS_PGTABLE_64_H */
184