1 /* 2 * Miscellaneous definitions used to initialise the interrupt vector table 3 * with the machine-specific interrupt routines. 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file "COPYING" in the main directory of this archive 7 * for more details. 8 * 9 * Copyright (C) 1997 by Paul M. Antoine. 10 * reworked 1998 by Harald Koerfgen. 11 * Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki 12 */ 13 14 #ifndef __ASM_DEC_INTERRUPTS_H 15 #define __ASM_DEC_INTERRUPTS_H 16 17 #include <asm/mipsregs.h> 18 19 20 /* 21 * The list of possible system devices which provide an 22 * interrupt. Not all devices exist on a given system. 23 */ 24 #define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */ 25 26 /* Ordinary interrupts */ 27 #define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */ 28 #define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */ 29 #define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */ 30 #define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */ 31 #define DEC_IRQ_FLOPPY 5 /* 82077 FDC */ 32 #define DEC_IRQ_FPU 6 /* R3k FPU */ 33 #define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */ 34 #define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */ 35 #define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */ 36 #define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */ 37 #define DEC_IRQ_PSU 11 /* power supply unit warning */ 38 #define DEC_IRQ_RTC 12 /* DS1287 RTC */ 39 #define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */ 40 #define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */ 41 #define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */ 42 #define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */ 43 #define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */ 44 #define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */ 45 #define DEC_IRQ_TIMER 19 /* ARC periodic timer */ 46 #define DEC_IRQ_VIDEO 20 /* framebuffer */ 47 48 /* I/O ASIC DMA interrupts */ 49 #define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */ 50 #define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */ 51 #define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */ 52 #define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */ 53 #define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */ 54 #define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */ 55 #define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */ 56 #define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */ 57 #define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */ 58 #define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */ 59 #define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */ 60 #define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */ 61 #define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */ 62 #define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */ 63 #define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */ 64 #define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */ 65 #define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */ 66 #define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */ 67 #define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */ 68 #define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */ 69 70 /* TC5 & TC6 are virtual slots for KN02's onboard devices */ 71 #define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */ 72 #define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */ 73 74 #define DEC_NR_INTS 41 75 76 77 /* Largest of cpu mask_nr tables. */ 78 #define DEC_MAX_CPU_INTS 6 79 /* Largest of asic mask_nr tables. */ 80 #define DEC_MAX_ASIC_INTS 9 81 82 83 /* 84 * CPU interrupt bits common to all systems. 85 */ 86 #define DEC_CPU_INR_FPU 7 /* R3k FPU */ 87 #define DEC_CPU_INR_SW1 1 /* software #1 */ 88 #define DEC_CPU_INR_SW0 0 /* software #0 */ 89 90 #define DEC_CPU_IRQ_BASE 0 /* first IRQ assigned to CPU */ 91 92 #define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE) 93 #define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP)) 94 #define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP) 95 96 97 #ifndef __ASSEMBLY__ 98 99 /* 100 * Interrupt table structures to hide differences between systems. 101 */ 102 typedef union { int i; void *p; } int_ptr; 103 extern int dec_interrupt[DEC_NR_INTS]; 104 extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2]; 105 extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2]; 106 extern int cpu_fpu_mask; 107 108 109 /* 110 * Common interrupt routine prototypes for all DECStations 111 */ 112 extern void kn02_io_int(void); 113 extern void kn02xa_io_int(void); 114 extern void kn03_io_int(void); 115 extern void asic_dma_int(void); 116 extern void asic_all_int(void); 117 extern void kn02_all_int(void); 118 extern void cpu_all_int(void); 119 120 extern void dec_intr_unimplemented(void); 121 extern void asic_intr_unimplemented(void); 122 123 #endif /* __ASSEMBLY__ */ 124 125 #endif 126