1 /* 2 * AMD Alchemy DB1x00 Reference Boards 3 * 4 * Copyright 2001 MontaVista Software Inc. 5 * Author: MontaVista Software, Inc. 6 * ppopov@mvista.com or source@mvista.com 7 * 8 * ######################################################################## 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 22 * 23 * ######################################################################## 24 * 25 * 26 */ 27 #ifndef __ASM_DB1X00_H 28 #define __ASM_DB1X00_H 29 30 #ifdef CONFIG_MIPS_DB1550 31 #define BCSR_KSEG1_ADDR 0xAF000000 32 #define NAND_PHYS_ADDR 0x20000000 33 #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 34 #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 35 #define SPI_PSC_BASE PSC0_BASE_ADDR 36 #define AC97_PSC_BASE PSC1_BASE_ADDR 37 #define SMBUS_PSC_BASE PSC2_BASE_ADDR 38 #define I2S_PSC_BASE PSC3_BASE_ADDR 39 40 #else 41 #define BCSR_KSEG1_ADDR 0xAE000000 42 #endif 43 44 /* 45 * Overlay data structure of the Db1x00 board registers. 46 * Registers located at physical 0E0000xx, KSEG1 0xAE0000xx 47 */ 48 typedef volatile struct 49 { 50 /*00*/ unsigned short whoami; 51 unsigned short reserved0; 52 /*04*/ unsigned short status; 53 unsigned short reserved1; 54 /*08*/ unsigned short switches; 55 unsigned short reserved2; 56 /*0C*/ unsigned short resets; 57 unsigned short reserved3; 58 /*10*/ unsigned short pcmcia; 59 unsigned short reserved4; 60 /*14*/ unsigned short specific; 61 unsigned short reserved5; 62 /*18*/ unsigned short leds; 63 unsigned short reserved6; 64 /*1C*/ unsigned short swreset; 65 unsigned short reserved7; 66 67 } BCSR; 68 69 70 /* 71 * Register/mask bit definitions for the BCSRs 72 */ 73 #define BCSR_WHOAMI_DCID 0x000F 74 #define BCSR_WHOAMI_CPLD 0x00F0 75 #define BCSR_WHOAMI_BOARD 0x0F00 76 77 #define BCSR_STATUS_PC0VS 0x0003 78 #define BCSR_STATUS_PC1VS 0x000C 79 #define BCSR_STATUS_PC0FI 0x0010 80 #define BCSR_STATUS_PC1FI 0x0020 81 #define BCSR_STATUS_FLASHBUSY 0x0100 82 #define BCSR_STATUS_ROMBUSY 0x0400 83 #define BCSR_STATUS_SWAPBOOT 0x2000 84 #define BCSR_STATUS_FLASHDEN 0xC000 85 86 #define BCSR_SWITCHES_DIP 0x00FF 87 #define BCSR_SWITCHES_DIP_1 0x0080 88 #define BCSR_SWITCHES_DIP_2 0x0040 89 #define BCSR_SWITCHES_DIP_3 0x0020 90 #define BCSR_SWITCHES_DIP_4 0x0010 91 #define BCSR_SWITCHES_DIP_5 0x0008 92 #define BCSR_SWITCHES_DIP_6 0x0004 93 #define BCSR_SWITCHES_DIP_7 0x0002 94 #define BCSR_SWITCHES_DIP_8 0x0001 95 #define BCSR_SWITCHES_ROTARY 0x0F00 96 97 #define BCSR_RESETS_PHY0 0x0001 98 #define BCSR_RESETS_PHY1 0x0002 99 #define BCSR_RESETS_DC 0x0004 100 #define BCSR_RESETS_FIR_SEL 0x2000 101 #define BCSR_RESETS_IRDA_MODE_MASK 0xC000 102 #define BCSR_RESETS_IRDA_MODE_FULL 0x0000 103 #define BCSR_RESETS_IRDA_MODE_OFF 0x4000 104 #define BCSR_RESETS_IRDA_MODE_2_3 0x8000 105 #define BCSR_RESETS_IRDA_MODE_1_3 0xC000 106 107 #define BCSR_PCMCIA_PC0VPP 0x0003 108 #define BCSR_PCMCIA_PC0VCC 0x000C 109 #define BCSR_PCMCIA_PC0DRVEN 0x0010 110 #define BCSR_PCMCIA_PC0RST 0x0080 111 #define BCSR_PCMCIA_PC1VPP 0x0300 112 #define BCSR_PCMCIA_PC1VCC 0x0C00 113 #define BCSR_PCMCIA_PC1DRVEN 0x1000 114 #define BCSR_PCMCIA_PC1RST 0x8000 115 116 #define BCSR_BOARD_PCIM66EN 0x0001 117 #define BCSR_BOARD_SD0_PWR 0x0040 118 #define BCSR_BOARD_SD1_PWR 0x0080 119 #define BCSR_BOARD_PCIM33 0x0100 120 #define BCSR_BOARD_GPIO200RST 0x0400 121 #define BCSR_BOARD_PCICFG 0x1000 122 #define BCSR_BOARD_SD0_WP 0x4000 123 #define BCSR_BOARD_SD1_WP 0x8000 124 125 #define BCSR_LEDS_DECIMALS 0x0003 126 #define BCSR_LEDS_LED0 0x0100 127 #define BCSR_LEDS_LED1 0x0200 128 #define BCSR_LEDS_LED2 0x0400 129 #define BCSR_LEDS_LED3 0x0800 130 131 #define BCSR_SWRESET_RESET 0x0080 132 133 /* PCMCIA Db1x00 specific defines */ 134 #define PCMCIA_MAX_SOCK 1 135 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 136 137 /* VPP/VCC */ 138 #define SET_VCC_VPP(VCC, VPP, SLOT)\ 139 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 140 141 /* MTD CONFIG OPTIONS */ 142 #if defined(CONFIG_MTD_DB1X00_BOOT) && defined(CONFIG_MTD_DB1X00_USER) 143 #define DB1X00_BOTH_BANKS 144 #elif defined(CONFIG_MTD_DB1X00_BOOT) && !defined(CONFIG_MTD_DB1X00_USER) 145 #define DB1X00_BOOT_ONLY 146 #elif !defined(CONFIG_MTD_DB1X00_BOOT) && defined(CONFIG_MTD_DB1X00_USER) 147 #define DB1X00_USER_ONLY 148 #endif 149 150 /* SD controller macros */ 151 /* 152 * Detect card. 153 */ 154 #define mmc_card_inserted(_n_, _res_) \ 155 do { \ 156 BCSR * const bcsr = (BCSR *)0xAE000000; \ 157 unsigned long mmc_wp, board_specific; \ 158 if ((_n_)) { \ 159 mmc_wp = BCSR_BOARD_SD1_WP; \ 160 } else { \ 161 mmc_wp = BCSR_BOARD_SD0_WP; \ 162 } \ 163 board_specific = au_readl((unsigned long)(&bcsr->specific)); \ 164 if (!(board_specific & mmc_wp)) {/* low means card present */ \ 165 *(int *)(_res_) = 1; \ 166 } else { \ 167 *(int *)(_res_) = 0; \ 168 } \ 169 } while (0) 170 171 /* 172 * Apply power to card slot(s). 173 */ 174 #define mmc_power_on(_n_) \ 175 do { \ 176 BCSR * const bcsr = (BCSR *)0xAE000000; \ 177 unsigned long mmc_pwr, mmc_wp, board_specific; \ 178 if ((_n_)) { \ 179 mmc_pwr = BCSR_BOARD_SD1_PWR; \ 180 mmc_wp = BCSR_BOARD_SD1_WP; \ 181 } else { \ 182 mmc_pwr = BCSR_BOARD_SD0_PWR; \ 183 mmc_wp = BCSR_BOARD_SD0_WP; \ 184 } \ 185 board_specific = au_readl((unsigned long)(&bcsr->specific)); \ 186 if (!(board_specific & mmc_wp)) {/* low means card present */ \ 187 board_specific |= mmc_pwr; \ 188 au_writel(board_specific, (int)(&bcsr->specific)); \ 189 au_sync(); \ 190 } \ 191 } while (0) 192 193 #endif /* __ASM_DB1X00_H */ 194 195