1 /* 2 * Lowlevel hardware stuff for the MIPS based Cobalt microservers. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1997 Cobalt Microserver 9 * Copyright (C) 1997 Ralf Baechle 10 * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv) 11 * 12 */ 13 #ifndef __ASM_MIPS_COBALT_H 14 #define __ASM_MIPS_COBALT_H 15 16 /* 17 * COBALT interrupt enable bits 18 */ 19 #define COBALT_IE_PCI (1 << 0) 20 #define COBALT_IE_FLOPPY (1 << 1) 21 #define COBALT_IE_KEYBOARD (1 << 2) 22 #define COBALT_IE_SERIAL1 (1 << 3) 23 #define COBALT_IE_SERIAL2 (1 << 4) 24 #define COBALT_IE_PARALLEL (1 << 5) 25 #define COBALT_IE_GPIO (1 << 6) 26 #define COBALT_IE_RTC (1 << 7) 27 28 /* 29 * PCI defines 30 */ 31 #define COBALT_IE_ETHERNET (1 << 7) 32 #define COBALT_IE_SCSI (1 << 7) 33 34 /* 35 * COBALT Interrupt Level definitions. 36 * These should match the request IRQ id's. 37 */ 38 #define COBALT_TIMER_IRQ 0 39 #define COBALT_KEYBOARD_IRQ 1 40 #define COBALT_QUBE_SLOT_IRQ 9 41 #define COBALT_ETH0_IRQ 4 42 #define COBALT_ETH1_IRQ 13 43 #define COBALT_SCC_IRQ 4 44 #define COBALT_SERIAL2_IRQ 4 45 #define COBALT_PARALLEL_IRQ 5 46 #define COBALT_FLOPPY_IRQ 6 /* needs to be consistent with floppy driver! */ 47 #define COBALT_SCSI_IRQ 7 48 #define COBALT_SERIAL_IRQ 7 49 #define COBALT_RAQ_SCSI_IRQ 4 50 51 /* 52 * PCI configuration space manifest constants. These are wired into 53 * the board layout according to the PCI spec to enable the software 54 * to probe the hardware configuration space in a well defined manner. 55 * 56 * The PCI_DEVSHFT() macro transforms these values into numbers 57 * suitable for passing as the dev parameter to the various 58 * pcibios_read/write_config routines. 59 */ 60 #define COBALT_PCICONF_CPU 0x06 61 #define COBALT_PCICONF_ETH0 0x07 62 #define COBALT_PCICONF_RAQSCSI 0x08 63 #define COBALT_PCICONF_VIA 0x09 64 #define COBALT_PCICONF_PCISLOT 0x0A 65 #define COBALT_PCICONF_ETH1 0x0C 66 67 68 /* 69 * The Cobalt board id information. The boards have an ID number wired 70 * into the VIA that is available in the high nibble of register 94. 71 * This register is available in the VIA configuration space through the 72 * interface routines qube_pcibios_read/write_config. See cobalt/pci.c 73 */ 74 #define VIA_COBALT_BRD_ID_REG 0x94 75 #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char) (reg) >> 4) 76 #define COBALT_BRD_ID_QUBE1 0x3 77 #define COBALT_BRD_ID_RAQ1 0x4 78 #define COBALT_BRD_ID_QUBE2 0x5 79 #define COBALT_BRD_ID_RAQ2 0x6 80 81 82 /* 83 * Galileo chipset access macros for the Cobalt. The base address for 84 * the GT64111 chip is 0x14000000 85 */ 86 #define GT64111_BASE 0x04000000 87 #define GALILEO_REG(ofs) (GT64111_BASE + (ofs)) 88 89 #define GALILEO_INL(port) (inl(GALILEO_REG(port))) 90 #define GALILEO_OUTL(val, port) outl(val, GALILEO_REG(port)) 91 92 #define GALILEO_T0EXP 0x0100 93 #define GALILEO_ENTC0 0x01 94 #define GALILEO_SELTC0 0x02 95 96 #endif /* __ASM_MIPS_COBALT_H */ 97