1 /* $Id$ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. 8 */ 9 #ifndef _ASM_IA64_SN_INVENT_H 10 #define _ASM_IA64_SN_INVENT_H 11 12 #include <linux/types.h> 13 #include <asm/sn/sgi.h> 14 /* 15 * sys/sn/invent.h -- Kernel Hardware Inventory 16 * 17 * As the system boots, a list of recognized devices is assembled. 18 * This list can then be accessed through syssgi() by user-level programs 19 * so that they can learn about available peripherals and the system's 20 * hardware configuration. 21 * 22 * The data is organized into a linked list of structures that are composed 23 * of an inventory item class and a class-specific type. Each instance may 24 * also specify a 32-bit "state" which might be size, readiness, or 25 * anything else that's relevant. 26 * 27 */ 28 29 #define major_t int 30 #define minor_t int 31 #define app32_ptr_t unsigned long 32 #define graph_vertex_place_t long 33 #define GRAPH_VERTEX_NONE ((vertex_hdl_t)-1) 34 #define GRAPH_EDGE_PLACE_NONE ((graph_edge_place_t)0) 35 #define GRAPH_INFO_PLACE_NONE ((graph_info_place_t)0) 36 #define GRAPH_VERTEX_PLACE_NONE ((graph_vertex_place_t)0) 37 38 39 typedef struct inventory_s { 40 struct inventory_s *inv_next; /* next inventory record in list */ 41 int inv_class; /* class of object */ 42 int inv_type; /* class sub-type of object */ 43 major_t inv_controller; /* object major identifier */ 44 minor_t inv_unit; /* object minor identifier */ 45 int inv_state; /* information specific to object or 46 class */ 47 } inventory_t; 48 49 typedef struct cpu_inv_s { 50 int cpuflavor; /* differentiate processor */ 51 int cpufq; /* cpu frequency */ 52 int sdsize; /* secondary data cache size */ 53 int sdfreq; /* speed of the secondary cache */ 54 } cpu_inv_t; 55 56 57 typedef struct diag_inv_s{ 58 char name[80]; 59 int diagval; 60 int physid; 61 int virtid; 62 } diag_inv_t; 63 64 65 typedef struct router_inv_s{ 66 char portmap[80]; /* String indicating which ports int/ext */ 67 char type[40]; /* String name: e.g. "star", "meta", etc. */ 68 int freq; /* From hub */ 69 int rev; /* From hub */ 70 } router_inv_t; 71 72 73 /* 74 * NOTE: This file is a central registry for inventory IDs for each 75 * class of inventory object. It is important to keep the central copy 76 * of this file up-to-date with the work going on in various engineering 77 * projects. When making changes to this file in an engineering project 78 * tree, please make those changes separately from any others and then 79 * merge the changes to this file into the main line trees in order to 80 * prevent other engineering projects from conflicting with your ID 81 * allocations. 82 */ 83 84 85 /* Inventory Classes */ 86 /* when adding a new class, add also to classes[] in hinv.c */ 87 #define INV_PROCESSOR 1 88 #define INV_DISK 2 89 #define INV_MEMORY 3 90 #define INV_SERIAL 4 91 #define INV_PARALLEL 5 92 #define INV_TAPE 6 93 #define INV_GRAPHICS 7 94 #define INV_NETWORK 8 95 #define INV_SCSI 9 /* SCSI devices other than disk and tape */ 96 #define INV_AUDIO 10 97 #define INV_IOBD 11 98 #define INV_VIDEO 12 99 #define INV_BUS 13 100 #define INV_MISC 14 /* miscellaneous: a catchall */ 101 /*** add post-5.2 classes here for backward compatibility ***/ 102 #define INV_COMPRESSION 15 103 #define INV_VSCSI 16 /* SCSI devices on jag other than disk and tape */ 104 #define INV_DISPLAY 17 105 #define INV_UNC_SCSILUN 18 /* Unconnected SCSI lun */ 106 #define INV_PCI 19 /* PCI Bus */ 107 #define INV_PCI_NO_DRV 20 /* PCI Bus without any driver */ 108 #define INV_PROM 21 /* Different proms in the system */ 109 #define INV_IEEE1394 22 /* IEEE1394 devices */ 110 #define INV_RPS 23 /* redundant power source */ 111 #define INV_TPU 24 /* Tensor Processing Unit */ 112 #define INV_FCNODE 25 /* Helper class for SCSI classes, not in classes[] */ 113 #define INV_USB 26 /* Universal Serial Bus */ 114 #define INV_1394NODE 27 /* helper class for 1394/SPB2 classes, not in classes[] */ 115 116 /* types for class processor */ 117 #define INV_CPUBOARD 1 118 #define INV_CPUCHIP 2 119 #define INV_FPUCHIP 3 120 #define INV_CCSYNC 4 /* CC Rev 2+ sync join counter */ 121 122 /* states for cpu and fpu chips are revision numbers */ 123 124 /* cpuboard states */ 125 #define INV_IP20BOARD 10 126 #define INV_IP19BOARD 11 127 #define INV_IP22BOARD 12 128 #define INV_IP21BOARD 13 129 #define INV_IP26BOARD 14 130 #define INV_IP25BOARD 15 131 #define INV_IP30BOARD 16 132 #define INV_IP28BOARD 17 133 #define INV_IP32BOARD 18 134 #define INV_IP27BOARD 19 135 #define INV_IPMHSIMBOARD 20 136 #define INV_IP33BOARD 21 137 #define INV_IP35BOARD 22 138 139 /* types for class INV_IOBD */ 140 #define INV_EVIO 2 /* EVEREST I/O board */ 141 #define INV_O200IO 3 /* Origin 200 base I/O */ 142 143 /* IO board types for origin2000 for class INV_IOBD*/ 144 145 #define INV_O2000BASEIO 0x21 146 #define INV_O2000MSCSI 0x22 147 #define INV_O2000MENET 0x23 148 #define INV_O2000HIPPI 0x24 149 #define INV_O2000GFX 0x25 150 #define INV_O2000HAROLD 0x26 151 #define INV_O2000VME 0x27 152 #define INV_O2000MIO 0x28 153 #define INV_O2000FC 0x29 154 #define INV_O2000LINC 0x2a 155 156 #define INV_PCIADAP 4 157 /* states for class INV_IOBD type INV_EVERESTIO -- value of eb_type field */ 158 #define INV_IO4_REV1 0x21 159 160 /* types for class disk */ 161 /* NB: types MUST be unique within a class. 162 Please check this if adding new types. */ 163 164 #define INV_SCSICONTROL 1 165 #define INV_SCSIDRIVE 2 166 #define INV_SCSIFLOPPY 5 /* also cdroms, optical disks, etc. */ 167 #define INV_JAGUAR 16 /* Interphase Jaguar */ 168 #define INV_VSCSIDRIVE 17 /* Disk connected to Jaguar */ 169 #define INV_GIO_SCSICONTROL 18 /* optional GIO SCSI controller */ 170 #define INV_SCSIRAID 19 /* SCSI attached RAID */ 171 #define INV_XLVGEN 20 /* Generic XLV disk device */ 172 #define INV_PCCARD 21 /* PC-card (PCMCIA) devices */ 173 #define INV_PCI_SCSICONTROL 22 /* optional PCI SCSI controller */ 174 175 /* states for INV_SCSICONTROL disk type; indicate which chip rev; 176 * for 93A and B, unit field has microcode rev. */ 177 #define INV_WD93 0 /* WD 33C93 */ 178 #define INV_WD93A 1 /* WD 33C93A */ 179 #define INV_WD93B 2 /* WD 33C93B */ 180 #define INV_WD95A 3 /* WD 33C95A */ 181 #define INV_SCIP95 4 /* SCIP with a WD 33C95A */ 182 #define INV_ADP7880 5 /* Adaptec 7880 (single channel) */ 183 #define INV_QL_REV1 6 /* qlogic 1040 */ 184 #define INV_QL_REV2 7 /* qlogic 1040A */ 185 #define INV_QL_REV2_4 8 /* qlogic 1040A rev 4 */ 186 #define INV_QL_REV3 9 /* qlogic 1040B */ 187 #define INV_FCADP 10 /* Adaptec Emerald Fibrechannel */ 188 #define INV_QL_REV4 11 /* qlogic 1040B rev 2 */ 189 #define INV_QL 12 /* Unknown QL version */ 190 #define INV_QL_1240 13 /* qlogic 1240 */ 191 #define INV_QL_1080 14 /* qlogic 1080 */ 192 #define INV_QL_1280 15 /* qlogic 1280 */ 193 #define INV_QL_10160 16 /* qlogic 10160 */ 194 #define INV_QL_12160 17 /* qlogic 12160 */ 195 #define INV_QL_2100 18 /* qLogic 2100 Fibrechannel */ 196 #define INV_QL_2200 19 /* qLogic 2200 Fibrechannel */ 197 #define INV_PR_HIO_D 20 /* Prisa HIO Dual channel */ 198 #define INV_PR_PCI64_D 21 /* Prisa PCI-64 Dual channel */ 199 #define INV_QL_2200A 22 /* qLogic 2200A Fibrechannel */ 200 #define INV_SBP2 23 /* SBP2 protocol over OHCI on 1394 */ 201 #define INV_QL_2300 24 /* qLogic 2300 Fibrechannel */ 202 203 204 /* states for INV_SCSIDRIVE type of class disk */ 205 #define INV_RAID5_LUN 0x100 206 #define INV_PRIMARY 0x200 /* primary path */ 207 #define INV_ALTERNATE 0x400 /* alternate path */ 208 #define INV_FAILED 0x800 /* path has failed */ 209 #define INV_XVMVOL 0x1000 /* disk is managed by XVM */ 210 211 /* states for INV_SCSIFLOPPY type of class disk */ 212 #define INV_TEAC_FLOPPY 1 /* TEAC 3 1/2 inch floppy drive */ 213 #define INV_INSITE_FLOPPY 2 /* INSITE, IOMEGA Io20S, SyQuest floppy drives */ 214 215 /* END OF CLASS DISK TYPES */ 216 217 /* types for class memory */ 218 /* NB. the states for class memory are sizes in bytes */ 219 #define INV_MAIN 1 220 #define INV_DCACHE 3 221 #define INV_ICACHE 4 222 #define INV_WBUFFER 5 223 #define INV_SDCACHE 6 224 #define INV_SICACHE 7 225 #define INV_SIDCACHE 8 226 #define INV_MAIN_MB 9 227 #define INV_HUBSPC 10 /* HUBSPC */ 228 #define INV_TIDCACHE 11 229 230 /* types for class serial */ 231 #define INV_CDSIO 1 /* Central Data serial board */ 232 #define INV_T3270 2 /* T3270 emulation */ 233 #define INV_GSE 3 /* SpectraGraphics Gerbil coax cable */ 234 #define INV_SI 4 /* SNA SDLC controller */ 235 #define INV_M333X25 6 /* X.25 controller */ 236 #define INV_CDSIO_E 7 /* Central Data serial board on E space */ 237 #define INV_ONBOARD 8 /* Serial ports per CPU board */ 238 #define INV_EPC_SERIAL 9 /* EVEREST I/O EPC serial port */ 239 #define INV_ICA 10 /* IRIS (IBM) Channel Adapter card */ 240 #define INV_VSC 11 /* SBE VME Synch Comm board */ 241 #define INV_ISC 12 /* SBE ISA Synch Comm board */ 242 #define INV_GSC 13 /* SGI GIO Synch Comm board */ 243 #define INV_ASO_SERIAL 14 /* serial portion of SGI ASO board */ 244 #define INV_PSC 15 /* SBE PCI Synch Comm board */ 245 #define INV_IOC3_DMA 16 /* DMA mode IOC3 serial */ 246 #define INV_IOC3_PIO 17 /* PIO mode IOC3 serial */ 247 #define INV_INVISIBLE 18 /* invisible inventory entry for kernel use */ 248 #define INV_ISA_DMA 19 /* DMA mode ISA serial -- O2 */ 249 250 /* types for class parallel */ 251 #define INV_GPIB 2 /* National Instrument GPIB board */ 252 #define INV_GPIB_E 3 /* National Instrument GPIB board on E space*/ 253 #define INV_EPC_PLP 4 /* EVEREST I/O EPC Parallel Port */ 254 #define INV_ONBOARD_PLP 5 /* Integral parallel port, 255 state = 0 -> output only 256 state = 1 -> bi-directional */ 257 #define INV_EPP_ECP_PLP 6 /* Integral EPP/ECP parallel port */ 258 #define INV_EPP_PFD 7 /* External EPP parallel peripheral */ 259 260 /* types for class tape */ 261 #define INV_SCSIQIC 1 /* Any SCSI tape, not just QIC{24,150}... */ 262 #define INV_VSCSITAPE 4 /* SCSI tape connected to Jaguar */ 263 264 /* sub types for type INV_SCSIQIC and INV_VSCSITAPE (in state) */ 265 #define TPUNKNOWN 0 /* type not known */ 266 #define TPQIC24 1 /* QIC24 1/4" cartridge */ 267 #define TPDAT 2 /* 4mm Digital Audio Tape cartridge */ 268 #define TPQIC150 3 /* QIC150 1/4" cartridge */ 269 #define TP9TRACK 4 /* 9 track reel */ 270 #define TP8MM_8200 5 /* 8 mm video tape cartridge */ 271 #define TP8MM_8500 6 /* 8 mm video tape cartridge */ 272 #define TPQIC1000 7 /* QIC1000 1/4" cartridge */ 273 #define TPQIC1350 8 /* QIC1350 1/4" cartridge */ 274 #define TP3480 9 /* 3480 compatible cartridge */ 275 #define TPDLT 10 /* DEC Digital Linear Tape cartridge */ 276 #define TPD2 11 /* D2 tape cartridge */ 277 #define TPDLTSTACKER 12 /* DEC Digital Linear Tape stacker */ 278 #define TPNTP 13 /* IBM Magstar 3590 Tape Device cartridge */ 279 #define TPNTPSTACKER 14 /* IBM Magstar 3590 Tape Device stacker */ 280 #define TPSTK9490 15 /* StorageTeK 9490 */ 281 #define TPSTKSD3 16 /* StorageTeK SD3 */ 282 #define TPGY10 17 /* Sony GY-10 */ 283 #define TP8MM_8900 18 /* 8 mm (AME) tape cartridge */ 284 #define TPMGSTRMP 19 /* IBM Magster MP 3570 cartridge */ 285 #define TPMGSTRMPSTCKR 20 /* IBM Magstar MP stacker */ 286 #define TPSTK4791 21 /* StorageTek 4791 */ 287 #define TPSTK4781 22 /* StorageTek 4781 */ 288 #define TPFUJDIANA1 23 /* Fujitsu Diana-1 (M1016/M1017) */ 289 #define TPFUJDIANA2 24 /* Fujitsu Diana-2 (M2483) */ 290 #define TPFUJDIANA3 25 /* Fujitsu Diana-3 (M2488) */ 291 #define TP8MM_AIT 26 /* Sony AIT format tape */ 292 #define TPTD3600 27 /* Philips TD3600 */ 293 #define TPTD3600STCKR 28 /* Philips TD3600 stacker */ 294 #define TPNCTP 29 /* Philips NCTP */ 295 #define TPGY2120 30 /* Sony GY-2120 (replaces GY-10) */ 296 #define TPOVL490E 31 /* Overland Data L490E (3490E compatible) */ 297 #define TPSTK9840 32 /* StorageTeK 9840 (aka Eagle) */ 298 299 /* Diagnostics inventory */ 300 #define INV_CPUDIAGVAL 70 301 302 303 /* 304 * GFX invent is a subset of gfxinfo 305 */ 306 307 /* types for class graphics */ 308 #define INV_GR1BOARD 1 /* GR1 (Eclipse) graphics */ 309 #define INV_GR1BP 2 /* OBSOLETE - use INV_GR1BIT24 instead */ 310 #define INV_GR1ZBUFFER 3 /* OBSOLETE - use INV_GR1ZBUF24 instead */ 311 #define INV_GRODEV 4 /* Clover1 graphics */ 312 #define INV_GMDEV 5 /* GT graphics */ 313 #define INV_CG2 6 /* CG2 composite video/genlock board */ 314 #define INV_VMUXBOARD 7 /* VMUX video mux board */ 315 #define INV_VGX 8 /* VGX (PowerVision) graphics */ 316 #define INV_VGXT 9 /* VGXT (PowerVision) graphics with IMP5s. */ 317 #define INV_LIGHT 10 /* LIGHT graphics */ 318 #define INV_GR2 11 /* EXPRESS graphics */ 319 #define INV_RE 12 /* RealityEngine graphics */ 320 #define INV_VTX 13 /* RealityEngine graphics - VTX variant */ 321 #define INV_NEWPORT 14 /* Newport graphics */ 322 #define INV_MGRAS 15 /* Mardigras graphics */ 323 #define INV_IR 16 /* InfiniteReality graphics */ 324 #define INV_CRIME 17 /* Moosehead on board CRIME graphics */ 325 #define INV_IR2 18 /* InfiniteReality2 graphics */ 326 #define INV_IR2LITE 19 /* Reality graphics */ 327 #define INV_IR2E 20 /* InfiniteReality2e graphics */ 328 #define INV_ODSY 21 /* Odyssey graphics */ 329 #define INV_IR3 22 /* InfiniteReality3 graphics */ 330 331 /* states for graphics class GR1 */ 332 #define INV_GR1REMASK 0x7 /* RE version */ 333 #define INV_GR1REUNK 0x0 /* RE version unknown */ 334 #define INV_GR1RE1 0x1 /* RE1 */ 335 #define INV_GR1RE2 0x2 /* RE2 */ 336 #define INV_GR1BUSMASK 0x38 /* GR1 bus architecture */ 337 #define INV_GR1PB 0x00 /* Eclipse private bus */ 338 #define INV_GR1PBVME 0x08 /* VGR2 board VME and private bus interfaces */ 339 #define INV_GR1TURBO 0x40 /* has turbo option */ 340 #define INV_GR1BIT24 0x80 /* has bitplane option */ 341 #define INV_GR1ZBUF24 0x100 /* has z-buffer option */ 342 #define INV_GR1SMALLMON 0x200 /* using 14" monitor */ 343 #define INV_GR1SMALLMAP 0x400 /* has 256 entry color map */ 344 #define INV_GR1AUX4 0x800 /* has AUX/WID plane option */ 345 346 /* states for graphics class GR2 */ 347 /* bitmasks */ 348 #define INV_GR2_Z 0x1 /* has z-buffer option */ 349 #define INV_GR2_24 0x2 /* has bitplane option */ 350 #define INV_GR2_4GE 0x4 /* has 4 GEs */ 351 #define INV_GR2_1GE 0x8 /* has 1 GEs */ 352 #define INV_GR2_2GE 0x10 /* has 2 GEs */ 353 #define INV_GR2_8GE 0x20 /* has 8 GEs */ 354 #define INV_GR2_GR3 0x40 /* board GR3 */ 355 #define INV_GR2_GU1 0x80 /* board GU1 */ 356 #define INV_GR2_INDY 0x100 /* board GR3 on Indy*/ 357 #define INV_GR2_GR5 0x200 /* board GR3 with 4 GEs, hinv prints GR5-XZ */ 358 359 /* supported configurations */ 360 #define INV_GR2_XS 0x0 /* GR2-XS */ 361 #define INV_GR2_XSZ 0x1 /* GR2-XS with z-buffer */ 362 #define INV_GR2_XS24 0x2 /* GR2-XS24 */ 363 #define INV_GR2_XS24Z 0x3 /* GR2-XS24 with z-buffer */ 364 #define INV_GR2_XSM 0x4 /* GR2-XSM */ 365 #define INV_GR2_ELAN 0x7 /* GR2-Elan */ 366 #define INV_GR2_XZ 0x13 /* GR2-XZ */ 367 #define INV_GR3_XSM 0x44 /* GR3-XSM */ 368 #define INV_GR3_ELAN 0x47 /* GR3-Elan */ 369 #define INV_GU1_EXTREME 0xa3 /* GU1-Extreme */ 370 371 /* States for graphics class NEWPORT */ 372 #define INV_NEWPORT_XL 0x01 /* Indigo2 XL model */ 373 #define INV_NEWPORT_24 0x02 /* board has 24 bitplanes */ 374 #define INV_NEWTON 0x04 /* Triton SUBGR tagging */ 375 376 /* States for graphics class MGRAS */ 377 #define INV_MGRAS_ARCHS 0xff000000 /* architectures */ 378 #define INV_MGRAS_HQ3 0x00000000 /*impact*/ 379 #define INV_MGRAS_HQ4 0x01000000 /*gamera*/ 380 #define INV_MGRAS_MOT 0x02000000 /*mothra*/ 381 #define INV_MGRAS_GES 0x00ff0000 /* number of GEs */ 382 #define INV_MGRAS_1GE 0x00010000 383 #define INV_MGRAS_2GE 0x00020000 384 #define INV_MGRAS_RES 0x0000ff00 /* number of REs */ 385 #define INV_MGRAS_1RE 0x00000100 386 #define INV_MGRAS_2RE 0x00000200 387 #define INV_MGRAS_TRS 0x000000ff /* number of TRAMs */ 388 #define INV_MGRAS_0TR 0x00000000 389 #define INV_MGRAS_1TR 0x00000001 390 #define INV_MGRAS_2TR 0x00000002 391 392 /* States for graphics class CRIME */ 393 #define INV_CRM_BASE 0x01 /* Moosehead basic model */ 394 395 /* States for graphics class ODSY */ 396 #define INV_ODSY_ARCHS 0xff000000 /* architectures */ 397 #define INV_ODSY_REVA_ARCH 0x01000000 /* Buzz Rev A */ 398 #define INV_ODSY_REVB_ARCH 0x02000000 /* Buzz Rev B */ 399 #define INV_ODSY_MEMCFG 0x00ff0000 /* memory configs */ 400 #define INV_ODSY_MEMCFG_32 0x00010000 /* 32MB memory */ 401 #define INV_ODSY_MEMCFG_64 0x00020000 /* 64MB memory */ 402 #define INV_ODSY_MEMCFG_128 0x00030000 /* 128MB memory */ 403 #define INV_ODSY_MEMCFG_256 0x00040000 /* 256MB memory */ 404 #define INV_ODSY_MEMCFG_512 0x00050000 /* 512MB memory */ 405 406 407 /* types for class network */ 408 #define INV_NET_ETHER 0 /* 10Mb Ethernet */ 409 #define INV_NET_HYPER 1 /* HyperNet */ 410 #define INV_NET_CRAYIOS 2 /* Cray Input/Ouput Subsystem */ 411 #define INV_NET_FDDI 3 /* FDDI */ 412 #define INV_NET_TOKEN 4 /* 16/4 Token Ring */ 413 #define INV_NET_HIPPI 5 /* HIPPI */ 414 #define INV_NET_ATM 6 /* ATM */ 415 #define INV_NET_ISDN_BRI 7 /* ISDN */ 416 #define INV_NET_ISDN_PRI 8 /* PRI ISDN */ 417 #define INV_NET_HIPPIS 9 /* HIPPI-Serial */ 418 #define INV_NET_GSN 10 /* GSN (aka HIPPI-6400) */ 419 #define INV_NET_MYRINET 11 /* Myricom PCI network */ 420 421 /* controllers for network types, unique within class network */ 422 #define INV_ETHER_EC 0 /* IP6 integral controller */ 423 #define INV_ETHER_ENP 1 /* CMC board */ 424 #define INV_ETHER_ET 2 /* IP5 integral controller */ 425 #define INV_HYPER_HY 3 /* HyperNet controller */ 426 #define INV_CRAYIOS_CFEI3 4 /* Cray Front End Interface, v3 */ 427 #define INV_FDDI_IMF 5 /* Interphase/Martin 3211 FDDI */ 428 #define INV_ETHER_EGL 6 /* Interphase V/4207 Eagle */ 429 #define INV_ETHER_FXP 7 /* CMC C/130 FXP */ 430 #define INV_FDDI_IPG 8 /* Interphase/SGI 4211 Peregrine FDDI */ 431 #define INV_TOKEN_FV 9 /* Formation fv1600 Token-Ring board */ 432 #define INV_FDDI_XPI 10 /* XPI GIO bus FDDI */ 433 #define INV_TOKEN_GTR 11 /* GTR GIO bus TokenRing */ 434 #define INV_ETHER_GIO 12 /* IP12/20 optional GIO ethernet controller */ 435 #define INV_ETHER_EE 13 /* Everest IO4 EPC SEEQ/EDLC */ 436 #define INV_HIO_HIPPI 14 /* HIO HIPPI for Challenge/Onyx */ 437 #define INV_ATM_GIO64 15 /* ATM OC-3c Mez card */ 438 #define INV_ETHER_EP 16 /* 8-port E-Plex Ethernet */ 439 #define INV_ISDN_SM 17 /* Siemens PEB 2085 */ 440 #define INV_TOKEN_MTR 18 /* EISA TokenRing */ 441 #define INV_ETHER_EF 19 /* IOC3 Fast Ethernet */ 442 #define INV_ISDN_48XP 20 /* Xircom PRI-48XP */ 443 #define INV_FDDI_RNS 21 /* Rockwell Network Systems FDDI */ 444 #define INV_HIPPIS_XTK 22 /* Xtalk HIPPI-Serial */ 445 #define INV_ATM_QUADOC3 23 /* Xtalk Quad OC-3c ATM interface */ 446 #define INV_TOKEN_MTRPCI 24 /* PCI TokenRing */ 447 #define INV_ETHER_ECF 25 /* PCI Fast Ethernet */ 448 #define INV_GFE 26 /* GIO Fast Ethernet */ 449 #define INV_VFE 27 /* VME Fast Ethernet */ 450 #define INV_ETHER_GE 28 /* Gigabit Ethernet */ 451 #define INV_ETHER_EFP INV_ETHER_EF /* unused (same as IOC3 Fast Ethernet) */ 452 #define INV_GSN_XTK1 29 /* single xtalk version of GSN */ 453 #define INV_GSN_XTK2 30 /* dual xtalk version of GSN */ 454 #define INV_FORE_HE 31 /* FORE HE ATM Card */ 455 #define INV_FORE_PCA 32 /* FORE PCA ATM Card */ 456 #define INV_FORE_VMA 33 /* FORE VMA ATM Card */ 457 #define INV_FORE_ESA 34 /* FORE ESA ATM Card */ 458 #define INV_FORE_GIA 35 /* FORE GIA ATM Card */ 459 460 /* Types for class INV_SCSI and INV_VSCSI; The type code is the same as 461 * the device type code returned by the Inquiry command, iff the Inquiry 462 * command defines a type code for the device in question. If it doesn't, 463 * values over 31 will be used for the device type. 464 * Note: the lun is encoded in bits 8-15 of the state. The 465 * state field low 3 bits contains the information from the inquiry 466 * cmd that indicates ANSI SCSI 1,2, etc. compliance, and bit 7 467 * contains the inquiry info that indicates whether the media is 468 * removable. 469 */ 470 #define INV_PRINTER 2 /* SCSI printer */ 471 #define INV_CPU 3 /* SCSI CPU device */ 472 #define INV_WORM 4 /* write-once-read-many (e.g. optical disks) */ 473 #define INV_CDROM 5 /* CD-ROM */ 474 #define INV_SCANNER 6 /* scanners */ 475 #define INV_OPTICAL 7 /* optical disks (read-write) */ 476 #define INV_CHANGER 8 /* jukebox's for CDROMS, for example */ 477 #define INV_COMM 9 /* Communications device */ 478 #define INV_STARCTLR 12 /* Storage Array Controller */ 479 #define INV_RAIDCTLR 32 /* RAID ctlr actually gives type 0 */ 480 481 /* bit definitions for state field for class INV_SCSI */ 482 #define INV_REMOVE 0x80 /* has removable media */ 483 #define INV_SCSI_MASK 7 /* to which ANSI SCSI standard device conforms*/ 484 485 /* types for class INV_AUDIO */ 486 487 #define INV_AUDIO_HDSP 0 /* Indigo DSP system */ 488 #define INV_AUDIO_VIGRA110 1 /* ViGRA 110 audio board */ 489 #define INV_AUDIO_VIGRA210 2 /* ViGRA 210 audio board */ 490 #define INV_AUDIO_A2 3 /* HAL2 / Audio Module for Indigo 2 */ 491 #define INV_AUDIO_A3 4 /* Moosehead (IP32) AD1843 codec */ 492 #define INV_AUDIO_RAD 5 /* RAD PCI chip */ 493 494 /* types for class INV_VIDEO */ 495 496 #define INV_VIDEO_LIGHT 0 497 #define INV_VIDEO_VS2 1 /* MultiChannel Option */ 498 #define INV_VIDEO_EXPRESS 2 /* kaleidecope video */ 499 #define INV_VIDEO_VINO 3 500 #define INV_VIDEO_VO2 4 /* Sirius Video */ 501 #define INV_VIDEO_INDY 5 /* Indy Video - kal vid on Newport 502 gfx on Indy */ 503 #define INV_VIDEO_MVP 6 /* Moosehead Video Ports */ 504 #define INV_VIDEO_INDY_601 7 /* Indy Video 601 */ 505 #define INV_VIDEO_PMUX 8 /* PALMUX video w/ PGR gfx */ 506 #define INV_VIDEO_MGRAS 9 /* Galileo 1.5 video */ 507 #define INV_VIDEO_DIVO 10 /* DIVO video */ 508 #define INV_VIDEO_RACER 11 /* SpeedRacer Pro Video */ 509 #define INV_VIDEO_EVO 12 /* EVO Personal Video */ 510 #define INV_VIDEO_XTHD 13 /* XIO XT-HDTV video */ 511 #define INV_VIDEO_XTDIGVID 14 /* XIO XT-HDDIGVID video */ 512 513 /* states for video class INV_VIDEO_EXPRESS */ 514 515 #define INV_GALILEO_REV 0xF 516 #define INV_GALILEO_JUNIOR 0x10 517 #define INV_GALILEO_INDY_CAM 0x20 518 #define INV_GALILEO_DBOB 0x40 519 #define INV_GALILEO_ELANTEC 0x80 520 521 /* states for video class VINO */ 522 523 #define INV_VINO_REV 0xF 524 #define INV_VINO_INDY_CAM 0x10 525 #define INV_VINO_INDY_NOSW 0x20 /* nebulous - means s/w not installed */ 526 527 /* states for video class MVP */ 528 529 #define INV_MVP_REV(x) (((x)&0x0000000f)) 530 #define INV_MVP_REV_SW(x) (((x)&0x000000f0)>>4) 531 #define INV_MVP_AV_BOARD(x) (((x)&0x00000f00)>>8) 532 #define INV_MVP_AV_REV(x) (((x)&0x0000f000)>>12) 533 #define INV_MVP_CAMERA(x) (((x)&0x000f0000)>>16) 534 #define INV_MVP_CAM_REV(x) (((x)&0x00f00000)>>20) 535 #define INV_MVP_SDIINF(x) (((x)&0x0f000000)>>24) 536 #define INV_MVP_SDI_REV(x) (((x)&0xf0000000)>>28) 537 538 /* types for class INV_BUS */ 539 540 #define INV_BUS_VME 0 541 #define INV_BUS_EISA 1 542 #define INV_BUS_GIO 2 543 #define INV_BUS_BT3_PCI 3 544 545 /* types for class INV_MISC */ 546 #define INV_MISC_EPC_EINT 0 /* EPC external interrupts */ 547 #define INV_MISC_PCKM 1 /* pc keyboard or mouse */ 548 #define INV_MISC_IOC3_EINT 2 /* IOC3 external interrupts */ 549 #define INV_MISC_OTHER 3 /* non-specific type */ 550 551 /* 552 * The four components below do not actually have inventory information 553 * associated with the vertex. These symbols are used by grio at the 554 * moment to figure out the device type from the vertex. If these get 555 * inventory structures in the future, either the type values must 556 * remain the same or grio code needs to change. 557 */ 558 559 #define INV_XBOW 3 /* cross bow */ 560 #define INV_HUB 4 /* hub */ 561 #define INV_PCI_BRIDGE 5 /* pci bridge */ 562 #define INV_ROUTER 6 /* router */ 563 564 /* types for class INV_PROM */ 565 #define INV_IO6PROM 0 566 #define INV_IP27PROM 1 567 #define INV_IP35PROM 2 568 569 /* types for class INV_COMPRESSION */ 570 571 #define INV_COSMO 0 572 #define INV_INDYCOMP 1 573 #define INV_IMPACTCOMP 2 /* cosmo2, aka impact compression */ 574 #define INV_VICE 3 /* Video imaging & compression engine */ 575 576 /* types for class INV_DISPLAY */ 577 #define INV_PRESENTER_BOARD 0 /* Indy Presenter adapter board */ 578 #define INV_PRESENTER_PANEL 1 /* Indy Presenter board and panel */ 579 #define INV_ICO_BOARD 2 /* IMPACT channel option board */ 580 #define INV_DCD_BOARD 3 /* O2 dual channel option board */ 581 #define INV_7of9_BOARD 4 /* 7of9 flatpanel adapter board */ 582 #define INV_7of9_PANEL 5 /* 7of9 flatpanel board and panel */ 583 584 /* types for class INV_IEEE1394 */ 585 #define INV_OHCI 0 /* Ohci IEEE1394 pci card */ 586 587 /* state for class INV_IEEE1394 & type INV_OHCI */ 588 #define INV_IEEE1394_STATE_TI_REV_1 0 589 590 /* O2 DVLink 1.1 controller static info */ 591 #define INV_IEEE1394_CTLR_O2_DVLINK_11 0x8009104c 592 593 /* types for class INV_TPU */ 594 #define INV_TPU_EXT 0 /* External XIO Tensor Processing Unit */ 595 #define INV_TPU_XIO 1 /* Internal XIO Tensor Processing Unit */ 596 597 /* 598 * USB Types. The upper 8 bits contain general usb device class and are used to 599 * qualify the lower 8 bits which contain device type within a usb class. 600 * Use USB_INV_DEVCLASS and USB_INV_DEVTYPE to to decode an i_type, and 601 * USB_INV_TYPE to set it. 602 */ 603 604 #define USB_INV_DEVCLASS(invtype) ((invtype) >> 8) 605 #define USB_INV_DEVTYPE(invtype) ((invtype) & 0xf) 606 #define USB_INV_TYPE(usbclass, usbtype) (((usbclass) << 8) | (usbtype)) 607 608 /* 609 * USB device classes. These classes might not match the classes as defined 610 * by the usb spec, but where possible we will try. 611 */ 612 613 #define USB_INV_CLASS_RH 0x00 /* root hub (ie. controller) */ 614 #define USB_INV_CLASS_HID 0x03 /* human interface device */ 615 #define USB_INV_CLASS_HUB 0x09 /* hub device */ 616 617 /* 618 * USB device types within a class. These will not match USB device types, 619 * as the usb is not consistent on how specific types are defined (sometimes 620 * they are found in the interface subclass, sometimes (as in HID devices) they 621 * are found within data generated by the device (hid report descriptors for 622 * example). 623 */ 624 625 /* 626 * RH types 627 */ 628 629 #define USB_INV_RH_OHCI 0x01 /* ohci root hub */ 630 631 /* 632 * HID types 633 */ 634 635 #define USB_INV_HID_KEYBOARD 0x01 /* kbd (HID class) */ 636 #define USB_INV_HID_MOUSE 0x02 /* mouse (HID class) */ 637 638 /* 639 * HUB types - none yet 640 */ 641 642 typedef struct invent_generic_s { 643 unsigned short ig_module; 644 unsigned short ig_slot; 645 unsigned char ig_flag; 646 int ig_invclass; 647 } invent_generic_t; 648 649 #define INVENT_ENABLED 0x1 650 651 typedef struct invent_membnkinfo { 652 unsigned short imb_size; /* bank size in MB */ 653 unsigned short imb_attr; /* Mem attributes */ 654 unsigned int imb_flag; /* bank flags */ 655 } invent_membnkinfo_t; 656 657 658 typedef struct invent_meminfo { 659 invent_generic_t im_gen; 660 unsigned short im_size; /* memory size */ 661 unsigned short im_banks; /* number of banks */ 662 /* 663 * declare an array with one element. Each platform is expected to 664 * allocate the size required based on the number of banks and set 665 * the im_banks correctly for this array traversal. 666 */ 667 invent_membnkinfo_t im_bank_info[1]; 668 } invent_meminfo_t; 669 670 #define INV_MEM_PREMIUM 0x01 671 672 typedef struct invent_cpuinfo { 673 invent_generic_t ic_gen; 674 cpu_inv_t ic_cpu_info; 675 unsigned short ic_cpuid; 676 unsigned short ic_slice; 677 unsigned short ic_cpumode; 678 679 } invent_cpuinfo_t; 680 681 typedef struct invent_rpsinfo { 682 invent_generic_t ir_gen; 683 int ir_xbox; /* is RPS connected to an xbox */ 684 } invent_rpsinfo_t; 685 686 typedef struct invent_miscinfo { 687 invent_generic_t im_gen; 688 int im_rev; 689 int im_version; 690 int im_type; 691 uint64_t im_speed; 692 } invent_miscinfo_t; 693 694 695 typedef struct invent_routerinfo{ 696 invent_generic_t im_gen; 697 router_inv_t rip; 698 } invent_routerinfo_t; 699 700 701 702 #ifdef __KERNEL__ 703 704 typedef struct invplace_s { 705 vertex_hdl_t invplace_vhdl; /* current vertex */ 706 vertex_hdl_t invplace_vplace; /* place in vertex list */ 707 inventory_t *invplace_inv; /* place in inv list on vertex */ 708 } invplace_t; /* Magic cookie placeholder in inventory list */ 709 710 extern invplace_t invplace_none; 711 #define INVPLACE_NONE invplace_none 712 713 extern void add_to_inventory(int, int, int, int, int); 714 extern void replace_in_inventory(inventory_t *, int, int, int, int, int); 715 extern void start_scan_inventory(invplace_t *); 716 extern inventory_t *get_next_inventory(invplace_t *); 717 extern void end_scan_inventory(invplace_t *); 718 extern inventory_t *find_inventory(inventory_t *, int, int, int, int, int); 719 extern int scaninvent(int (*)(inventory_t *, void *), void *); 720 extern int get_sizeof_inventory(int); 721 722 extern void device_inventory_add( vertex_hdl_t device, 723 int class, 724 int type, 725 major_t ctlr, 726 minor_t unit, 727 int state); 728 729 730 extern inventory_t *device_inventory_get_next( vertex_hdl_t device, 731 invplace_t *); 732 733 extern void device_controller_num_set( vertex_hdl_t, 734 int); 735 extern int device_controller_num_get( vertex_hdl_t); 736 #endif /* __KERNEL__ */ 737 #endif /* _ASM_IA64_SN_INVENT_H */ 738