1 /* CRIS pgtable.h - macros and functions to manipulate page tables
2 *
3 * HISTORY:
4 *
5 * $Log: pgtable.h,v $
6 * Revision 1.17 2002/12/02 08:14:08 starvik
7 * Merge of Linux 2.4.20
8 *
9 * Revision 1.16 2002/11/20 18:20:17 hp
10 * Make all static inline functions extern inline.
11 *
12 * Revision 1.15 2002/04/23 15:37:52 bjornw
13 * Removed page_address and added flush_icache_user_range
14 *
15 * Revision 1.14 2001/12/10 03:08:50 bjornw
16 * Added pgtable_cache_init dummy
17 *
18 * Revision 1.13 2001/11/12 18:05:38 pkj
19 * Added declaration of paging_init().
20 *
21 * Revision 1.12 2001/08/11 00:28:00 bjornw
22 * PAGE_CHG_MASK and PAGE_NONE had somewhat untraditional values
23 *
24 * Revision 1.11 2001/04/04 14:38:36 bjornw
25 * Removed bad_pagetable handling and the _kernel functions
26 *
27 * Revision 1.10 2001/03/23 07:46:42 starvik
28 * Corrected according to review remarks
29 *
30 * Revision 1.9 2000/11/22 14:57:53 bjornw
31 * * extern inline -> static inline
32 * * include asm-generic/pgtable.h
33 *
34 * Revision 1.8 2000/11/21 13:56:16 bjornw
35 * Use CONFIG_CRIS_LOW_MAP for the low VM map instead of explicit CPU type
36 *
37 * Revision 1.7 2000/10/06 15:05:32 bjornw
38 * VMALLOC area changed in memory mapping change
39 *
40 * Revision 1.6 2000/10/04 16:59:14 bjornw
41 * Changed comments
42 *
43 * Revision 1.5 2000/09/13 14:39:53 bjornw
44 * New macros
45 *
46 * Revision 1.4 2000/08/17 15:38:48 bjornw
47 * 2.4.0-test6 modifications:
48 * * flush_dcache_page added
49 * * MAP_NR removed
50 * * virt_to_page added
51 *
52 * Plus some comments and type-clarifications.
53 *
54 * Revision 1.3 2000/08/15 16:33:35 bjornw
55 * pmd_bad should recognize both kernel and user page-tables
56 *
57 * Revision 1.2 2000/07/10 17:06:01 bjornw
58 * Fixed warnings
59 *
60 * Revision 1.1.1.1 2000/07/10 16:32:31 bjornw
61 * CRIS architecture, working draft
62 *
63 *
64 * Revision 1.11 2000/05/29 14:55:56 bjornw
65 * Small tweaks of pte_mk routines
66 *
67 * Revision 1.10 2000/01/27 01:49:06 bjornw
68 * * Ooops. The physical frame number in a PTE entry needs to point to the
69 * DRAM directly, not to what the kernel thinks is DRAM (due to KSEG mapping).
70 * Hence we need to strip bit 31 so 0xcXXXXXXX -> 0x4XXXXXXX.
71 *
72 * Revision 1.9 2000/01/26 16:25:50 bjornw
73 * Fixed PAGE_KERNEL bits
74 *
75 * Revision 1.8 2000/01/23 22:53:22 bjornw
76 * Correct flush_tlb_* macros and externs
77 *
78 * Revision 1.7 2000/01/18 16:22:55 bjornw
79 * Use PAGE_MASK instead of PFN_MASK.
80 *
81 * Revision 1.6 2000/01/17 02:42:53 bjornw
82 * Added the pmd_set macro.
83 *
84 * Revision 1.5 2000/01/16 19:53:42 bjornw
85 * Removed VMALLOC_OFFSET. Changed definitions of swapper_pg_dir and zero_page.
86 *
87 * Revision 1.4 2000/01/14 16:38:20 bjornw
88 * PAGE_DIRTY -> PAGE_SILENT_WRITE, removed PAGE_COW from PAGE_COPY.
89 *
90 * Revision 1.3 1999/12/04 20:12:21 bjornw
91 * * PTE bits have moved to asm/mmu.h
92 * * Fixed definitions of the higher level page protection bits
93 * * Added the pte_* functions, including dirty/accessed SW simulation
94 * (these are exactly the same as for the MIPS port)
95 *
96 * Revision 1.2 1999/12/04 00:41:54 bjornw
97 * * Fixed page table offsets, sizes and shifts
98 * * Removed reference to i386 SMP stuff
99 * * Added stray comments about Linux/CRIS mm design
100 * * Include asm/mmu.h which will contain MMU details
101 *
102 * Revision 1.1 1999/12/03 15:04:02 bjornw
103 * Copied from include/asm-etrax100. For the new CRIS architecture.
104 */
105
106 #ifndef _CRIS_PGTABLE_H
107 #define _CRIS_PGTABLE_H
108
109 #include <linux/config.h>
110 #include <asm/mmu.h>
111
112 /*
113 * The Linux memory management assumes a three-level page table setup. On
114 * CRIS, we use that, but "fold" the mid level into the top-level page
115 * table. Since the MMU TLB is software loaded through an interrupt, it
116 * supports any page table structure, so we could have used a three-level
117 * setup, but for the amounts of memory we normally use, a two-level is
118 * probably more efficient.
119 *
120 * This file contains the functions and defines necessary to modify and use
121 * the CRIS page table tree.
122 */
123
124 extern void paging_init(void);
125
126 /* The cache doesn't need to be flushed when TLB entries change because
127 * the cache is mapped to physical memory, not virtual memory
128 */
129 #define flush_cache_all() do { } while (0)
130 #define flush_cache_mm(mm) do { } while (0)
131 #define flush_cache_range(mm, start, end) do { } while (0)
132 #define flush_cache_page(vma, vmaddr) do { } while (0)
133 #define flush_page_to_ram(page) do { } while (0)
134 #define flush_dcache_page(page) do { } while (0)
135 #define flush_icache_range(start, end) do { } while (0)
136 #define flush_icache_page(vma,pg) do { } while (0)
137 #define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
138
139 /*
140 * TLB flushing (implemented in arch/cris/mm/tlb.c):
141 *
142 * - flush_tlb() flushes the current mm struct TLBs
143 * - flush_tlb_all() flushes all processes TLBs
144 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
145 * - flush_tlb_page(vma, vmaddr) flushes one page
146 * - flush_tlb_range(mm, start, end) flushes a range of pages
147 *
148 */
149
150 extern void flush_tlb_all(void);
151 extern void flush_tlb_mm(struct mm_struct *mm);
152 extern void flush_tlb_page(struct vm_area_struct *vma,
153 unsigned long addr);
154 extern void flush_tlb_range(struct mm_struct *mm,
155 unsigned long start,
156 unsigned long end);
157
flush_tlb_pgtables(struct mm_struct * mm,unsigned long start,unsigned long end)158 extern inline void flush_tlb_pgtables(struct mm_struct *mm,
159 unsigned long start, unsigned long end)
160 {
161 /* CRIS does not keep any page table caches in TLB */
162 }
163
164
flush_tlb(void)165 extern inline void flush_tlb(void)
166 {
167 flush_tlb_mm(current->mm);
168 }
169
170 /* Certain architectures need to do special things when pte's
171 * within a page table are directly modified. Thus, the following
172 * hook is made available.
173 */
174 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
175 #define set_pte_atomic(pteptr, pteval) ((*(pteptr)) = (pteval))
176
177 /*
178 * (pmds are folded into pgds so this doesn't get actually called,
179 * but the define is needed for a generic inline function.)
180 */
181 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
182 #define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
183
184 /* PMD_SHIFT determines the size of the area a second-level page table can
185 * map. It is equal to the page size times the number of PTE's that fit in
186 * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
187 */
188
189 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2))
190 #define PMD_SIZE (1UL << PMD_SHIFT)
191 #define PMD_MASK (~(PMD_SIZE-1))
192
193 /* PGDIR_SHIFT determines what a third-level page table entry can map.
194 * Since we fold into a two-level structure, this is the same as PMD_SHIFT.
195 */
196
197 #define PGDIR_SHIFT PMD_SHIFT
198 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
199 #define PGDIR_MASK (~(PGDIR_SIZE-1))
200
201 /*
202 * entries per page directory level: we use a two-level, so
203 * we don't really have any PMD directory physically.
204 * pointers are 4 bytes so we can use the page size and
205 * divide it by 4 (shift by 2).
206 */
207 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2))
208 #define PTRS_PER_PMD 1
209 #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2))
210
211 /* calculate how many PGD entries a user-level program can use
212 * the first mappable virtual address is 0
213 * (TASK_SIZE is the maximum virtual address space)
214 */
215
216 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
217 #define FIRST_USER_PGD_NR 0
218
219 /*
220 * Kernels own virtual memory area.
221 */
222
223 #ifdef CONFIG_CRIS_LOW_MAP
224 #define VMALLOC_START KSEG_7
225 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
226 #define VMALLOC_END KSEG_8
227 #else
228 #define VMALLOC_START KSEG_D
229 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
230 #define VMALLOC_END KSEG_E
231 #endif
232
233 /* Define some higher level generic page attributes. The PTE bits are
234 * defined in asm-cris/mmu.h, and these are just combinations of those.
235 */
236
237 #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
238 #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
239
240 #define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE)
241 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
242
243 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
244 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
245 _PAGE_ACCESSED)
246 #define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW
247 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE)
248 #define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
249 _PAGE_PRESENT | __READABLE | __WRITEABLE)
250 #define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL)
251
252 /*
253 * CRIS can't do page protection for execute, and considers read the same.
254 * Also, write permissions imply read permissions. This is the closest we can
255 * get..
256 */
257
258 #define __P000 PAGE_NONE
259 #define __P001 PAGE_READONLY
260 #define __P010 PAGE_COPY
261 #define __P011 PAGE_COPY
262 #define __P100 PAGE_READONLY
263 #define __P101 PAGE_READONLY
264 #define __P110 PAGE_COPY
265 #define __P111 PAGE_COPY
266
267 #define __S000 PAGE_NONE
268 #define __S001 PAGE_READONLY
269 #define __S010 PAGE_SHARED
270 #define __S011 PAGE_SHARED
271 #define __S100 PAGE_READONLY
272 #define __S101 PAGE_READONLY
273 #define __S110 PAGE_SHARED
274 #define __S111 PAGE_SHARED
275
276 /* zero page used for uninitialized stuff */
277 extern unsigned long empty_zero_page;
278 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
279
280 /* number of bits that fit into a memory pointer */
281 #define BITS_PER_PTR (8*sizeof(unsigned long))
282
283 /* to align the pointer to a pointer address */
284 #define PTR_MASK (~(sizeof(void*)-1))
285
286 /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
287 /* 64-bit machines, beware! SRB. */
288 #define SIZEOF_PTR_LOG2 2
289
290 /* to find an entry in a page-table */
291 #define PAGE_PTR(address) \
292 ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
293
294 /* to set the page-dir */
295 #define SET_PAGE_DIR(tsk,pgdir)
296
297 #define pte_none(x) (!pte_val(x))
298 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
299 #define pte_clear(xp) do { pte_val(*(xp)) = 0; } while (0)
300
301 #define pmd_none(x) (!pmd_val(x))
302 /* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad
303 * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries.
304 */
305 #define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE)
306 #define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
307 #define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
308
309 /*
310 * The "pgd_xxx()" functions here are trivial for a folded two-level
311 * setup: the pgd is never bad, and a pmd always exists (as it's folded
312 * into the pgd entry)
313 */
pgd_none(pgd_t pgd)314 extern inline int pgd_none(pgd_t pgd) { return 0; }
pgd_bad(pgd_t pgd)315 extern inline int pgd_bad(pgd_t pgd) { return 0; }
pgd_present(pgd_t pgd)316 extern inline int pgd_present(pgd_t pgd) { return 1; }
pgd_clear(pgd_t * pgdp)317 extern inline void pgd_clear(pgd_t * pgdp) { }
318
319 /*
320 * The following only work if pte_present() is true.
321 * Undefined behaviour if not..
322 */
323
pte_read(pte_t pte)324 extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
pte_write(pte_t pte)325 extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
pte_exec(pte_t pte)326 extern inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
pte_dirty(pte_t pte)327 extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
pte_young(pte_t pte)328 extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
329
pte_wrprotect(pte_t pte)330 extern inline pte_t pte_wrprotect(pte_t pte)
331 {
332 pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
333 return pte;
334 }
335
pte_rdprotect(pte_t pte)336 extern inline pte_t pte_rdprotect(pte_t pte)
337 {
338 pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ);
339 return pte;
340 }
341
pte_exprotect(pte_t pte)342 extern inline pte_t pte_exprotect(pte_t pte)
343 {
344 pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ);
345 return pte;
346 }
347
pte_mkclean(pte_t pte)348 extern inline pte_t pte_mkclean(pte_t pte)
349 {
350 pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
351 return pte;
352 }
353
pte_mkold(pte_t pte)354 extern inline pte_t pte_mkold(pte_t pte)
355 {
356 pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
357 return pte;
358 }
359
pte_mkwrite(pte_t pte)360 extern inline pte_t pte_mkwrite(pte_t pte)
361 {
362 pte_val(pte) |= _PAGE_WRITE;
363 if (pte_val(pte) & _PAGE_MODIFIED)
364 pte_val(pte) |= _PAGE_SILENT_WRITE;
365 return pte;
366 }
367
pte_mkread(pte_t pte)368 extern inline pte_t pte_mkread(pte_t pte)
369 {
370 pte_val(pte) |= _PAGE_READ;
371 if (pte_val(pte) & _PAGE_ACCESSED)
372 pte_val(pte) |= _PAGE_SILENT_READ;
373 return pte;
374 }
375
pte_mkexec(pte_t pte)376 extern inline pte_t pte_mkexec(pte_t pte)
377 {
378 pte_val(pte) |= _PAGE_READ;
379 if (pte_val(pte) & _PAGE_ACCESSED)
380 pte_val(pte) |= _PAGE_SILENT_READ;
381 return pte;
382 }
383
pte_mkdirty(pte_t pte)384 extern inline pte_t pte_mkdirty(pte_t pte)
385 {
386 pte_val(pte) |= _PAGE_MODIFIED;
387 if (pte_val(pte) & _PAGE_WRITE)
388 pte_val(pte) |= _PAGE_SILENT_WRITE;
389 return pte;
390 }
391
pte_mkyoung(pte_t pte)392 extern inline pte_t pte_mkyoung(pte_t pte)
393 {
394 pte_val(pte) |= _PAGE_ACCESSED;
395 if (pte_val(pte) & _PAGE_READ)
396 {
397 pte_val(pte) |= _PAGE_SILENT_READ;
398 if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) ==
399 (_PAGE_WRITE | _PAGE_MODIFIED))
400 pte_val(pte) |= _PAGE_SILENT_WRITE;
401 }
402 return pte;
403 }
404
405 /*
406 * Conversion functions: convert a page and protection to a page entry,
407 * and a page entry and page directory to the page they refer to.
408 */
409
410 /* What actually goes as arguments to the various functions is less than
411 * obvious, but a rule of thumb is that struct page's goes as struct page *,
412 * really physical DRAM addresses are unsigned long's, and DRAM "virtual"
413 * addresses (the 0xc0xxxxxx's) goes as void *'s.
414 */
415
__mk_pte(void * page,pgprot_t pgprot)416 extern inline pte_t __mk_pte(void * page, pgprot_t pgprot)
417 {
418 pte_t pte;
419 /* the PTE needs a physical address */
420 pte_val(pte) = __pa(page) | pgprot_val(pgprot);
421 return pte;
422 }
423
424 #define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))
425
426 #define mk_pte_phys(physpage, pgprot) \
427 ({ \
428 pte_t __pte; \
429 \
430 pte_val(__pte) = (physpage) + pgprot_val(pgprot); \
431 __pte; \
432 })
433
pte_modify(pte_t pte,pgprot_t newprot)434 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
435 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
436
437
438 /* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval
439 * __pte_page(pte_val) refers to the "virtual" DRAM interval
440 * pte_pagenr refers to the page-number counted starting from the virtual DRAM start
441 */
442
__pte_page(pte_t pte)443 extern inline unsigned long __pte_page(pte_t pte)
444 {
445 /* the PTE contains a physical address */
446 return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
447 }
448
449 #define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
450
451 /* permanent address of a page */
452
453 #define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
454 #define pte_page(pte) (mem_map+pte_pagenr(pte))
455
456 /* only the pte's themselves need to point to physical DRAM (see above)
457 * the pagetable links are purely handled within the kernel SW and thus
458 * don't need the __pa and __va transformations.
459 */
460
pmd_page(pmd_t pmd)461 extern inline unsigned long pmd_page(pmd_t pmd)
462 { return pmd_val(pmd) & PAGE_MASK; }
463
pmd_set(pmd_t * pmdp,pte_t * ptep)464 extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
465 { pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; }
466
467 /* to find an entry in a page-table-directory. */
468 #define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
469
470 /* to find an entry in a page-table-directory */
pgd_offset(struct mm_struct * mm,unsigned long address)471 extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
472 {
473 return mm->pgd + pgd_index(address);
474 }
475
476 /* to find an entry in a kernel page-table-directory */
477 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
478
479 /* Find an entry in the second-level page table.. */
pmd_offset(pgd_t * dir,unsigned long address)480 extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
481 {
482 return (pmd_t *) dir;
483 }
484
485 /* Find an entry in the third-level page table.. */
pte_offset(pmd_t * dir,unsigned long address)486 extern inline pte_t * pte_offset(pmd_t * dir, unsigned long address)
487 {
488 return (pte_t *) pmd_page(*dir) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
489 }
490
491 #define pte_ERROR(e) \
492 printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
493 #define pmd_ERROR(e) \
494 printk("%s:%d: bad pmd %p(%08lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
495 #define pgd_ERROR(e) \
496 printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
497
498 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
499
500 /*
501 * CRIS doesn't have any external MMU info: the kernel page
502 * tables contain all the necessary information.
503 *
504 * Actually I am not sure on what this could be used for.
505 */
update_mmu_cache(struct vm_area_struct * vma,unsigned long address,pte_t pte)506 extern inline void update_mmu_cache(struct vm_area_struct * vma,
507 unsigned long address, pte_t pte)
508 {
509 }
510
511 /* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
512 /* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */
513
514 #define SWP_TYPE(x) (((x).val >> 5) & 0x7f)
515 #define SWP_OFFSET(x) ((x).val >> 12)
516 #define SWP_ENTRY(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) })
517 #define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
518 #define swp_entry_to_pte(x) ((pte_t) { (x).val })
519
520 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
521 #define PageSkip(page) (0)
522 #define kern_addr_valid(addr) (1)
523
524 #include <asm-generic/pgtable.h>
525
526 /*
527 * No page table caches to initialise
528 */
529 #define pgtable_cache_init() do { } while (0)
530
531 #endif /* _CRIS_PGTABLE_H */
532