1 /* 2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family 3 * of PCI-SCSI IO processors. 4 * 5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 6 * 7 * This driver is derived from the Linux sym53c8xx driver. 8 * Copyright (C) 1998-2000 Gerard Roudier 9 * 10 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 11 * a port of the FreeBSD ncr driver to Linux-1.2.13. 12 * 13 * The original ncr driver has been written for 386bsd and FreeBSD by 14 * Wolfgang Stanglmeier <wolf@cologne.de> 15 * Stefan Esser <se@mi.Uni-Koeln.de> 16 * Copyright (C) 1994 Wolfgang Stanglmeier 17 * 18 * Other major contributions: 19 * 20 * NVRAM detection and reading. 21 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 22 * 23 *----------------------------------------------------------------------------- 24 * 25 * Redistribution and use in source and binary forms, with or without 26 * modification, are permitted provided that the following conditions 27 * are met: 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. The name of the author may not be used to endorse or promote products 31 * derived from this software without specific prior written permission. 32 * 33 * Where this Software is combined with software released under the terms of 34 * the GNU Public License ("GPL") and the terms of the GPL would require the 35 * combined work to also be released under the terms of the GPL, the terms 36 * and conditions of this License will apply in addition to those of the 37 * GPL with the exception of any terms or conditions of this License that 38 * conflict with, or are expressly prohibited by, the GPL. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 44 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 53 /* 54 * Scripts for SYMBIOS-Processor 55 * 56 * We have to know the offsets of all labels before we reach 57 * them (for forward jumps). Therefore we declare a struct 58 * here. If you make changes inside the script, 59 * 60 * DONT FORGET TO CHANGE THE LENGTHS HERE! 61 */ 62 63 /* 64 * Script fragments which are loaded into the on-chip RAM 65 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips. 66 * Must not exceed 4K bytes. 67 */ 68 struct SYM_FWA_SCR { 69 u32 start [ 14]; 70 u32 getjob_begin [ 4]; 71 u32 getjob_end [ 4]; 72 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT 73 u32 select [ 6]; 74 #else 75 u32 select [ 4]; 76 #endif 77 #if SYM_CONF_DMA_ADDRESSING_MODE == 2 78 u32 is_dmap_dirty [ 4]; 79 #endif 80 u32 wf_sel_done [ 2]; 81 u32 sel_done [ 2]; 82 u32 send_ident [ 2]; 83 #ifdef SYM_CONF_IARB_SUPPORT 84 u32 select2 [ 8]; 85 #else 86 u32 select2 [ 2]; 87 #endif 88 u32 command [ 2]; 89 u32 dispatch [ 28]; 90 u32 sel_no_cmd [ 10]; 91 u32 init [ 6]; 92 u32 clrack [ 4]; 93 u32 datai_done [ 10]; 94 u32 datai_done_wsr [ 20]; 95 u32 datao_done [ 10]; 96 u32 datao_done_wss [ 6]; 97 u32 datai_phase [ 4]; 98 u32 datao_phase [ 6]; 99 u32 msg_in [ 2]; 100 u32 msg_in2 [ 10]; 101 #ifdef SYM_CONF_IARB_SUPPORT 102 u32 status [ 14]; 103 #else 104 u32 status [ 10]; 105 #endif 106 u32 complete [ 6]; 107 u32 complete2 [ 12]; 108 u32 done [ 14]; 109 u32 done_end [ 2]; 110 u32 complete_error [ 4]; 111 u32 save_dp [ 12]; 112 u32 restore_dp [ 8]; 113 u32 disconnect [ 12]; 114 #ifdef SYM_CONF_IARB_SUPPORT 115 u32 idle [ 4]; 116 #else 117 u32 idle [ 2]; 118 #endif 119 #ifdef SYM_CONF_IARB_SUPPORT 120 u32 ungetjob [ 6]; 121 #else 122 u32 ungetjob [ 4]; 123 #endif 124 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT 125 u32 reselect [ 4]; 126 #else 127 u32 reselect [ 2]; 128 #endif 129 u32 reselected [ 22]; 130 u32 resel_scntl4 [ 20]; 131 u32 resel_lun0 [ 6]; 132 #if SYM_CONF_MAX_TASK*4 > 512 133 u32 resel_tag [ 26]; 134 #elif SYM_CONF_MAX_TASK*4 > 256 135 u32 resel_tag [ 20]; 136 #else 137 u32 resel_tag [ 16]; 138 #endif 139 u32 resel_dsa [ 2]; 140 u32 resel_dsa1 [ 4]; 141 u32 resel_no_tag [ 6]; 142 u32 data_in [SYM_CONF_MAX_SG * 2]; 143 u32 data_in2 [ 4]; 144 u32 data_out [SYM_CONF_MAX_SG * 2]; 145 u32 data_out2 [ 4]; 146 u32 pm0_data [ 12]; 147 u32 pm0_data_out [ 6]; 148 u32 pm0_data_end [ 6]; 149 u32 pm1_data [ 12]; 150 u32 pm1_data_out [ 6]; 151 u32 pm1_data_end [ 6]; 152 }; 153 154 /* 155 * Script fragments which stay in main memory for all chips 156 * except for chips that support 8K on-chip RAM. 157 */ 158 struct SYM_FWB_SCR { 159 u32 start64 [ 2]; 160 u32 no_data [ 2]; 161 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT 162 u32 sel_for_abort [ 18]; 163 #else 164 u32 sel_for_abort [ 16]; 165 #endif 166 u32 sel_for_abort_1 [ 2]; 167 u32 msg_in_etc [ 12]; 168 u32 msg_received [ 4]; 169 u32 msg_weird_seen [ 4]; 170 u32 msg_extended [ 20]; 171 u32 msg_bad [ 6]; 172 u32 msg_weird [ 4]; 173 u32 msg_weird1 [ 8]; 174 175 u32 wdtr_resp [ 6]; 176 u32 send_wdtr [ 4]; 177 u32 sdtr_resp [ 6]; 178 u32 send_sdtr [ 4]; 179 u32 ppr_resp [ 6]; 180 u32 send_ppr [ 4]; 181 u32 nego_bad_phase [ 4]; 182 u32 msg_out [ 4]; 183 u32 msg_out_done [ 4]; 184 u32 data_ovrun [ 2]; 185 u32 data_ovrun1 [ 22]; 186 u32 data_ovrun2 [ 8]; 187 u32 abort_resel [ 16]; 188 u32 resend_ident [ 4]; 189 u32 ident_break [ 4]; 190 u32 ident_break_atn [ 4]; 191 u32 sdata_in [ 6]; 192 u32 resel_bad_lun [ 4]; 193 u32 bad_i_t_l [ 4]; 194 u32 bad_i_t_l_q [ 4]; 195 u32 bad_status [ 6]; 196 u32 pm_handle [ 20]; 197 u32 pm_handle1 [ 4]; 198 u32 pm_save [ 4]; 199 u32 pm0_save [ 12]; 200 u32 pm_save_end [ 4]; 201 u32 pm1_save [ 14]; 202 203 /* WSR handling */ 204 u32 pm_wsr_handle [ 38]; 205 u32 wsr_ma_helper [ 4]; 206 207 #ifdef SYM_OPT_HANDLE_DIR_UNKNOWN 208 /* Unknown direction handling */ 209 u32 data_io [ 2]; 210 u32 data_io_in [ 2]; 211 u32 data_io_com [ 6]; 212 u32 data_io_out [ 8]; 213 #endif 214 /* Data area */ 215 u32 zero [ 1]; 216 u32 scratch [ 1]; 217 u32 pm0_data_addr [ 1]; 218 u32 pm1_data_addr [ 1]; 219 u32 done_pos [ 1]; 220 u32 startpos [ 1]; 221 u32 targtbl [ 1]; 222 }; 223 224 /* 225 * Script fragments used at initialisations. 226 * Only runs out of main memory. 227 */ 228 struct SYM_FWZ_SCR { 229 u32 snooptest [ 6]; 230 u32 snoopend [ 2]; 231 #ifdef SYM_OPT_NO_BUS_MEMORY_MAPPING 232 u32 start_ram [ 1]; 233 u32 scripta0_ba [ 4]; 234 u32 start_ram64 [ 3]; 235 u32 scripta0_ba64 [ 3]; 236 u32 scriptb0_ba64 [ 6]; 237 u32 ram_seg64 [ 1]; 238 #endif 239 }; 240 241 static struct SYM_FWA_SCR SYM_FWA_SCR = { 242 /*--------------------------< START >----------------------------*/ { 243 /* 244 * Switch the LED on. 245 * Will be patched with a NO_OP if LED 246 * not needed or not desired. 247 */ 248 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 249 0, 250 /* 251 * Clear SIGP. 252 */ 253 SCR_FROM_REG (ctest2), 254 0, 255 /* 256 * Stop here if the C code wants to perform 257 * some error recovery procedure manually. 258 * (Indicate this by setting SEM in ISTAT) 259 */ 260 SCR_FROM_REG (istat), 261 0, 262 /* 263 * Report to the C code the next position in 264 * the start queue the SCRIPTS will schedule. 265 * The C code must not change SCRATCHA. 266 */ 267 SCR_LOAD_ABS (scratcha, 4), 268 PADDR_B (startpos), 269 SCR_INT ^ IFTRUE (MASK (SEM, SEM)), 270 SIR_SCRIPT_STOPPED, 271 /* 272 * Start the next job. 273 * 274 * @DSA = start point for this job. 275 * SCRATCHA = address of this job in the start queue. 276 * 277 * We will restore startpos with SCRATCHA if we fails the 278 * arbitration or if it is the idle job. 279 * 280 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS 281 * is a critical path. If it is partially executed, it then 282 * may happen that the job address is not yet in the DSA 283 * and the next queue position points to the next JOB. 284 */ 285 SCR_LOAD_ABS (dsa, 4), 286 PADDR_B (startpos), 287 SCR_LOAD_REL (temp, 4), 288 4, 289 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{ 290 SCR_STORE_ABS (temp, 4), 291 PADDR_B (startpos), 292 SCR_LOAD_REL (dsa, 4), 293 0, 294 }/*-------------------------< GETJOB_END >-----------------------*/,{ 295 SCR_LOAD_REL (temp, 4), 296 0, 297 SCR_RETURN, 298 0, 299 }/*-------------------------< SELECT >---------------------------*/,{ 300 /* 301 * DSA contains the address of a scheduled 302 * data structure. 303 * 304 * SCRATCHA contains the address of the start queue 305 * entry which points to the next job. 306 * 307 * Set Initiator mode. 308 * 309 * (Target mode is left as an exercise for the reader) 310 */ 311 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT 312 SCR_CLR (SCR_TRG), 313 0, 314 #endif 315 /* 316 * And try to select this target. 317 */ 318 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select), 319 PADDR_A (ungetjob), 320 /* 321 * Now there are 4 possibilities: 322 * 323 * (1) The chip looses arbitration. 324 * This is ok, because it will try again, 325 * when the bus becomes idle. 326 * (But beware of the timeout function!) 327 * 328 * (2) The chip is reselected. 329 * Then the script processor takes the jump 330 * to the RESELECT label. 331 * 332 * (3) The chip wins arbitration. 333 * Then it will execute SCRIPTS instruction until 334 * the next instruction that checks SCSI phase. 335 * Then will stop and wait for selection to be 336 * complete or selection time-out to occur. 337 * 338 * After having won arbitration, the SCRIPTS 339 * processor is able to execute instructions while 340 * the SCSI core is performing SCSI selection. 341 */ 342 /* 343 * Initialize the status registers 344 */ 345 SCR_LOAD_REL (scr0, 4), 346 offsetof (struct sym_ccb, phys.head.status), 347 /* 348 * We may need help from CPU if the DMA segment 349 * registers aren't up-to-date for this IO. 350 * Patched with NOOP for chips that donnot 351 * support DAC addressing. 352 */ 353 #if SYM_CONF_DMA_ADDRESSING_MODE == 2 354 }/*-------------------------< IS_DMAP_DIRTY >--------------------*/,{ 355 SCR_FROM_REG (HX_REG), 356 0, 357 SCR_INT ^ IFTRUE (MASK (HX_DMAP_DIRTY, HX_DMAP_DIRTY)), 358 SIR_DMAP_DIRTY, 359 #endif 360 }/*-------------------------< WF_SEL_DONE >----------------------*/,{ 361 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), 362 SIR_SEL_ATN_NO_MSG_OUT, 363 }/*-------------------------< SEL_DONE >-------------------------*/,{ 364 /* 365 * C1010-33 errata work-around. 366 * Due to a race, the SCSI core may not have 367 * loaded SCNTL3 on SEL_TBL instruction. 368 * We reload it once phase is stable. 369 * Patched with a NOOP for other chips. 370 */ 371 SCR_LOAD_REL (scntl3, 1), 372 offsetof(struct sym_dsb, select.sel_scntl3), 373 }/*-------------------------< SEND_IDENT >-----------------------*/,{ 374 /* 375 * Selection complete. 376 * Send the IDENTIFY and possibly the TAG message 377 * and negotiation message if present. 378 */ 379 SCR_MOVE_TBL ^ SCR_MSG_OUT, 380 offsetof (struct sym_dsb, smsg), 381 }/*-------------------------< SELECT2 >--------------------------*/,{ 382 #ifdef SYM_CONF_IARB_SUPPORT 383 /* 384 * Set IMMEDIATE ARBITRATION if we have been given 385 * a hint to do so. (Some job to do after this one). 386 */ 387 SCR_FROM_REG (HF_REG), 388 0, 389 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), 390 8, 391 SCR_REG_REG (scntl1, SCR_OR, IARB), 392 0, 393 #endif 394 /* 395 * Anticipate the COMMAND phase. 396 * This is the PHASE we expect at this point. 397 */ 398 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)), 399 PADDR_A (sel_no_cmd), 400 }/*-------------------------< COMMAND >--------------------------*/,{ 401 /* 402 * ... and send the command 403 */ 404 SCR_MOVE_TBL ^ SCR_COMMAND, 405 offsetof (struct sym_dsb, cmd), 406 }/*-------------------------< DISPATCH >-------------------------*/,{ 407 /* 408 * MSG_IN is the only phase that shall be 409 * entered at least once for each (re)selection. 410 * So we test it first. 411 */ 412 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 413 PADDR_A (msg_in), 414 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)), 415 PADDR_A (datao_phase), 416 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)), 417 PADDR_A (datai_phase), 418 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)), 419 PADDR_A (status), 420 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)), 421 PADDR_A (command), 422 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)), 423 PADDR_B (msg_out), 424 /* 425 * Discard as many illegal phases as 426 * required and tell the C code about. 427 */ 428 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)), 429 16, 430 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT, 431 HADDR_1 (scratch), 432 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)), 433 -16, 434 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)), 435 16, 436 SCR_MOVE_ABS (1) ^ SCR_ILG_IN, 437 HADDR_1 (scratch), 438 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)), 439 -16, 440 SCR_INT, 441 SIR_BAD_PHASE, 442 SCR_JUMP, 443 PADDR_A (dispatch), 444 }/*-------------------------< SEL_NO_CMD >-----------------------*/,{ 445 /* 446 * The target does not switch to command 447 * phase after IDENTIFY has been sent. 448 * 449 * If it stays in MSG OUT phase send it 450 * the IDENTIFY again. 451 */ 452 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 453 PADDR_B (resend_ident), 454 /* 455 * If target does not switch to MSG IN phase 456 * and we sent a negotiation, assert the 457 * failure immediately. 458 */ 459 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 460 PADDR_A (dispatch), 461 SCR_FROM_REG (HS_REG), 462 0, 463 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), 464 SIR_NEGO_FAILED, 465 /* 466 * Jump to dispatcher. 467 */ 468 SCR_JUMP, 469 PADDR_A (dispatch), 470 }/*-------------------------< INIT >-----------------------------*/,{ 471 /* 472 * Wait for the SCSI RESET signal to be 473 * inactive before restarting operations, 474 * since the chip may hang on SEL_ATN 475 * if SCSI RESET is active. 476 */ 477 SCR_FROM_REG (sstat0), 478 0, 479 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), 480 -16, 481 SCR_JUMP, 482 PADDR_A (start), 483 }/*-------------------------< CLRACK >---------------------------*/,{ 484 /* 485 * Terminate possible pending message phase. 486 */ 487 SCR_CLR (SCR_ACK), 488 0, 489 SCR_JUMP, 490 PADDR_A (dispatch), 491 }/*-------------------------< DATAI_DONE >-----------------------*/,{ 492 /* 493 * Save current pointer to LASTP. 494 */ 495 SCR_STORE_REL (temp, 4), 496 offsetof (struct sym_ccb, phys.head.lastp), 497 /* 498 * If the SWIDE is not full, jump to dispatcher. 499 * We anticipate a STATUS phase. 500 */ 501 SCR_FROM_REG (scntl2), 502 0, 503 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)), 504 PADDR_A (datai_done_wsr), 505 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), 506 PADDR_A (status), 507 SCR_JUMP, 508 PADDR_A (dispatch), 509 }/*-------------------------< DATAI_DONE_WSR >-------------------*/,{ 510 /* 511 * The SWIDE is full. 512 * Clear this condition. 513 */ 514 SCR_REG_REG (scntl2, SCR_OR, WSR), 515 0, 516 /* 517 * We are expecting an IGNORE RESIDUE message 518 * from the device, otherwise we are in data 519 * overrun condition. Check against MSG_IN phase. 520 */ 521 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 522 SIR_SWIDE_OVERRUN, 523 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 524 PADDR_A (dispatch), 525 /* 526 * We are in MSG_IN phase, 527 * Read the first byte of the message. 528 * If it is not an IGNORE RESIDUE message, 529 * signal overrun and jump to message 530 * processing. 531 */ 532 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 533 HADDR_1 (msgin[0]), 534 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)), 535 SIR_SWIDE_OVERRUN, 536 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)), 537 PADDR_A (msg_in2), 538 /* 539 * We got the message we expected. 540 * Read the 2nd byte, and jump to dispatcher. 541 */ 542 SCR_CLR (SCR_ACK), 543 0, 544 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 545 HADDR_1 (msgin[1]), 546 SCR_CLR (SCR_ACK), 547 0, 548 SCR_JUMP, 549 PADDR_A (dispatch), 550 }/*-------------------------< DATAO_DONE >-----------------------*/,{ 551 /* 552 * Save current pointer to LASTP. 553 */ 554 SCR_STORE_REL (temp, 4), 555 offsetof (struct sym_ccb, phys.head.lastp), 556 /* 557 * If the SODL is not full jump to dispatcher. 558 * We anticipate a STATUS phase. 559 */ 560 SCR_FROM_REG (scntl2), 561 0, 562 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)), 563 PADDR_A (datao_done_wss), 564 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), 565 PADDR_A (status), 566 SCR_JUMP, 567 PADDR_A (dispatch), 568 }/*-------------------------< DATAO_DONE_WSS >-------------------*/,{ 569 /* 570 * The SODL is full, clear this condition. 571 */ 572 SCR_REG_REG (scntl2, SCR_OR, WSS), 573 0, 574 /* 575 * And signal a DATA UNDERRUN condition 576 * to the C code. 577 */ 578 SCR_INT, 579 SIR_SODL_UNDERRUN, 580 SCR_JUMP, 581 PADDR_A (dispatch), 582 }/*-------------------------< DATAI_PHASE >----------------------*/,{ 583 /* 584 * Jump to current pointer. 585 */ 586 SCR_LOAD_REL (temp, 4), 587 offsetof (struct sym_ccb, phys.head.lastp), 588 SCR_RETURN, 589 0, 590 }/*-------------------------< DATAO_PHASE >----------------------*/,{ 591 /* 592 * C1010-66 errata work-around. 593 * Extra clocks of data hold must be inserted 594 * in DATA OUT phase on 33 MHz PCI BUS. 595 * Patched with a NOOP for other chips. 596 */ 597 SCR_REG_REG (scntl4, SCR_OR, (XCLKH_DT|XCLKH_ST)), 598 0, 599 /* 600 * Jump to current pointer. 601 */ 602 SCR_LOAD_REL (temp, 4), 603 offsetof (struct sym_ccb, phys.head.lastp), 604 SCR_RETURN, 605 0, 606 }/*-------------------------< MSG_IN >---------------------------*/,{ 607 /* 608 * Get the first byte of the message. 609 * 610 * The script processor doesn't negate the 611 * ACK signal after this transfer. 612 */ 613 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 614 HADDR_1 (msgin[0]), 615 }/*-------------------------< MSG_IN2 >--------------------------*/,{ 616 /* 617 * Check first against 1 byte messages 618 * that we handle from SCRIPTS. 619 */ 620 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)), 621 PADDR_A (complete), 622 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)), 623 PADDR_A (disconnect), 624 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)), 625 PADDR_A (save_dp), 626 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)), 627 PADDR_A (restore_dp), 628 /* 629 * We handle all other messages from the 630 * C code, so no need to waste on-chip RAM 631 * for those ones. 632 */ 633 SCR_JUMP, 634 PADDR_B (msg_in_etc), 635 }/*-------------------------< STATUS >---------------------------*/,{ 636 /* 637 * get the status 638 */ 639 SCR_MOVE_ABS (1) ^ SCR_STATUS, 640 HADDR_1 (scratch), 641 #ifdef SYM_CONF_IARB_SUPPORT 642 /* 643 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION, 644 * since we may have to tamper the start queue from 645 * the C code. 646 */ 647 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)), 648 8, 649 SCR_REG_REG (scntl1, SCR_AND, ~IARB), 650 0, 651 #endif 652 /* 653 * save status to scsi_status. 654 * mark as complete. 655 */ 656 SCR_TO_REG (SS_REG), 657 0, 658 SCR_LOAD_REG (HS_REG, HS_COMPLETE), 659 0, 660 /* 661 * Anticipate the MESSAGE PHASE for 662 * the TASK COMPLETE message. 663 */ 664 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 665 PADDR_A (msg_in), 666 SCR_JUMP, 667 PADDR_A (dispatch), 668 }/*-------------------------< COMPLETE >-------------------------*/,{ 669 /* 670 * Complete message. 671 * 672 * When we terminate the cycle by clearing ACK, 673 * the target may disconnect immediately. 674 * 675 * We don't want to be told of an "unexpected disconnect", 676 * so we disable this feature. 677 */ 678 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 679 0, 680 /* 681 * Terminate cycle ... 682 */ 683 SCR_CLR (SCR_ACK|SCR_ATN), 684 0, 685 /* 686 * ... and wait for the disconnect. 687 */ 688 SCR_WAIT_DISC, 689 0, 690 }/*-------------------------< COMPLETE2 >------------------------*/,{ 691 /* 692 * Save host status. 693 */ 694 SCR_STORE_REL (scr0, 4), 695 offsetof (struct sym_ccb, phys.head.status), 696 /* 697 * Some bridges may reorder DMA writes to memory. 698 * We donnot want the CPU to deal with completions 699 * without all the posted write having been flushed 700 * to memory. This DUMMY READ should flush posted 701 * buffers prior to the CPU having to deal with 702 * completions. 703 */ 704 SCR_LOAD_REL (scr0, 4), /* DUMMY READ */ 705 offsetof (struct sym_ccb, phys.head.status), 706 707 /* 708 * If command resulted in not GOOD status, 709 * call the C code if needed. 710 */ 711 SCR_FROM_REG (SS_REG), 712 0, 713 SCR_CALL ^ IFFALSE (DATA (S_GOOD)), 714 PADDR_B (bad_status), 715 /* 716 * If we performed an auto-sense, call 717 * the C code to synchronyze task aborts 718 * with UNIT ATTENTION conditions. 719 */ 720 SCR_FROM_REG (HF_REG), 721 0, 722 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), 723 PADDR_A (complete_error), 724 }/*-------------------------< DONE >-----------------------------*/,{ 725 /* 726 * Copy the DSA to the DONE QUEUE and 727 * signal completion to the host. 728 * If we are interrupted between DONE 729 * and DONE_END, we must reset, otherwise 730 * the completed CCB may be lost. 731 */ 732 SCR_STORE_ABS (dsa, 4), 733 PADDR_B (scratch), 734 SCR_LOAD_ABS (dsa, 4), 735 PADDR_B (done_pos), 736 SCR_LOAD_ABS (scratcha, 4), 737 PADDR_B (scratch), 738 SCR_STORE_REL (scratcha, 4), 739 0, 740 /* 741 * The instruction below reads the DONE QUEUE next 742 * free position from memory. 743 * In addition it ensures that all PCI posted writes 744 * are flushed and so the DSA value of the done 745 * CCB is visible by the CPU before INTFLY is raised. 746 */ 747 SCR_LOAD_REL (scratcha, 4), 748 4, 749 SCR_INT_FLY, 750 0, 751 SCR_STORE_ABS (scratcha, 4), 752 PADDR_B (done_pos), 753 }/*-------------------------< DONE_END >-------------------------*/,{ 754 SCR_JUMP, 755 PADDR_A (start), 756 }/*-------------------------< COMPLETE_ERROR >-------------------*/,{ 757 SCR_LOAD_ABS (scratcha, 4), 758 PADDR_B (startpos), 759 SCR_INT, 760 SIR_COMPLETE_ERROR, 761 }/*-------------------------< SAVE_DP >--------------------------*/,{ 762 /* 763 * Clear ACK immediately. 764 * No need to delay it. 765 */ 766 SCR_CLR (SCR_ACK), 767 0, 768 /* 769 * Keep track we received a SAVE DP, so 770 * we will switch to the other PM context 771 * on the next PM since the DP may point 772 * to the current PM context. 773 */ 774 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 775 0, 776 /* 777 * SAVE_DP message: 778 * Copy LASTP to SAVEP. 779 */ 780 SCR_LOAD_REL (scratcha, 4), 781 offsetof (struct sym_ccb, phys.head.lastp), 782 SCR_STORE_REL (scratcha, 4), 783 offsetof (struct sym_ccb, phys.head.savep), 784 /* 785 * Anticipate the MESSAGE PHASE for 786 * the DISCONNECT message. 787 */ 788 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 789 PADDR_A (msg_in), 790 SCR_JUMP, 791 PADDR_A (dispatch), 792 }/*-------------------------< RESTORE_DP >-----------------------*/,{ 793 /* 794 * Clear ACK immediately. 795 * No need to delay it. 796 */ 797 SCR_CLR (SCR_ACK), 798 0, 799 /* 800 * Copy SAVEP to LASTP. 801 */ 802 SCR_LOAD_REL (scratcha, 4), 803 offsetof (struct sym_ccb, phys.head.savep), 804 SCR_STORE_REL (scratcha, 4), 805 offsetof (struct sym_ccb, phys.head.lastp), 806 SCR_JUMP, 807 PADDR_A (dispatch), 808 }/*-------------------------< DISCONNECT >-----------------------*/,{ 809 /* 810 * DISCONNECTing ... 811 * 812 * disable the "unexpected disconnect" feature, 813 * and remove the ACK signal. 814 */ 815 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 816 0, 817 SCR_CLR (SCR_ACK|SCR_ATN), 818 0, 819 /* 820 * Wait for the disconnect. 821 */ 822 SCR_WAIT_DISC, 823 0, 824 /* 825 * Status is: DISCONNECTED. 826 */ 827 SCR_LOAD_REG (HS_REG, HS_DISCONNECT), 828 0, 829 /* 830 * Save host status. 831 */ 832 SCR_STORE_REL (scr0, 4), 833 offsetof (struct sym_ccb, phys.head.status), 834 SCR_JUMP, 835 PADDR_A (start), 836 }/*-------------------------< IDLE >-----------------------------*/,{ 837 /* 838 * Nothing to do? 839 * Switch the LED off and wait for reselect. 840 * Will be patched with a NO_OP if LED 841 * not needed or not desired. 842 */ 843 SCR_REG_REG (gpreg, SCR_OR, 0x01), 844 0, 845 #ifdef SYM_CONF_IARB_SUPPORT 846 SCR_JUMPR, 847 8, 848 #endif 849 }/*-------------------------< UNGETJOB >-------------------------*/,{ 850 #ifdef SYM_CONF_IARB_SUPPORT 851 /* 852 * Set IMMEDIATE ARBITRATION, for the next time. 853 * This will give us better chance to win arbitration 854 * for the job we just wanted to do. 855 */ 856 SCR_REG_REG (scntl1, SCR_OR, IARB), 857 0, 858 #endif 859 /* 860 * We are not able to restart the SCRIPTS if we are 861 * interrupted and these instruction haven't been 862 * all executed. BTW, this is very unlikely to 863 * happen, but we check that from the C code. 864 */ 865 SCR_LOAD_REG (dsa, 0xff), 866 0, 867 SCR_STORE_ABS (scratcha, 4), 868 PADDR_B (startpos), 869 }/*-------------------------< RESELECT >-------------------------*/,{ 870 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT 871 /* 872 * Make sure we are in initiator mode. 873 */ 874 SCR_CLR (SCR_TRG), 875 0, 876 #endif 877 /* 878 * Sleep waiting for a reselection. 879 */ 880 SCR_WAIT_RESEL, 881 PADDR_A(start), 882 }/*-------------------------< RESELECTED >-----------------------*/,{ 883 /* 884 * Switch the LED on. 885 * Will be patched with a NO_OP if LED 886 * not needed or not desired. 887 */ 888 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 889 0, 890 /* 891 * load the target id into the sdid 892 */ 893 SCR_REG_SFBR (ssid, SCR_AND, 0x8F), 894 0, 895 SCR_TO_REG (sdid), 896 0, 897 /* 898 * Load the target control block address 899 */ 900 SCR_LOAD_ABS (dsa, 4), 901 PADDR_B (targtbl), 902 SCR_SFBR_REG (dsa, SCR_SHL, 0), 903 0, 904 SCR_REG_REG (dsa, SCR_SHL, 0), 905 0, 906 SCR_REG_REG (dsa, SCR_AND, 0x3c), 907 0, 908 SCR_LOAD_REL (dsa, 4), 909 0, 910 /* 911 * We expect MESSAGE IN phase. 912 * If not, get help from the C code. 913 */ 914 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 915 SIR_RESEL_NO_MSG_IN, 916 /* 917 * Load the legacy synchronous transfer registers. 918 */ 919 SCR_LOAD_REL (scntl3, 1), 920 offsetof(struct sym_tcb, head.wval), 921 SCR_LOAD_REL (sxfer, 1), 922 offsetof(struct sym_tcb, head.sval), 923 }/*-------------------------< RESEL_SCNTL4 >---------------------*/,{ 924 /* 925 * The C1010 uses a new synchronous timing scheme. 926 * Will be patched with a NO_OP if not a C1010. 927 */ 928 SCR_LOAD_REL (scntl4, 1), 929 offsetof(struct sym_tcb, head.uval), 930 /* 931 * Get the IDENTIFY message. 932 */ 933 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 934 HADDR_1 (msgin), 935 /* 936 * If IDENTIFY LUN #0, use a faster path 937 * to find the LCB structure. 938 */ 939 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), 940 PADDR_A (resel_lun0), 941 /* 942 * If message isn't an IDENTIFY, 943 * tell the C code about. 944 */ 945 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), 946 SIR_RESEL_NO_IDENTIFY, 947 /* 948 * It is an IDENTIFY message, 949 * Load the LUN control block address. 950 */ 951 SCR_LOAD_REL (dsa, 4), 952 offsetof(struct sym_tcb, head.luntbl_sa), 953 SCR_SFBR_REG (dsa, SCR_SHL, 0), 954 0, 955 SCR_REG_REG (dsa, SCR_SHL, 0), 956 0, 957 SCR_REG_REG (dsa, SCR_AND, 0xfc), 958 0, 959 SCR_LOAD_REL (dsa, 4), 960 0, 961 SCR_JUMPR, 962 8, 963 }/*-------------------------< RESEL_LUN0 >-----------------------*/,{ 964 /* 965 * LUN 0 special case (but usual one :)) 966 */ 967 SCR_LOAD_REL (dsa, 4), 968 offsetof(struct sym_tcb, head.lun0_sa), 969 /* 970 * Jump indirectly to the reselect action for this LUN. 971 */ 972 SCR_LOAD_REL (temp, 4), 973 offsetof(struct sym_lcb, head.resel_sa), 974 SCR_RETURN, 975 0, 976 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */ 977 }/*-------------------------< RESEL_TAG >------------------------*/,{ 978 /* 979 * ACK the IDENTIFY previously received. 980 */ 981 SCR_CLR (SCR_ACK), 982 0, 983 /* 984 * It shall be a tagged command. 985 * Read SIMPLE+TAG. 986 * The C code will deal with errors. 987 * Agressive optimization, is'nt it? :) 988 */ 989 SCR_MOVE_ABS (2) ^ SCR_MSG_IN, 990 HADDR_1 (msgin), 991 /* 992 * Load the pointer to the tagged task 993 * table for this LUN. 994 */ 995 SCR_LOAD_REL (dsa, 4), 996 offsetof(struct sym_lcb, head.itlq_tbl_sa), 997 /* 998 * The SIDL still contains the TAG value. 999 * Agressive optimization, isn't it? :):) 1000 */ 1001 SCR_REG_SFBR (sidl, SCR_SHL, 0), 1002 0, 1003 #if SYM_CONF_MAX_TASK*4 > 512 1004 SCR_JUMPR ^ IFFALSE (CARRYSET), 1005 8, 1006 SCR_REG_REG (dsa1, SCR_OR, 2), 1007 0, 1008 SCR_REG_REG (sfbr, SCR_SHL, 0), 1009 0, 1010 SCR_JUMPR ^ IFFALSE (CARRYSET), 1011 8, 1012 SCR_REG_REG (dsa1, SCR_OR, 1), 1013 0, 1014 #elif SYM_CONF_MAX_TASK*4 > 256 1015 SCR_JUMPR ^ IFFALSE (CARRYSET), 1016 8, 1017 SCR_REG_REG (dsa1, SCR_OR, 1), 1018 0, 1019 #endif 1020 /* 1021 * Retrieve the DSA of this task. 1022 * JUMP indirectly to the restart point of the CCB. 1023 */ 1024 SCR_SFBR_REG (dsa, SCR_AND, 0xfc), 1025 0, 1026 SCR_LOAD_REL (dsa, 4), 1027 0, 1028 SCR_LOAD_REL (temp, 4), 1029 offsetof(struct sym_ccb, phys.head.go.restart), 1030 SCR_RETURN, 1031 0, 1032 /* In normal situations we branch to RESEL_DSA */ 1033 }/*-------------------------< RESEL_DSA >------------------------*/,{ 1034 /* 1035 * ACK the IDENTIFY or TAG previously received. 1036 */ 1037 SCR_CLR (SCR_ACK), 1038 0, 1039 }/*-------------------------< RESEL_DSA1 >-----------------------*/,{ 1040 /* 1041 * Initialize the status registers 1042 */ 1043 SCR_LOAD_REL (scr0, 4), 1044 offsetof (struct sym_ccb, phys.head.status), 1045 /* 1046 * Jump to dispatcher. 1047 */ 1048 SCR_JUMP, 1049 PADDR_A (dispatch), 1050 }/*-------------------------< RESEL_NO_TAG >---------------------*/,{ 1051 /* 1052 * Load the DSA with the unique ITL task. 1053 */ 1054 SCR_LOAD_REL (dsa, 4), 1055 offsetof(struct sym_lcb, head.itl_task_sa), 1056 /* 1057 * JUMP indirectly to the restart point of the CCB. 1058 */ 1059 SCR_LOAD_REL (temp, 4), 1060 offsetof(struct sym_ccb, phys.head.go.restart), 1061 SCR_RETURN, 1062 0, 1063 /* In normal situations we branch to RESEL_DSA */ 1064 }/*-------------------------< DATA_IN >--------------------------*/,{ 1065 /* 1066 * Because the size depends on the 1067 * #define SYM_CONF_MAX_SG parameter, 1068 * it is filled in at runtime. 1069 * 1070 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1071 * || SCR_CHMOV_TBL ^ SCR_DATA_IN, 1072 * || offsetof (struct sym_dsb, data[ i]), 1073 * ##========================================== 1074 */ 1075 0 1076 }/*-------------------------< DATA_IN2 >-------------------------*/,{ 1077 SCR_CALL, 1078 PADDR_A (datai_done), 1079 SCR_JUMP, 1080 PADDR_B (data_ovrun), 1081 }/*-------------------------< DATA_OUT >-------------------------*/,{ 1082 /* 1083 * Because the size depends on the 1084 * #define SYM_CONF_MAX_SG parameter, 1085 * it is filled in at runtime. 1086 * 1087 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1088 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1089 * || offsetof (struct sym_dsb, data[ i]), 1090 * ##========================================== 1091 */ 1092 0 1093 }/*-------------------------< DATA_OUT2 >------------------------*/,{ 1094 SCR_CALL, 1095 PADDR_A (datao_done), 1096 SCR_JUMP, 1097 PADDR_B (data_ovrun), 1098 }/*-------------------------< PM0_DATA >-------------------------*/,{ 1099 /* 1100 * Read our host flags to SFBR, so we will be able 1101 * to check against the data direction we expect. 1102 */ 1103 SCR_FROM_REG (HF_REG), 1104 0, 1105 /* 1106 * Check against actual DATA PHASE. 1107 */ 1108 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1109 PADDR_A (pm0_data_out), 1110 /* 1111 * Actual phase is DATA IN. 1112 * Check against expected direction. 1113 */ 1114 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1115 PADDR_B (data_ovrun), 1116 /* 1117 * Keep track we are moving data from the 1118 * PM0 DATA mini-script. 1119 */ 1120 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1121 0, 1122 /* 1123 * Move the data to memory. 1124 */ 1125 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1126 offsetof (struct sym_ccb, phys.pm0.sg), 1127 SCR_JUMP, 1128 PADDR_A (pm0_data_end), 1129 }/*-------------------------< PM0_DATA_OUT >---------------------*/,{ 1130 /* 1131 * Actual phase is DATA OUT. 1132 * Check against expected direction. 1133 */ 1134 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1135 PADDR_B (data_ovrun), 1136 /* 1137 * Keep track we are moving data from the 1138 * PM0 DATA mini-script. 1139 */ 1140 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1141 0, 1142 /* 1143 * Move the data from memory. 1144 */ 1145 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1146 offsetof (struct sym_ccb, phys.pm0.sg), 1147 }/*-------------------------< PM0_DATA_END >---------------------*/,{ 1148 /* 1149 * Clear the flag that told we were moving 1150 * data from the PM0 DATA mini-script. 1151 */ 1152 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)), 1153 0, 1154 /* 1155 * Return to the previous DATA script which 1156 * is guaranteed by design (if no bug) to be 1157 * the main DATA script for this transfer. 1158 */ 1159 SCR_LOAD_REL (temp, 4), 1160 offsetof (struct sym_ccb, phys.pm0.ret), 1161 SCR_RETURN, 1162 0, 1163 }/*-------------------------< PM1_DATA >-------------------------*/,{ 1164 /* 1165 * Read our host flags to SFBR, so we will be able 1166 * to check against the data direction we expect. 1167 */ 1168 SCR_FROM_REG (HF_REG), 1169 0, 1170 /* 1171 * Check against actual DATA PHASE. 1172 */ 1173 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1174 PADDR_A (pm1_data_out), 1175 /* 1176 * Actual phase is DATA IN. 1177 * Check against expected direction. 1178 */ 1179 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1180 PADDR_B (data_ovrun), 1181 /* 1182 * Keep track we are moving data from the 1183 * PM1 DATA mini-script. 1184 */ 1185 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1186 0, 1187 /* 1188 * Move the data to memory. 1189 */ 1190 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1191 offsetof (struct sym_ccb, phys.pm1.sg), 1192 SCR_JUMP, 1193 PADDR_A (pm1_data_end), 1194 }/*-------------------------< PM1_DATA_OUT >---------------------*/,{ 1195 /* 1196 * Actual phase is DATA OUT. 1197 * Check against expected direction. 1198 */ 1199 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1200 PADDR_B (data_ovrun), 1201 /* 1202 * Keep track we are moving data from the 1203 * PM1 DATA mini-script. 1204 */ 1205 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1206 0, 1207 /* 1208 * Move the data from memory. 1209 */ 1210 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1211 offsetof (struct sym_ccb, phys.pm1.sg), 1212 }/*-------------------------< PM1_DATA_END >---------------------*/,{ 1213 /* 1214 * Clear the flag that told we were moving 1215 * data from the PM1 DATA mini-script. 1216 */ 1217 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)), 1218 0, 1219 /* 1220 * Return to the previous DATA script which 1221 * is guaranteed by design (if no bug) to be 1222 * the main DATA script for this transfer. 1223 */ 1224 SCR_LOAD_REL (temp, 4), 1225 offsetof (struct sym_ccb, phys.pm1.ret), 1226 SCR_RETURN, 1227 0, 1228 }/*-------------------------<>-----------------------------------*/ 1229 }; 1230 1231 static struct SYM_FWB_SCR SYM_FWB_SCR = { 1232 /*--------------------------< START64 >--------------------------*/ { 1233 /* 1234 * SCRIPT entry point for the 895A, 896 and 1010. 1235 * For now, there is no specific stuff for those 1236 * chips at this point, but this may come. 1237 */ 1238 SCR_JUMP, 1239 PADDR_A (init), 1240 }/*-------------------------< NO_DATA >--------------------------*/,{ 1241 SCR_JUMP, 1242 PADDR_B (data_ovrun), 1243 }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{ 1244 /* 1245 * We are jumped here by the C code, if we have 1246 * some target to reset or some disconnected 1247 * job to abort. Since error recovery is a serious 1248 * busyness, we will really reset the SCSI BUS, if 1249 * case of a SCSI interrupt occuring in this path. 1250 */ 1251 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT 1252 /* 1253 * Set initiator mode. 1254 */ 1255 SCR_CLR (SCR_TRG), 1256 0, 1257 #endif 1258 /* 1259 * And try to select this target. 1260 */ 1261 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel), 1262 PADDR_A (reselect), 1263 /* 1264 * Wait for the selection to complete or 1265 * the selection to time out. 1266 */ 1267 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1268 -8, 1269 /* 1270 * Call the C code. 1271 */ 1272 SCR_INT, 1273 SIR_TARGET_SELECTED, 1274 /* 1275 * The C code should let us continue here. 1276 * Send the 'kiss of death' message. 1277 * We expect an immediate disconnect once 1278 * the target has eaten the message. 1279 */ 1280 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1281 0, 1282 SCR_MOVE_TBL ^ SCR_MSG_OUT, 1283 offsetof (struct sym_hcb, abrt_tbl), 1284 SCR_CLR (SCR_ACK|SCR_ATN), 1285 0, 1286 SCR_WAIT_DISC, 1287 0, 1288 /* 1289 * Tell the C code that we are done. 1290 */ 1291 SCR_INT, 1292 SIR_ABORT_SENT, 1293 }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{ 1294 /* 1295 * Jump at scheduler. 1296 */ 1297 SCR_JUMP, 1298 PADDR_A (start), 1299 }/*-------------------------< MSG_IN_ETC >-----------------------*/,{ 1300 /* 1301 * If it is an EXTENDED (variable size message) 1302 * Handle it. 1303 */ 1304 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)), 1305 PADDR_B (msg_extended), 1306 /* 1307 * Let the C code handle any other 1308 * 1 byte message. 1309 */ 1310 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)), 1311 PADDR_B (msg_received), 1312 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)), 1313 PADDR_B (msg_received), 1314 /* 1315 * We donnot handle 2 bytes messages from SCRIPTS. 1316 * So, let the C code deal with these ones too. 1317 */ 1318 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)), 1319 PADDR_B (msg_weird_seen), 1320 SCR_CLR (SCR_ACK), 1321 0, 1322 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1323 HADDR_1 (msgin[1]), 1324 }/*-------------------------< MSG_RECEIVED >---------------------*/,{ 1325 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */ 1326 0, 1327 SCR_INT, 1328 SIR_MSG_RECEIVED, 1329 }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{ 1330 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */ 1331 0, 1332 SCR_INT, 1333 SIR_MSG_WEIRD, 1334 }/*-------------------------< MSG_EXTENDED >---------------------*/,{ 1335 /* 1336 * Clear ACK and get the next byte 1337 * assumed to be the message length. 1338 */ 1339 SCR_CLR (SCR_ACK), 1340 0, 1341 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1342 HADDR_1 (msgin[1]), 1343 /* 1344 * Try to catch some unlikely situations as 0 length 1345 * or too large the length. 1346 */ 1347 SCR_JUMP ^ IFTRUE (DATA (0)), 1348 PADDR_B (msg_weird_seen), 1349 SCR_TO_REG (scratcha), 1350 0, 1351 SCR_REG_REG (sfbr, SCR_ADD, (256-8)), 1352 0, 1353 SCR_JUMP ^ IFTRUE (CARRYSET), 1354 PADDR_B (msg_weird_seen), 1355 /* 1356 * We donnot handle extended messages from SCRIPTS. 1357 * Read the amount of data correponding to the 1358 * message length and call the C code. 1359 */ 1360 SCR_STORE_REL (scratcha, 1), 1361 offsetof (struct sym_dsb, smsg_ext.size), 1362 SCR_CLR (SCR_ACK), 1363 0, 1364 SCR_MOVE_TBL ^ SCR_MSG_IN, 1365 offsetof (struct sym_dsb, smsg_ext), 1366 SCR_JUMP, 1367 PADDR_B (msg_received), 1368 }/*-------------------------< MSG_BAD >--------------------------*/,{ 1369 /* 1370 * unimplemented message - reject it. 1371 */ 1372 SCR_INT, 1373 SIR_REJECT_TO_SEND, 1374 SCR_SET (SCR_ATN), 1375 0, 1376 SCR_JUMP, 1377 PADDR_A (clrack), 1378 }/*-------------------------< MSG_WEIRD >------------------------*/,{ 1379 /* 1380 * weird message received 1381 * ignore all MSG IN phases and reject it. 1382 */ 1383 SCR_INT, 1384 SIR_REJECT_TO_SEND, 1385 SCR_SET (SCR_ATN), 1386 0, 1387 }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{ 1388 SCR_CLR (SCR_ACK), 1389 0, 1390 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 1391 PADDR_A (dispatch), 1392 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1393 HADDR_1 (scratch), 1394 SCR_JUMP, 1395 PADDR_B (msg_weird1), 1396 }/*-------------------------< WDTR_RESP >------------------------*/,{ 1397 /* 1398 * let the target fetch our answer. 1399 */ 1400 SCR_SET (SCR_ATN), 1401 0, 1402 SCR_CLR (SCR_ACK), 1403 0, 1404 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1405 PADDR_B (nego_bad_phase), 1406 }/*-------------------------< SEND_WDTR >------------------------*/,{ 1407 /* 1408 * Send the M_X_WIDE_REQ 1409 */ 1410 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT, 1411 HADDR_1 (msgout), 1412 SCR_JUMP, 1413 PADDR_B (msg_out_done), 1414 }/*-------------------------< SDTR_RESP >------------------------*/,{ 1415 /* 1416 * let the target fetch our answer. 1417 */ 1418 SCR_SET (SCR_ATN), 1419 0, 1420 SCR_CLR (SCR_ACK), 1421 0, 1422 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1423 PADDR_B (nego_bad_phase), 1424 }/*-------------------------< SEND_SDTR >------------------------*/,{ 1425 /* 1426 * Send the M_X_SYNC_REQ 1427 */ 1428 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT, 1429 HADDR_1 (msgout), 1430 SCR_JUMP, 1431 PADDR_B (msg_out_done), 1432 }/*-------------------------< PPR_RESP >-------------------------*/,{ 1433 /* 1434 * let the target fetch our answer. 1435 */ 1436 SCR_SET (SCR_ATN), 1437 0, 1438 SCR_CLR (SCR_ACK), 1439 0, 1440 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1441 PADDR_B (nego_bad_phase), 1442 }/*-------------------------< SEND_PPR >-------------------------*/,{ 1443 /* 1444 * Send the M_X_PPR_REQ 1445 */ 1446 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT, 1447 HADDR_1 (msgout), 1448 SCR_JUMP, 1449 PADDR_B (msg_out_done), 1450 }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{ 1451 SCR_INT, 1452 SIR_NEGO_PROTO, 1453 SCR_JUMP, 1454 PADDR_A (dispatch), 1455 }/*-------------------------< MSG_OUT >--------------------------*/,{ 1456 /* 1457 * The target requests a message. 1458 * We donnot send messages that may 1459 * require the device to go to bus free. 1460 */ 1461 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1462 HADDR_1 (msgout), 1463 /* 1464 * ... wait for the next phase 1465 * if it's a message out, send it again, ... 1466 */ 1467 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 1468 PADDR_B (msg_out), 1469 }/*-------------------------< MSG_OUT_DONE >---------------------*/,{ 1470 /* 1471 * Let the C code be aware of the 1472 * sent message and clear the message. 1473 */ 1474 SCR_INT, 1475 SIR_MSG_OUT_DONE, 1476 /* 1477 * ... and process the next phase 1478 */ 1479 SCR_JUMP, 1480 PADDR_A (dispatch), 1481 }/*-------------------------< DATA_OVRUN >-----------------------*/,{ 1482 /* 1483 * Use scratcha to count the extra bytes. 1484 */ 1485 SCR_LOAD_ABS (scratcha, 4), 1486 PADDR_B (zero), 1487 }/*-------------------------< DATA_OVRUN1 >----------------------*/,{ 1488 /* 1489 * The target may want to transfer too much data. 1490 * 1491 * If phase is DATA OUT write 1 byte and count it. 1492 */ 1493 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)), 1494 16, 1495 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT, 1496 HADDR_1 (scratch), 1497 SCR_JUMP, 1498 PADDR_B (data_ovrun2), 1499 /* 1500 * If WSR is set, clear this condition, and 1501 * count this byte. 1502 */ 1503 SCR_FROM_REG (scntl2), 1504 0, 1505 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), 1506 16, 1507 SCR_REG_REG (scntl2, SCR_OR, WSR), 1508 0, 1509 SCR_JUMP, 1510 PADDR_B (data_ovrun2), 1511 /* 1512 * Finally check against DATA IN phase. 1513 * Signal data overrun to the C code 1514 * and jump to dispatcher if not so. 1515 * Read 1 byte otherwise and count it. 1516 */ 1517 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)), 1518 16, 1519 SCR_INT, 1520 SIR_DATA_OVERRUN, 1521 SCR_JUMP, 1522 PADDR_A (dispatch), 1523 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN, 1524 HADDR_1 (scratch), 1525 }/*-------------------------< DATA_OVRUN2 >----------------------*/,{ 1526 /* 1527 * Count this byte. 1528 * This will allow to return a negative 1529 * residual to user. 1530 */ 1531 SCR_REG_REG (scratcha, SCR_ADD, 0x01), 1532 0, 1533 SCR_REG_REG (scratcha1, SCR_ADDC, 0), 1534 0, 1535 SCR_REG_REG (scratcha2, SCR_ADDC, 0), 1536 0, 1537 /* 1538 * .. and repeat as required. 1539 */ 1540 SCR_JUMP, 1541 PADDR_B (data_ovrun1), 1542 }/*-------------------------< ABORT_RESEL >----------------------*/,{ 1543 SCR_SET (SCR_ATN), 1544 0, 1545 SCR_CLR (SCR_ACK), 1546 0, 1547 /* 1548 * send the abort/abortag/reset message 1549 * we expect an immediate disconnect 1550 */ 1551 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1552 0, 1553 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1554 HADDR_1 (msgout), 1555 SCR_CLR (SCR_ACK|SCR_ATN), 1556 0, 1557 SCR_WAIT_DISC, 1558 0, 1559 SCR_INT, 1560 SIR_RESEL_ABORTED, 1561 SCR_JUMP, 1562 PADDR_A (start), 1563 }/*-------------------------< RESEND_IDENT >---------------------*/,{ 1564 /* 1565 * The target stays in MSG OUT phase after having acked 1566 * Identify [+ Tag [+ Extended message ]]. Targets shall 1567 * behave this way on parity error. 1568 * We must send it again all the messages. 1569 */ 1570 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */ 1571 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */ 1572 SCR_JUMP, 1573 PADDR_A (send_ident), 1574 }/*-------------------------< IDENT_BREAK >----------------------*/,{ 1575 SCR_CLR (SCR_ATN), 1576 0, 1577 SCR_JUMP, 1578 PADDR_A (select2), 1579 }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{ 1580 SCR_SET (SCR_ATN), 1581 0, 1582 SCR_JUMP, 1583 PADDR_A (select2), 1584 }/*-------------------------< SDATA_IN >-------------------------*/,{ 1585 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1586 offsetof (struct sym_dsb, sense), 1587 SCR_CALL, 1588 PADDR_A (datai_done), 1589 SCR_JUMP, 1590 PADDR_B (data_ovrun), 1591 }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{ 1592 /* 1593 * Message is an IDENTIFY, but lun is unknown. 1594 * Signal problem to C code for logging the event. 1595 * Send a M_ABORT to clear all pending tasks. 1596 */ 1597 SCR_INT, 1598 SIR_RESEL_BAD_LUN, 1599 SCR_JUMP, 1600 PADDR_B (abort_resel), 1601 }/*-------------------------< BAD_I_T_L >------------------------*/,{ 1602 /* 1603 * We donnot have a task for that I_T_L. 1604 * Signal problem to C code for logging the event. 1605 * Send a M_ABORT message. 1606 */ 1607 SCR_INT, 1608 SIR_RESEL_BAD_I_T_L, 1609 SCR_JUMP, 1610 PADDR_B (abort_resel), 1611 }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{ 1612 /* 1613 * We donnot have a task that matches the tag. 1614 * Signal problem to C code for logging the event. 1615 * Send a M_ABORTTAG message. 1616 */ 1617 SCR_INT, 1618 SIR_RESEL_BAD_I_T_L_Q, 1619 SCR_JUMP, 1620 PADDR_B (abort_resel), 1621 }/*-------------------------< BAD_STATUS >-----------------------*/,{ 1622 /* 1623 * Anything different from INTERMEDIATE 1624 * CONDITION MET should be a bad SCSI status, 1625 * given that GOOD status has already been tested. 1626 * Call the C code. 1627 */ 1628 SCR_LOAD_ABS (scratcha, 4), 1629 PADDR_B (startpos), 1630 SCR_INT ^ IFFALSE (DATA (S_COND_MET)), 1631 SIR_BAD_SCSI_STATUS, 1632 SCR_RETURN, 1633 0, 1634 }/*-------------------------< PM_HANDLE >------------------------*/,{ 1635 /* 1636 * Phase mismatch handling. 1637 * 1638 * Since we have to deal with 2 SCSI data pointers 1639 * (current and saved), we need at least 2 contexts. 1640 * Each context (pm0 and pm1) has a saved area, a 1641 * SAVE mini-script and a DATA phase mini-script. 1642 */ 1643 /* 1644 * Get the PM handling flags. 1645 */ 1646 SCR_FROM_REG (HF_REG), 1647 0, 1648 /* 1649 * If no flags (1rst PM for example), avoid 1650 * all the below heavy flags testing. 1651 * This makes the normal case a bit faster. 1652 */ 1653 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED))), 1654 PADDR_B (pm_handle1), 1655 /* 1656 * If we received a SAVE DP, switch to the 1657 * other PM context since the savep may point 1658 * to the current PM context. 1659 */ 1660 SCR_JUMPR ^ IFFALSE (MASK (HF_DP_SAVED, HF_DP_SAVED)), 1661 8, 1662 SCR_REG_REG (sfbr, SCR_XOR, HF_ACT_PM), 1663 0, 1664 /* 1665 * If we have been interrupt in a PM DATA mini-script, 1666 * we take the return address from the corresponding 1667 * saved area. 1668 * This ensure the return address always points to the 1669 * main DATA script for this transfer. 1670 */ 1671 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1))), 1672 PADDR_B (pm_handle1), 1673 SCR_JUMPR ^ IFFALSE (MASK (HF_IN_PM0, HF_IN_PM0)), 1674 16, 1675 SCR_LOAD_REL (ia, 4), 1676 offsetof(struct sym_ccb, phys.pm0.ret), 1677 SCR_JUMP, 1678 PADDR_B (pm_save), 1679 SCR_LOAD_REL (ia, 4), 1680 offsetof(struct sym_ccb, phys.pm1.ret), 1681 SCR_JUMP, 1682 PADDR_B (pm_save), 1683 }/*-------------------------< PM_HANDLE1 >-----------------------*/,{ 1684 /* 1685 * Normal case. 1686 * Update the return address so that it 1687 * will point after the interrupted MOVE. 1688 */ 1689 SCR_REG_REG (ia, SCR_ADD, 8), 1690 0, 1691 SCR_REG_REG (ia1, SCR_ADDC, 0), 1692 0, 1693 }/*-------------------------< PM_SAVE >--------------------------*/,{ 1694 /* 1695 * Clear all the flags that told us if we were 1696 * interrupted in a PM DATA mini-script and/or 1697 * we received a SAVE DP. 1698 */ 1699 SCR_SFBR_REG (HF_REG, SCR_AND, (~(HF_IN_PM0|HF_IN_PM1|HF_DP_SAVED))), 1700 0, 1701 /* 1702 * Choose the current PM context. 1703 */ 1704 SCR_JUMP ^ IFTRUE (MASK (HF_ACT_PM, HF_ACT_PM)), 1705 PADDR_B (pm1_save), 1706 }/*-------------------------< PM0_SAVE >-------------------------*/,{ 1707 SCR_STORE_REL (ia, 4), 1708 offsetof(struct sym_ccb, phys.pm0.ret), 1709 /* 1710 * If WSR bit is set, either UA and RBC may 1711 * have to be changed whether the device wants 1712 * to ignore this residue or not. 1713 */ 1714 SCR_FROM_REG (scntl2), 1715 0, 1716 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)), 1717 PADDR_B (pm_wsr_handle), 1718 /* 1719 * Save the remaining byte count, the updated 1720 * address and the return address. 1721 */ 1722 SCR_STORE_REL (rbc, 4), 1723 offsetof(struct sym_ccb, phys.pm0.sg.size), 1724 SCR_STORE_REL (ua, 4), 1725 offsetof(struct sym_ccb, phys.pm0.sg.addr), 1726 /* 1727 * Set the current pointer at the PM0 DATA mini-script. 1728 */ 1729 SCR_LOAD_ABS (ia, 4), 1730 PADDR_B (pm0_data_addr), 1731 }/*-------------------------< PM_SAVE_END >----------------------*/,{ 1732 SCR_STORE_REL (ia, 4), 1733 offsetof(struct sym_ccb, phys.head.lastp), 1734 SCR_JUMP, 1735 PADDR_A (dispatch), 1736 }/*-------------------------< PM1_SAVE >-------------------------*/,{ 1737 SCR_STORE_REL (ia, 4), 1738 offsetof(struct sym_ccb, phys.pm1.ret), 1739 /* 1740 * If WSR bit is set, either UA and RBC may 1741 * have to be changed whether the device wants 1742 * to ignore this residue or not. 1743 */ 1744 SCR_FROM_REG (scntl2), 1745 0, 1746 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)), 1747 PADDR_B (pm_wsr_handle), 1748 /* 1749 * Save the remaining byte count, the updated 1750 * address and the return address. 1751 */ 1752 SCR_STORE_REL (rbc, 4), 1753 offsetof(struct sym_ccb, phys.pm1.sg.size), 1754 SCR_STORE_REL (ua, 4), 1755 offsetof(struct sym_ccb, phys.pm1.sg.addr), 1756 /* 1757 * Set the current pointer at the PM1 DATA mini-script. 1758 */ 1759 SCR_LOAD_ABS (ia, 4), 1760 PADDR_B (pm1_data_addr), 1761 SCR_JUMP, 1762 PADDR_B (pm_save_end), 1763 }/*-------------------------< PM_WSR_HANDLE >--------------------*/,{ 1764 /* 1765 * Phase mismatch handling from SCRIPT with WSR set. 1766 * Such a condition can occur if the chip wants to 1767 * execute a CHMOV(size > 1) when the WSR bit is 1768 * set and the target changes PHASE. 1769 * 1770 * We must move the residual byte to memory. 1771 * 1772 * UA contains bit 0..31 of the address to 1773 * move the residual byte. 1774 * Move it to the table indirect. 1775 */ 1776 SCR_STORE_REL (ua, 4), 1777 offsetof (struct sym_ccb, phys.wresid.addr), 1778 /* 1779 * Increment UA (move address to next position). 1780 */ 1781 SCR_REG_REG (ua, SCR_ADD, 1), 1782 0, 1783 SCR_REG_REG (ua1, SCR_ADDC, 0), 1784 0, 1785 SCR_REG_REG (ua2, SCR_ADDC, 0), 1786 0, 1787 SCR_REG_REG (ua3, SCR_ADDC, 0), 1788 0, 1789 /* 1790 * Compute SCRATCHA as: 1791 * - size to transfer = 1 byte. 1792 * - bit 24..31 = high address bit [32...39]. 1793 */ 1794 SCR_LOAD_ABS (scratcha, 4), 1795 PADDR_B (zero), 1796 SCR_REG_REG (scratcha, SCR_OR, 1), 1797 0, 1798 SCR_FROM_REG (rbc3), 1799 0, 1800 SCR_TO_REG (scratcha3), 1801 0, 1802 /* 1803 * Move this value to the table indirect. 1804 */ 1805 SCR_STORE_REL (scratcha, 4), 1806 offsetof (struct sym_ccb, phys.wresid.size), 1807 /* 1808 * Wait for a valid phase. 1809 * While testing with bogus QUANTUM drives, the C1010 1810 * sometimes raised a spurious phase mismatch with 1811 * WSR and the CHMOV(1) triggered another PM. 1812 * Waiting explicitely for the PHASE seemed to avoid 1813 * the nested phase mismatch. Btw, this didn't happen 1814 * using my IBM drives. 1815 */ 1816 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_IN)), 1817 0, 1818 /* 1819 * Perform the move of the residual byte. 1820 */ 1821 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1822 offsetof (struct sym_ccb, phys.wresid), 1823 /* 1824 * We can now handle the phase mismatch with UA fixed. 1825 * RBC[0..23]=0 is a special case that does not require 1826 * a PM context. The C code also checks against this. 1827 */ 1828 SCR_FROM_REG (rbc), 1829 0, 1830 SCR_RETURN ^ IFFALSE (DATA (0)), 1831 0, 1832 SCR_FROM_REG (rbc1), 1833 0, 1834 SCR_RETURN ^ IFFALSE (DATA (0)), 1835 0, 1836 SCR_FROM_REG (rbc2), 1837 0, 1838 SCR_RETURN ^ IFFALSE (DATA (0)), 1839 0, 1840 /* 1841 * RBC[0..23]=0. 1842 * Not only we donnot need a PM context, but this would 1843 * lead to a bogus CHMOV(0). This condition means that 1844 * the residual was the last byte to move from this CHMOV. 1845 * So, we just have to move the current data script pointer 1846 * (i.e. TEMP) to the SCRIPTS address following the 1847 * interrupted CHMOV and jump to dispatcher. 1848 * IA contains the data pointer to save. 1849 */ 1850 SCR_JUMP, 1851 PADDR_B (pm_save_end), 1852 }/*-------------------------< WSR_MA_HELPER >--------------------*/,{ 1853 /* 1854 * Helper for the C code when WSR bit is set. 1855 * Perform the move of the residual byte. 1856 */ 1857 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1858 offsetof (struct sym_ccb, phys.wresid), 1859 SCR_JUMP, 1860 PADDR_A (dispatch), 1861 1862 #ifdef SYM_OPT_HANDLE_DIR_UNKNOWN 1863 }/*-------------------------< DATA_IO >--------------------------*/,{ 1864 /* 1865 * We jump here if the data direction was unknown at the 1866 * time we had to queue the command to the scripts processor. 1867 * Pointers had been set as follow in this situation: 1868 * savep --> DATA_IO 1869 * lastp --> start pointer when DATA_IN 1870 * wlastp --> start pointer when DATA_OUT 1871 * This script sets savep and lastp according to the 1872 * direction chosen by the target. 1873 */ 1874 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)), 1875 PADDR_B (data_io_out), 1876 }/*-------------------------< DATA_IO_IN >-----------------------*/,{ 1877 /* 1878 * Direction is DATA IN. 1879 */ 1880 SCR_LOAD_REL (scratcha, 4), 1881 offsetof (struct sym_ccb, phys.head.lastp), 1882 }/*-------------------------< DATA_IO_COM >----------------------*/,{ 1883 SCR_STORE_REL (scratcha, 4), 1884 offsetof (struct sym_ccb, phys.head.savep), 1885 1886 /* 1887 * Jump to the SCRIPTS according to actual direction. 1888 */ 1889 SCR_LOAD_REL (temp, 4), 1890 offsetof (struct sym_ccb, phys.head.savep), 1891 SCR_RETURN, 1892 0, 1893 }/*-------------------------< DATA_IO_OUT >----------------------*/,{ 1894 /* 1895 * Direction is DATA OUT. 1896 */ 1897 SCR_REG_REG (HF_REG, SCR_AND, (~HF_DATA_IN)), 1898 0, 1899 SCR_LOAD_REL (scratcha, 4), 1900 offsetof (struct sym_ccb, phys.head.wlastp), 1901 SCR_STORE_REL (scratcha, 4), 1902 offsetof (struct sym_ccb, phys.head.lastp), 1903 SCR_JUMP, 1904 PADDR_B(data_io_com), 1905 #endif /* SYM_OPT_HANDLE_DIR_UNKNOWN */ 1906 1907 }/*-------------------------< ZERO >-----------------------------*/,{ 1908 SCR_DATA_ZERO, 1909 }/*-------------------------< SCRATCH >--------------------------*/,{ 1910 SCR_DATA_ZERO, 1911 }/*-------------------------< PM0_DATA_ADDR >--------------------*/,{ 1912 SCR_DATA_ZERO, 1913 }/*-------------------------< PM1_DATA_ADDR >--------------------*/,{ 1914 SCR_DATA_ZERO, 1915 }/*-------------------------< DONE_POS >-------------------------*/,{ 1916 SCR_DATA_ZERO, 1917 }/*-------------------------< STARTPOS >-------------------------*/,{ 1918 SCR_DATA_ZERO, 1919 }/*-------------------------< TARGTBL >--------------------------*/,{ 1920 SCR_DATA_ZERO, 1921 }/*-------------------------<>-----------------------------------*/ 1922 }; 1923 1924 static struct SYM_FWZ_SCR SYM_FWZ_SCR = { 1925 /*-------------------------< SNOOPTEST >------------------------*/{ 1926 /* 1927 * Read the variable from memory. 1928 */ 1929 SCR_LOAD_REL (scratcha, 4), 1930 offsetof(struct sym_hcb, scratch), 1931 /* 1932 * Write the variable to memory. 1933 */ 1934 SCR_STORE_REL (temp, 4), 1935 offsetof(struct sym_hcb, scratch), 1936 /* 1937 * Read back the variable from memory. 1938 */ 1939 SCR_LOAD_REL (temp, 4), 1940 offsetof(struct sym_hcb, scratch), 1941 }/*-------------------------< SNOOPEND >-------------------------*/,{ 1942 /* 1943 * And stop. 1944 */ 1945 SCR_INT, 1946 99, 1947 #ifdef SYM_OPT_NO_BUS_MEMORY_MAPPING 1948 /* 1949 * We may use MEMORY MOVE instructions to load the on chip-RAM, 1950 * if it happens that mapping PCI memory is not possible. 1951 * But writing the RAM from the CPU is the preferred method, 1952 * since PCI 2.2 seems to disallow PCI self-mastering. 1953 */ 1954 }/*-------------------------< START_RAM >------------------------*/,{ 1955 /* 1956 * Load the script into on-chip RAM, 1957 * and jump to start point. 1958 */ 1959 SCR_COPY (sizeof(struct SYM_FWA_SCR)), 1960 }/*-------------------------< SCRIPTA0_BA >----------------------*/,{ 1961 0, 1962 PADDR_A (start), 1963 SCR_JUMP, 1964 PADDR_A (init), 1965 }/*-------------------------< START_RAM64 >----------------------*/,{ 1966 /* 1967 * Load the RAM and start for 64 bit PCI (895A,896). 1968 * Both scripts (script and scripth) are loaded into 1969 * the RAM which is 8K (4K for 825A/875/895). 1970 * We also need to load some 32-63 bit segments 1971 * address of the SCRIPTS processor. 1972 * LOAD/STORE ABSOLUTE always refers to on-chip RAM 1973 * in our implementation. The main memory is 1974 * accessed using LOAD/STORE DSA RELATIVE. 1975 */ 1976 SCR_LOAD_REL (mmws, 4), 1977 offsetof (struct sym_hcb, scr_ram_seg), 1978 SCR_COPY (sizeof(struct SYM_FWA_SCR)), 1979 }/*-------------------------< SCRIPTA0_BA64 >--------------------*/,{ 1980 0, 1981 PADDR_A (start), 1982 SCR_COPY (sizeof(struct SYM_FWB_SCR)), 1983 }/*-------------------------< SCRIPTB0_BA64 >--------------------*/,{ 1984 0, 1985 PADDR_B (start64), 1986 SCR_LOAD_REL (mmrs, 4), 1987 offsetof (struct sym_hcb, scr_ram_seg), 1988 SCR_JUMP64, 1989 PADDR_B (start64), 1990 }/*-------------------------< RAM_SEG64 >------------------------*/,{ 1991 0, 1992 #endif /* SYM_OPT_NO_BUS_MEMORY_MAPPING */ 1993 }/*-------------------------<>-----------------------------------*/ 1994 }; 1995