1 /* 2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family 3 * of PCI-SCSI IO processors. 4 * 5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 6 * 7 * This driver is derived from the Linux sym53c8xx driver. 8 * Copyright (C) 1998-2000 Gerard Roudier 9 * 10 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 11 * a port of the FreeBSD ncr driver to Linux-1.2.13. 12 * 13 * The original ncr driver has been written for 386bsd and FreeBSD by 14 * Wolfgang Stanglmeier <wolf@cologne.de> 15 * Stefan Esser <se@mi.Uni-Koeln.de> 16 * Copyright (C) 1994 Wolfgang Stanglmeier 17 * 18 * Other major contributions: 19 * 20 * NVRAM detection and reading. 21 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 22 * 23 *----------------------------------------------------------------------------- 24 * 25 * Redistribution and use in source and binary forms, with or without 26 * modification, are permitted provided that the following conditions 27 * are met: 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. The name of the author may not be used to endorse or promote products 31 * derived from this software without specific prior written permission. 32 * 33 * Where this Software is combined with software released under the terms of 34 * the GNU Public License ("GPL") and the terms of the GPL would require the 35 * combined work to also be released under the terms of the GPL, the terms 36 * and conditions of this License will apply in addition to those of the 37 * GPL with the exception of any terms or conditions of this License that 38 * conflict with, or are expressly prohibited by, the GPL. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 44 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 53 /* 54 * Scripts for SYMBIOS-Processor 55 * 56 * We have to know the offsets of all labels before we reach 57 * them (for forward jumps). Therefore we declare a struct 58 * here. If you make changes inside the script, 59 * 60 * DONT FORGET TO CHANGE THE LENGTHS HERE! 61 */ 62 63 /* 64 * Script fragments which are loaded into the on-chip RAM 65 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips. 66 * Must not exceed 4K bytes. 67 */ 68 struct SYM_FWA_SCR { 69 u32 start [ 11]; 70 u32 getjob_begin [ 4]; 71 u32 _sms_a10 [ 5]; 72 u32 getjob_end [ 4]; 73 u32 _sms_a20 [ 4]; 74 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT 75 u32 select [ 8]; 76 #else 77 u32 select [ 6]; 78 #endif 79 u32 _sms_a30 [ 5]; 80 u32 wf_sel_done [ 2]; 81 u32 send_ident [ 2]; 82 #ifdef SYM_CONF_IARB_SUPPORT 83 u32 select2 [ 8]; 84 #else 85 u32 select2 [ 2]; 86 #endif 87 u32 command [ 2]; 88 u32 dispatch [ 28]; 89 u32 sel_no_cmd [ 10]; 90 u32 init [ 6]; 91 u32 clrack [ 4]; 92 u32 datai_done [ 11]; 93 u32 datai_done_wsr [ 20]; 94 u32 datao_done [ 11]; 95 u32 datao_done_wss [ 6]; 96 u32 datai_phase [ 5]; 97 u32 datao_phase [ 5]; 98 u32 msg_in [ 2]; 99 u32 msg_in2 [ 10]; 100 #ifdef SYM_CONF_IARB_SUPPORT 101 u32 status [ 14]; 102 #else 103 u32 status [ 10]; 104 #endif 105 u32 complete [ 6]; 106 u32 complete2 [ 8]; 107 u32 _sms_a40 [ 12]; 108 u32 done [ 5]; 109 u32 _sms_a50 [ 5]; 110 u32 _sms_a60 [ 2]; 111 u32 done_end [ 4]; 112 u32 complete_error [ 5]; 113 u32 save_dp [ 11]; 114 u32 restore_dp [ 7]; 115 u32 disconnect [ 11]; 116 u32 disconnect2 [ 5]; 117 u32 _sms_a65 [ 3]; 118 #ifdef SYM_CONF_IARB_SUPPORT 119 u32 idle [ 4]; 120 #else 121 u32 idle [ 2]; 122 #endif 123 #ifdef SYM_CONF_IARB_SUPPORT 124 u32 ungetjob [ 7]; 125 #else 126 u32 ungetjob [ 5]; 127 #endif 128 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT 129 u32 reselect [ 4]; 130 #else 131 u32 reselect [ 2]; 132 #endif 133 u32 reselected [ 19]; 134 u32 _sms_a70 [ 6]; 135 u32 _sms_a80 [ 4]; 136 u32 reselected1 [ 25]; 137 u32 _sms_a90 [ 4]; 138 u32 resel_lun0 [ 7]; 139 u32 _sms_a100 [ 4]; 140 u32 resel_tag [ 8]; 141 #if SYM_CONF_MAX_TASK*4 > 512 142 u32 _sms_a110 [ 23]; 143 #elif SYM_CONF_MAX_TASK*4 > 256 144 u32 _sms_a110 [ 17]; 145 #else 146 u32 _sms_a110 [ 13]; 147 #endif 148 u32 _sms_a120 [ 2]; 149 u32 resel_go [ 4]; 150 u32 _sms_a130 [ 7]; 151 u32 resel_dsa [ 2]; 152 u32 resel_dsa1 [ 4]; 153 u32 _sms_a140 [ 7]; 154 u32 resel_no_tag [ 4]; 155 u32 _sms_a145 [ 7]; 156 u32 data_in [SYM_CONF_MAX_SG * 2]; 157 u32 data_in2 [ 4]; 158 u32 data_out [SYM_CONF_MAX_SG * 2]; 159 u32 data_out2 [ 4]; 160 u32 pm0_data [ 12]; 161 u32 pm0_data_out [ 6]; 162 u32 pm0_data_end [ 7]; 163 u32 pm_data_end [ 4]; 164 u32 _sms_a150 [ 4]; 165 u32 pm1_data [ 12]; 166 u32 pm1_data_out [ 6]; 167 u32 pm1_data_end [ 9]; 168 }; 169 170 /* 171 * Script fragments which stay in main memory for all chips 172 * except for chips that support 8K on-chip RAM. 173 */ 174 struct SYM_FWB_SCR { 175 u32 no_data [ 2]; 176 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT 177 u32 sel_for_abort [ 18]; 178 #else 179 u32 sel_for_abort [ 16]; 180 #endif 181 u32 sel_for_abort_1 [ 2]; 182 u32 msg_in_etc [ 12]; 183 u32 msg_received [ 5]; 184 u32 msg_weird_seen [ 5]; 185 u32 msg_extended [ 17]; 186 u32 _sms_b10 [ 4]; 187 u32 msg_bad [ 6]; 188 u32 msg_weird [ 4]; 189 u32 msg_weird1 [ 8]; 190 u32 wdtr_resp [ 6]; 191 u32 send_wdtr [ 4]; 192 u32 sdtr_resp [ 6]; 193 u32 send_sdtr [ 4]; 194 u32 ppr_resp [ 6]; 195 u32 send_ppr [ 4]; 196 u32 nego_bad_phase [ 4]; 197 u32 msg_out [ 4]; 198 u32 msg_out_done [ 4]; 199 u32 data_ovrun [ 3]; 200 u32 data_ovrun1 [ 22]; 201 u32 data_ovrun2 [ 8]; 202 u32 abort_resel [ 16]; 203 u32 resend_ident [ 4]; 204 u32 ident_break [ 4]; 205 u32 ident_break_atn [ 4]; 206 u32 sdata_in [ 6]; 207 u32 resel_bad_lun [ 4]; 208 u32 bad_i_t_l [ 4]; 209 u32 bad_i_t_l_q [ 4]; 210 u32 bad_status [ 7]; 211 u32 wsr_ma_helper [ 4]; 212 213 #ifdef SYM_OPT_HANDLE_DIR_UNKNOWN 214 /* Unknown direction handling */ 215 u32 data_io [ 2]; 216 u32 data_io_com [ 8]; 217 u32 data_io_out [ 7]; 218 #endif 219 /* Data area */ 220 u32 zero [ 1]; 221 u32 scratch [ 1]; 222 u32 scratch1 [ 1]; 223 u32 prev_done [ 1]; 224 u32 done_pos [ 1]; 225 u32 nextjob [ 1]; 226 u32 startpos [ 1]; 227 u32 targtbl [ 1]; 228 }; 229 230 /* 231 * Script fragments used at initialisations. 232 * Only runs out of main memory. 233 */ 234 struct SYM_FWZ_SCR { 235 u32 snooptest [ 9]; 236 u32 snoopend [ 2]; 237 #ifdef SYM_OPT_NO_BUS_MEMORY_MAPPING 238 u32 start_ram [ 1]; 239 u32 scripta0_ba [ 4]; 240 #endif 241 }; 242 243 static struct SYM_FWA_SCR SYM_FWA_SCR = { 244 /*--------------------------< START >----------------------------*/ { 245 /* 246 * Switch the LED on. 247 * Will be patched with a NO_OP if LED 248 * not needed or not desired. 249 */ 250 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 251 0, 252 /* 253 * Clear SIGP. 254 */ 255 SCR_FROM_REG (ctest2), 256 0, 257 /* 258 * Stop here if the C code wants to perform 259 * some error recovery procedure manually. 260 * (Indicate this by setting SEM in ISTAT) 261 */ 262 SCR_FROM_REG (istat), 263 0, 264 /* 265 * Report to the C code the next position in 266 * the start queue the SCRIPTS will schedule. 267 * The C code must not change SCRATCHA. 268 */ 269 SCR_COPY (4), 270 PADDR_B (startpos), 271 RADDR_1 (scratcha), 272 SCR_INT ^ IFTRUE (MASK (SEM, SEM)), 273 SIR_SCRIPT_STOPPED, 274 /* 275 * Start the next job. 276 * 277 * @DSA = start point for this job. 278 * SCRATCHA = address of this job in the start queue. 279 * 280 * We will restore startpos with SCRATCHA if we fails the 281 * arbitration or if it is the idle job. 282 * 283 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS 284 * is a critical path. If it is partially executed, it then 285 * may happen that the job address is not yet in the DSA 286 * and the next queue position points to the next JOB. 287 */ 288 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{ 289 /* 290 * Copy to a fixed location both the next STARTPOS 291 * and the current JOB address, using self modifying 292 * SCRIPTS. 293 */ 294 SCR_COPY (4), 295 RADDR_1 (scratcha), 296 PADDR_A (_sms_a10), 297 SCR_COPY (8), 298 }/*-------------------------< _SMS_A10 >-------------------------*/,{ 299 0, 300 PADDR_B (nextjob), 301 /* 302 * Move the start address to TEMP using self- 303 * modifying SCRIPTS and jump indirectly to 304 * that address. 305 */ 306 SCR_COPY (4), 307 PADDR_B (nextjob), 308 RADDR_1 (dsa), 309 }/*-------------------------< GETJOB_END >-----------------------*/,{ 310 SCR_COPY (4), 311 RADDR_1 (dsa), 312 PADDR_A (_sms_a20), 313 SCR_COPY (4), 314 }/*-------------------------< _SMS_A20 >-------------------------*/,{ 315 0, 316 RADDR_1 (temp), 317 SCR_RETURN, 318 0, 319 }/*-------------------------< SELECT >---------------------------*/,{ 320 /* 321 * DSA contains the address of a scheduled 322 * data structure. 323 * 324 * SCRATCHA contains the address of the start queue 325 * entry which points to the next job. 326 * 327 * Set Initiator mode. 328 * 329 * (Target mode is left as an exercise for the reader) 330 */ 331 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT 332 SCR_CLR (SCR_TRG), 333 0, 334 #endif 335 /* 336 * And try to select this target. 337 */ 338 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select), 339 PADDR_A (ungetjob), 340 /* 341 * Now there are 4 possibilities: 342 * 343 * (1) The chip looses arbitration. 344 * This is ok, because it will try again, 345 * when the bus becomes idle. 346 * (But beware of the timeout function!) 347 * 348 * (2) The chip is reselected. 349 * Then the script processor takes the jump 350 * to the RESELECT label. 351 * 352 * (3) The chip wins arbitration. 353 * Then it will execute SCRIPTS instruction until 354 * the next instruction that checks SCSI phase. 355 * Then will stop and wait for selection to be 356 * complete or selection time-out to occur. 357 * 358 * After having won arbitration, the SCRIPTS 359 * processor is able to execute instructions while 360 * the SCSI core is performing SCSI selection. 361 */ 362 363 /* 364 * Copy the CCB header to a fixed location 365 * in the HCB using self-modifying SCRIPTS. 366 */ 367 SCR_COPY (4), 368 RADDR_1 (dsa), 369 PADDR_A (_sms_a30), 370 SCR_COPY (sizeof(struct sym_ccbh)), 371 }/*-------------------------< _SMS_A30 >-------------------------*/,{ 372 0, 373 HADDR_1 (ccb_head), 374 /* 375 * Initialize the status register 376 */ 377 SCR_COPY (4), 378 HADDR_1 (ccb_head.status), 379 RADDR_1 (scr0), 380 }/*-------------------------< WF_SEL_DONE >----------------------*/,{ 381 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), 382 SIR_SEL_ATN_NO_MSG_OUT, 383 }/*-------------------------< SEND_IDENT >-----------------------*/,{ 384 /* 385 * Selection complete. 386 * Send the IDENTIFY and possibly the TAG message 387 * and negotiation message if present. 388 */ 389 SCR_MOVE_TBL ^ SCR_MSG_OUT, 390 offsetof (struct sym_dsb, smsg), 391 }/*-------------------------< SELECT2 >--------------------------*/,{ 392 #ifdef SYM_CONF_IARB_SUPPORT 393 /* 394 * Set IMMEDIATE ARBITRATION if we have been given 395 * a hint to do so. (Some job to do after this one). 396 */ 397 SCR_FROM_REG (HF_REG), 398 0, 399 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), 400 8, 401 SCR_REG_REG (scntl1, SCR_OR, IARB), 402 0, 403 #endif 404 /* 405 * Anticipate the COMMAND phase. 406 * This is the PHASE we expect at this point. 407 */ 408 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)), 409 PADDR_A (sel_no_cmd), 410 }/*-------------------------< COMMAND >--------------------------*/,{ 411 /* 412 * ... and send the command 413 */ 414 SCR_MOVE_TBL ^ SCR_COMMAND, 415 offsetof (struct sym_dsb, cmd), 416 }/*-------------------------< DISPATCH >-------------------------*/,{ 417 /* 418 * MSG_IN is the only phase that shall be 419 * entered at least once for each (re)selection. 420 * So we test it first. 421 */ 422 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 423 PADDR_A (msg_in), 424 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)), 425 PADDR_A (datao_phase), 426 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)), 427 PADDR_A (datai_phase), 428 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)), 429 PADDR_A (status), 430 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)), 431 PADDR_A (command), 432 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)), 433 PADDR_B (msg_out), 434 /* 435 * Discard as many illegal phases as 436 * required and tell the C code about. 437 */ 438 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)), 439 16, 440 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT, 441 HADDR_1 (scratch), 442 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)), 443 -16, 444 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)), 445 16, 446 SCR_MOVE_ABS (1) ^ SCR_ILG_IN, 447 HADDR_1 (scratch), 448 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)), 449 -16, 450 SCR_INT, 451 SIR_BAD_PHASE, 452 SCR_JUMP, 453 PADDR_A (dispatch), 454 }/*-------------------------< SEL_NO_CMD >-----------------------*/,{ 455 /* 456 * The target does not switch to command 457 * phase after IDENTIFY has been sent. 458 * 459 * If it stays in MSG OUT phase send it 460 * the IDENTIFY again. 461 */ 462 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 463 PADDR_B (resend_ident), 464 /* 465 * If target does not switch to MSG IN phase 466 * and we sent a negotiation, assert the 467 * failure immediately. 468 */ 469 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 470 PADDR_A (dispatch), 471 SCR_FROM_REG (HS_REG), 472 0, 473 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), 474 SIR_NEGO_FAILED, 475 /* 476 * Jump to dispatcher. 477 */ 478 SCR_JUMP, 479 PADDR_A (dispatch), 480 }/*-------------------------< INIT >-----------------------------*/,{ 481 /* 482 * Wait for the SCSI RESET signal to be 483 * inactive before restarting operations, 484 * since the chip may hang on SEL_ATN 485 * if SCSI RESET is active. 486 */ 487 SCR_FROM_REG (sstat0), 488 0, 489 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), 490 -16, 491 SCR_JUMP, 492 PADDR_A (start), 493 }/*-------------------------< CLRACK >---------------------------*/,{ 494 /* 495 * Terminate possible pending message phase. 496 */ 497 SCR_CLR (SCR_ACK), 498 0, 499 SCR_JUMP, 500 PADDR_A (dispatch), 501 }/*-------------------------< DATAI_DONE >-----------------------*/,{ 502 /* 503 * Save current pointer to LASTP. 504 */ 505 SCR_COPY (4), 506 RADDR_1 (temp), 507 HADDR_1 (ccb_head.lastp), 508 /* 509 * If the SWIDE is not full, jump to dispatcher. 510 * We anticipate a STATUS phase. 511 */ 512 SCR_FROM_REG (scntl2), 513 0, 514 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)), 515 PADDR_A (datai_done_wsr), 516 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), 517 PADDR_A (status), 518 SCR_JUMP, 519 PADDR_A (dispatch), 520 }/*-------------------------< DATAI_DONE_WSR >-------------------*/,{ 521 /* 522 * The SWIDE is full. 523 * Clear this condition. 524 */ 525 SCR_REG_REG (scntl2, SCR_OR, WSR), 526 0, 527 /* 528 * We are expecting an IGNORE RESIDUE message 529 * from the device, otherwise we are in data 530 * overrun condition. Check against MSG_IN phase. 531 */ 532 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 533 SIR_SWIDE_OVERRUN, 534 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 535 PADDR_A (dispatch), 536 /* 537 * We are in MSG_IN phase, 538 * Read the first byte of the message. 539 * If it is not an IGNORE RESIDUE message, 540 * signal overrun and jump to message 541 * processing. 542 */ 543 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 544 HADDR_1 (msgin[0]), 545 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)), 546 SIR_SWIDE_OVERRUN, 547 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)), 548 PADDR_A (msg_in2), 549 /* 550 * We got the message we expected. 551 * Read the 2nd byte, and jump to dispatcher. 552 */ 553 SCR_CLR (SCR_ACK), 554 0, 555 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 556 HADDR_1 (msgin[1]), 557 SCR_CLR (SCR_ACK), 558 0, 559 SCR_JUMP, 560 PADDR_A (dispatch), 561 }/*-------------------------< DATAO_DONE >-----------------------*/,{ 562 /* 563 * Save current pointer to LASTP. 564 */ 565 SCR_COPY (4), 566 RADDR_1 (temp), 567 HADDR_1 (ccb_head.lastp), 568 /* 569 * If the SODL is not full jump to dispatcher. 570 * We anticipate a STATUS phase. 571 */ 572 SCR_FROM_REG (scntl2), 573 0, 574 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)), 575 PADDR_A (datao_done_wss), 576 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), 577 PADDR_A (status), 578 SCR_JUMP, 579 PADDR_A (dispatch), 580 }/*-------------------------< DATAO_DONE_WSS >-------------------*/,{ 581 /* 582 * The SODL is full, clear this condition. 583 */ 584 SCR_REG_REG (scntl2, SCR_OR, WSS), 585 0, 586 /* 587 * And signal a DATA UNDERRUN condition 588 * to the C code. 589 */ 590 SCR_INT, 591 SIR_SODL_UNDERRUN, 592 SCR_JUMP, 593 PADDR_A (dispatch), 594 }/*-------------------------< DATAI_PHASE >----------------------*/,{ 595 /* 596 * Jump to current pointer. 597 */ 598 SCR_COPY (4), 599 HADDR_1 (ccb_head.lastp), 600 RADDR_1 (temp), 601 SCR_RETURN, 602 0, 603 }/*-------------------------< DATAO_PHASE >----------------------*/,{ 604 /* 605 * Jump to current pointer. 606 */ 607 SCR_COPY (4), 608 HADDR_1 (ccb_head.lastp), 609 RADDR_1 (temp), 610 SCR_RETURN, 611 0, 612 }/*-------------------------< MSG_IN >---------------------------*/,{ 613 /* 614 * Get the first byte of the message. 615 * 616 * The script processor doesn't negate the 617 * ACK signal after this transfer. 618 */ 619 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 620 HADDR_1 (msgin[0]), 621 }/*-------------------------< MSG_IN2 >--------------------------*/,{ 622 /* 623 * Check first against 1 byte messages 624 * that we handle from SCRIPTS. 625 */ 626 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)), 627 PADDR_A (complete), 628 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)), 629 PADDR_A (disconnect), 630 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)), 631 PADDR_A (save_dp), 632 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)), 633 PADDR_A (restore_dp), 634 /* 635 * We handle all other messages from the 636 * C code, so no need to waste on-chip RAM 637 * for those ones. 638 */ 639 SCR_JUMP, 640 PADDR_B (msg_in_etc), 641 }/*-------------------------< STATUS >---------------------------*/,{ 642 /* 643 * get the status 644 */ 645 SCR_MOVE_ABS (1) ^ SCR_STATUS, 646 HADDR_1 (scratch), 647 #ifdef SYM_CONF_IARB_SUPPORT 648 /* 649 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION, 650 * since we may have to tamper the start queue from 651 * the C code. 652 */ 653 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)), 654 8, 655 SCR_REG_REG (scntl1, SCR_AND, ~IARB), 656 0, 657 #endif 658 /* 659 * save status to scsi_status. 660 * mark as complete. 661 */ 662 SCR_TO_REG (SS_REG), 663 0, 664 SCR_LOAD_REG (HS_REG, HS_COMPLETE), 665 0, 666 /* 667 * Anticipate the MESSAGE PHASE for 668 * the TASK COMPLETE message. 669 */ 670 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 671 PADDR_A (msg_in), 672 SCR_JUMP, 673 PADDR_A (dispatch), 674 }/*-------------------------< COMPLETE >-------------------------*/,{ 675 /* 676 * Complete message. 677 * 678 * When we terminate the cycle by clearing ACK, 679 * the target may disconnect immediately. 680 * 681 * We don't want to be told of an "unexpected disconnect", 682 * so we disable this feature. 683 */ 684 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 685 0, 686 /* 687 * Terminate cycle ... 688 */ 689 SCR_CLR (SCR_ACK|SCR_ATN), 690 0, 691 /* 692 * ... and wait for the disconnect. 693 */ 694 SCR_WAIT_DISC, 695 0, 696 }/*-------------------------< COMPLETE2 >------------------------*/,{ 697 /* 698 * Save host status. 699 */ 700 SCR_COPY (4), 701 RADDR_1 (scr0), 702 HADDR_1 (ccb_head.status), 703 /* 704 * Move back the CCB header using self-modifying 705 * SCRIPTS. 706 */ 707 SCR_COPY (4), 708 RADDR_1 (dsa), 709 PADDR_A (_sms_a40), 710 SCR_COPY (sizeof(struct sym_ccbh)), 711 HADDR_1 (ccb_head), 712 }/*-------------------------< _SMS_A40 >-------------------------*/,{ 713 0, 714 /* 715 * Some bridges may reorder DMA writes to memory. 716 * We donnot want the CPU to deal with completions 717 * without all the posted write having been flushed 718 * to memory. This DUMMY READ should flush posted 719 * buffers prior to the CPU having to deal with 720 * completions. 721 */ 722 SCR_COPY (4), /* DUMMY READ */ 723 HADDR_1 (ccb_head.status), 724 RADDR_1 (scr0), 725 /* 726 * If command resulted in not GOOD status, 727 * call the C code if needed. 728 */ 729 SCR_FROM_REG (SS_REG), 730 0, 731 SCR_CALL ^ IFFALSE (DATA (S_GOOD)), 732 PADDR_B (bad_status), 733 /* 734 * If we performed an auto-sense, call 735 * the C code to synchronyze task aborts 736 * with UNIT ATTENTION conditions. 737 */ 738 SCR_FROM_REG (HF_REG), 739 0, 740 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), 741 PADDR_A (complete_error), 742 }/*-------------------------< DONE >-----------------------------*/,{ 743 /* 744 * Copy the DSA to the DONE QUEUE and 745 * signal completion to the host. 746 * If we are interrupted between DONE 747 * and DONE_END, we must reset, otherwise 748 * the completed CCB may be lost. 749 */ 750 SCR_COPY (4), 751 PADDR_B (done_pos), 752 PADDR_A (_sms_a50), 753 SCR_COPY (4), 754 RADDR_1 (dsa), 755 }/*-------------------------< _SMS_A50 >-------------------------*/,{ 756 0, 757 SCR_COPY (4), 758 PADDR_B (done_pos), 759 PADDR_A (_sms_a60), 760 /* 761 * The instruction below reads the DONE QUEUE next 762 * free position from memory. 763 * In addition it ensures that all PCI posted writes 764 * are flushed and so the DSA value of the done 765 * CCB is visible by the CPU before INTFLY is raised. 766 */ 767 SCR_COPY (8), 768 }/*-------------------------< _SMS_A60 >-------------------------*/,{ 769 0, 770 PADDR_B (prev_done), 771 }/*-------------------------< DONE_END >-------------------------*/,{ 772 SCR_INT_FLY, 773 0, 774 SCR_JUMP, 775 PADDR_A (start), 776 }/*-------------------------< COMPLETE_ERROR >-------------------*/,{ 777 SCR_COPY (4), 778 PADDR_B (startpos), 779 RADDR_1 (scratcha), 780 SCR_INT, 781 SIR_COMPLETE_ERROR, 782 }/*-------------------------< SAVE_DP >--------------------------*/,{ 783 /* 784 * Clear ACK immediately. 785 * No need to delay it. 786 */ 787 SCR_CLR (SCR_ACK), 788 0, 789 /* 790 * Keep track we received a SAVE DP, so 791 * we will switch to the other PM context 792 * on the next PM since the DP may point 793 * to the current PM context. 794 */ 795 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 796 0, 797 /* 798 * SAVE_DP message: 799 * Copy LASTP to SAVEP. 800 */ 801 SCR_COPY (4), 802 HADDR_1 (ccb_head.lastp), 803 HADDR_1 (ccb_head.savep), 804 /* 805 * Anticipate the MESSAGE PHASE for 806 * the DISCONNECT message. 807 */ 808 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 809 PADDR_A (msg_in), 810 SCR_JUMP, 811 PADDR_A (dispatch), 812 }/*-------------------------< RESTORE_DP >-----------------------*/,{ 813 /* 814 * Clear ACK immediately. 815 * No need to delay it. 816 */ 817 SCR_CLR (SCR_ACK), 818 0, 819 /* 820 * Copy SAVEP to LASTP. 821 */ 822 SCR_COPY (4), 823 HADDR_1 (ccb_head.savep), 824 HADDR_1 (ccb_head.lastp), 825 SCR_JUMP, 826 PADDR_A (dispatch), 827 }/*-------------------------< DISCONNECT >-----------------------*/,{ 828 /* 829 * DISCONNECTing ... 830 * 831 * disable the "unexpected disconnect" feature, 832 * and remove the ACK signal. 833 */ 834 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 835 0, 836 SCR_CLR (SCR_ACK|SCR_ATN), 837 0, 838 /* 839 * Wait for the disconnect. 840 */ 841 SCR_WAIT_DISC, 842 0, 843 /* 844 * Status is: DISCONNECTED. 845 */ 846 SCR_LOAD_REG (HS_REG, HS_DISCONNECT), 847 0, 848 /* 849 * Save host status. 850 */ 851 SCR_COPY (4), 852 RADDR_1 (scr0), 853 HADDR_1 (ccb_head.status), 854 }/*-------------------------< DISCONNECT2 >----------------------*/,{ 855 /* 856 * Move back the CCB header using self-modifying 857 * SCRIPTS. 858 */ 859 SCR_COPY (4), 860 RADDR_1 (dsa), 861 PADDR_A (_sms_a65), 862 SCR_COPY (sizeof(struct sym_ccbh)), 863 HADDR_1 (ccb_head), 864 }/*-------------------------< _SMS_A65 >-------------------------*/,{ 865 0, 866 SCR_JUMP, 867 PADDR_A (start), 868 }/*-------------------------< IDLE >-----------------------------*/,{ 869 /* 870 * Nothing to do? 871 * Switch the LED off and wait for reselect. 872 * Will be patched with a NO_OP if LED 873 * not needed or not desired. 874 */ 875 SCR_REG_REG (gpreg, SCR_OR, 0x01), 876 0, 877 #ifdef SYM_CONF_IARB_SUPPORT 878 SCR_JUMPR, 879 8, 880 #endif 881 }/*-------------------------< UNGETJOB >-------------------------*/,{ 882 #ifdef SYM_CONF_IARB_SUPPORT 883 /* 884 * Set IMMEDIATE ARBITRATION, for the next time. 885 * This will give us better chance to win arbitration 886 * for the job we just wanted to do. 887 */ 888 SCR_REG_REG (scntl1, SCR_OR, IARB), 889 0, 890 #endif 891 /* 892 * We are not able to restart the SCRIPTS if we are 893 * interrupted and these instruction haven't been 894 * all executed. BTW, this is very unlikely to 895 * happen, but we check that from the C code. 896 */ 897 SCR_LOAD_REG (dsa, 0xff), 898 0, 899 SCR_COPY (4), 900 RADDR_1 (scratcha), 901 PADDR_B (startpos), 902 }/*-------------------------< RESELECT >-------------------------*/,{ 903 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT 904 /* 905 * Make sure we are in initiator mode. 906 */ 907 SCR_CLR (SCR_TRG), 908 0, 909 #endif 910 /* 911 * Sleep waiting for a reselection. 912 */ 913 SCR_WAIT_RESEL, 914 PADDR_A(start), 915 }/*-------------------------< RESELECTED >-----------------------*/,{ 916 /* 917 * Switch the LED on. 918 * Will be patched with a NO_OP if LED 919 * not needed or not desired. 920 */ 921 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 922 0, 923 /* 924 * load the target id into the sdid 925 */ 926 SCR_REG_SFBR (ssid, SCR_AND, 0x8F), 927 0, 928 SCR_TO_REG (sdid), 929 0, 930 /* 931 * Load the target control block address 932 */ 933 SCR_COPY (4), 934 PADDR_B (targtbl), 935 RADDR_1 (dsa), 936 SCR_SFBR_REG (dsa, SCR_SHL, 0), 937 0, 938 SCR_REG_REG (dsa, SCR_SHL, 0), 939 0, 940 SCR_REG_REG (dsa, SCR_AND, 0x3c), 941 0, 942 SCR_COPY (4), 943 RADDR_1 (dsa), 944 PADDR_A (_sms_a70), 945 SCR_COPY (4), 946 }/*-------------------------< _SMS_A70 >-------------------------*/,{ 947 0, 948 RADDR_1 (dsa), 949 /* 950 * Copy the TCB header to a fixed place in 951 * the HCB. 952 */ 953 SCR_COPY (4), 954 RADDR_1 (dsa), 955 PADDR_A (_sms_a80), 956 SCR_COPY (sizeof(struct sym_tcbh)), 957 }/*-------------------------< _SMS_A80 >-------------------------*/,{ 958 0, 959 HADDR_1 (tcb_head), 960 /* 961 * We expect MESSAGE IN phase. 962 * If not, get help from the C code. 963 */ 964 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 965 SIR_RESEL_NO_MSG_IN, 966 }/*-------------------------< RESELECTED1 >----------------------*/,{ 967 /* 968 * Load the synchronous transfer registers. 969 */ 970 SCR_COPY (1), 971 HADDR_1 (tcb_head.wval), 972 RADDR_1 (scntl3), 973 SCR_COPY (1), 974 HADDR_1 (tcb_head.sval), 975 RADDR_1 (sxfer), 976 /* 977 * Get the IDENTIFY message. 978 */ 979 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 980 HADDR_1 (msgin), 981 /* 982 * If IDENTIFY LUN #0, use a faster path 983 * to find the LCB structure. 984 */ 985 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), 986 PADDR_A (resel_lun0), 987 /* 988 * If message isn't an IDENTIFY, 989 * tell the C code about. 990 */ 991 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), 992 SIR_RESEL_NO_IDENTIFY, 993 /* 994 * It is an IDENTIFY message, 995 * Load the LUN control block address. 996 */ 997 SCR_COPY (4), 998 HADDR_1 (tcb_head.luntbl_sa), 999 RADDR_1 (dsa), 1000 SCR_SFBR_REG (dsa, SCR_SHL, 0), 1001 0, 1002 SCR_REG_REG (dsa, SCR_SHL, 0), 1003 0, 1004 SCR_REG_REG (dsa, SCR_AND, 0xfc), 1005 0, 1006 SCR_COPY (4), 1007 RADDR_1 (dsa), 1008 PADDR_A (_sms_a90), 1009 SCR_COPY (4), 1010 }/*-------------------------< _SMS_A90 >-------------------------*/,{ 1011 0, 1012 RADDR_1 (dsa), 1013 SCR_JUMPR, 1014 12, 1015 }/*-------------------------< RESEL_LUN0 >-----------------------*/,{ 1016 /* 1017 * LUN 0 special case (but usual one :)) 1018 */ 1019 SCR_COPY (4), 1020 HADDR_1 (tcb_head.lun0_sa), 1021 RADDR_1 (dsa), 1022 /* 1023 * Jump indirectly to the reselect action for this LUN. 1024 * (lcb.head.resel_sa assumed at offset zero of lcb). 1025 */ 1026 SCR_COPY (4), 1027 RADDR_1 (dsa), 1028 PADDR_A (_sms_a100), 1029 SCR_COPY (4), 1030 }/*-------------------------< _SMS_A100 >------------------------*/,{ 1031 0, 1032 RADDR_1 (temp), 1033 SCR_RETURN, 1034 0, 1035 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */ 1036 }/*-------------------------< RESEL_TAG >------------------------*/,{ 1037 /* 1038 * ACK the IDENTIFY previously received. 1039 */ 1040 SCR_CLR (SCR_ACK), 1041 0, 1042 /* 1043 * It shall be a tagged command. 1044 * Read SIMPLE+TAG. 1045 * The C code will deal with errors. 1046 * Agressive optimization, is'nt it? :) 1047 */ 1048 SCR_MOVE_ABS (2) ^ SCR_MSG_IN, 1049 HADDR_1 (msgin), 1050 /* 1051 * Copy the LCB header to a fixed place in 1052 * the HCB using self-modifying SCRIPTS. 1053 */ 1054 SCR_COPY (4), 1055 RADDR_1 (dsa), 1056 PADDR_A (_sms_a110), 1057 SCR_COPY (sizeof(struct sym_lcbh)), 1058 }/*-------------------------< _SMS_A110 >------------------------*/,{ 1059 0, 1060 HADDR_1 (lcb_head), 1061 /* 1062 * Load the pointer to the tagged task 1063 * table for this LUN. 1064 */ 1065 SCR_COPY (4), 1066 HADDR_1 (lcb_head.itlq_tbl_sa), 1067 RADDR_1 (dsa), 1068 /* 1069 * The SIDL still contains the TAG value. 1070 * Agressive optimization, isn't it? :):) 1071 */ 1072 SCR_REG_SFBR (sidl, SCR_SHL, 0), 1073 0, 1074 #if SYM_CONF_MAX_TASK*4 > 512 1075 SCR_JUMPR ^ IFFALSE (CARRYSET), 1076 8, 1077 SCR_REG_REG (dsa1, SCR_OR, 2), 1078 0, 1079 SCR_REG_REG (sfbr, SCR_SHL, 0), 1080 0, 1081 SCR_JUMPR ^ IFFALSE (CARRYSET), 1082 8, 1083 SCR_REG_REG (dsa1, SCR_OR, 1), 1084 0, 1085 #elif SYM_CONF_MAX_TASK*4 > 256 1086 SCR_JUMPR ^ IFFALSE (CARRYSET), 1087 8, 1088 SCR_REG_REG (dsa1, SCR_OR, 1), 1089 0, 1090 #endif 1091 /* 1092 * Retrieve the DSA of this task. 1093 * JUMP indirectly to the restart point of the CCB. 1094 */ 1095 SCR_SFBR_REG (dsa, SCR_AND, 0xfc), 1096 0, 1097 SCR_COPY (4), 1098 RADDR_1 (dsa), 1099 PADDR_A (_sms_a120), 1100 SCR_COPY (4), 1101 }/*-------------------------< _SMS_A120 >------------------------*/,{ 1102 0, 1103 RADDR_1 (dsa), 1104 }/*-------------------------< RESEL_GO >-------------------------*/,{ 1105 SCR_COPY (4), 1106 RADDR_1 (dsa), 1107 PADDR_A (_sms_a130), 1108 /* 1109 * Move 'ccb.phys.head.go' action to 1110 * scratch/scratch1. So scratch1 will 1111 * contain the 'restart' field of the 1112 * 'go' structure. 1113 */ 1114 SCR_COPY (8), 1115 }/*-------------------------< _SMS_A130 >------------------------*/,{ 1116 0, 1117 PADDR_B (scratch), 1118 SCR_COPY (4), 1119 PADDR_B (scratch1), /* phys.head.go.restart */ 1120 RADDR_1 (temp), 1121 SCR_RETURN, 1122 0, 1123 /* In normal situations we branch to RESEL_DSA */ 1124 }/*-------------------------< RESEL_DSA >------------------------*/,{ 1125 /* 1126 * ACK the IDENTIFY or TAG previously received. 1127 */ 1128 SCR_CLR (SCR_ACK), 1129 0, 1130 }/*-------------------------< RESEL_DSA1 >-----------------------*/,{ 1131 /* 1132 * Copy the CCB header to a fixed location 1133 * in the HCB using self-modifying SCRIPTS. 1134 */ 1135 SCR_COPY (4), 1136 RADDR_1 (dsa), 1137 PADDR_A (_sms_a140), 1138 SCR_COPY (sizeof(struct sym_ccbh)), 1139 }/*-------------------------< _SMS_A140 >------------------------*/,{ 1140 0, 1141 HADDR_1 (ccb_head), 1142 /* 1143 * Initialize the status register 1144 */ 1145 SCR_COPY (4), 1146 HADDR_1 (ccb_head.status), 1147 RADDR_1 (scr0), 1148 /* 1149 * Jump to dispatcher. 1150 */ 1151 SCR_JUMP, 1152 PADDR_A (dispatch), 1153 }/*-------------------------< RESEL_NO_TAG >---------------------*/,{ 1154 /* 1155 * Copy the LCB header to a fixed place in 1156 * the HCB using self-modifying SCRIPTS. 1157 */ 1158 SCR_COPY (4), 1159 RADDR_1 (dsa), 1160 PADDR_A (_sms_a145), 1161 SCR_COPY (sizeof(struct sym_lcbh)), 1162 }/*-------------------------< _SMS_A145 >------------------------*/,{ 1163 0, 1164 HADDR_1 (lcb_head), 1165 /* 1166 * Load the DSA with the unique ITL task. 1167 */ 1168 SCR_COPY (4), 1169 HADDR_1 (lcb_head.itl_task_sa), 1170 RADDR_1 (dsa), 1171 SCR_JUMP, 1172 PADDR_A (resel_go), 1173 }/*-------------------------< DATA_IN >--------------------------*/,{ 1174 /* 1175 * Because the size depends on the 1176 * #define SYM_CONF_MAX_SG parameter, 1177 * it is filled in at runtime. 1178 * 1179 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1180 * || SCR_CHMOV_TBL ^ SCR_DATA_IN, 1181 * || offsetof (struct sym_dsb, data[ i]), 1182 * ##========================================== 1183 */ 1184 0 1185 }/*-------------------------< DATA_IN2 >-------------------------*/,{ 1186 SCR_CALL, 1187 PADDR_A (datai_done), 1188 SCR_JUMP, 1189 PADDR_B (data_ovrun), 1190 }/*-------------------------< DATA_OUT >-------------------------*/,{ 1191 /* 1192 * Because the size depends on the 1193 * #define SYM_CONF_MAX_SG parameter, 1194 * it is filled in at runtime. 1195 * 1196 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1197 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1198 * || offsetof (struct sym_dsb, data[ i]), 1199 * ##========================================== 1200 */ 1201 0 1202 }/*-------------------------< DATA_OUT2 >------------------------*/,{ 1203 SCR_CALL, 1204 PADDR_A (datao_done), 1205 SCR_JUMP, 1206 PADDR_B (data_ovrun), 1207 }/*-------------------------< PM0_DATA >-------------------------*/,{ 1208 /* 1209 * Read our host flags to SFBR, so we will be able 1210 * to check against the data direction we expect. 1211 */ 1212 SCR_FROM_REG (HF_REG), 1213 0, 1214 /* 1215 * Check against actual DATA PHASE. 1216 */ 1217 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1218 PADDR_A (pm0_data_out), 1219 /* 1220 * Actual phase is DATA IN. 1221 * Check against expected direction. 1222 */ 1223 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1224 PADDR_B (data_ovrun), 1225 /* 1226 * Keep track we are moving data from the 1227 * PM0 DATA mini-script. 1228 */ 1229 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1230 0, 1231 /* 1232 * Move the data to memory. 1233 */ 1234 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1235 offsetof (struct sym_ccb, phys.pm0.sg), 1236 SCR_JUMP, 1237 PADDR_A (pm0_data_end), 1238 }/*-------------------------< PM0_DATA_OUT >---------------------*/,{ 1239 /* 1240 * Actual phase is DATA OUT. 1241 * Check against expected direction. 1242 */ 1243 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1244 PADDR_B (data_ovrun), 1245 /* 1246 * Keep track we are moving data from the 1247 * PM0 DATA mini-script. 1248 */ 1249 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1250 0, 1251 /* 1252 * Move the data from memory. 1253 */ 1254 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1255 offsetof (struct sym_ccb, phys.pm0.sg), 1256 }/*-------------------------< PM0_DATA_END >---------------------*/,{ 1257 /* 1258 * Clear the flag that told we were moving 1259 * data from the PM0 DATA mini-script. 1260 */ 1261 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)), 1262 0, 1263 /* 1264 * Return to the previous DATA script which 1265 * is guaranteed by design (if no bug) to be 1266 * the main DATA script for this transfer. 1267 */ 1268 SCR_COPY (4), 1269 RADDR_1 (dsa), 1270 RADDR_1 (scratcha), 1271 SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm0.ret)), 1272 0, 1273 }/*-------------------------< PM_DATA_END >----------------------*/,{ 1274 SCR_COPY (4), 1275 RADDR_1 (scratcha), 1276 PADDR_A (_sms_a150), 1277 SCR_COPY (4), 1278 }/*-------------------------< _SMS_A150 >------------------------*/,{ 1279 0, 1280 RADDR_1 (temp), 1281 SCR_RETURN, 1282 0, 1283 }/*-------------------------< PM1_DATA >-------------------------*/,{ 1284 /* 1285 * Read our host flags to SFBR, so we will be able 1286 * to check against the data direction we expect. 1287 */ 1288 SCR_FROM_REG (HF_REG), 1289 0, 1290 /* 1291 * Check against actual DATA PHASE. 1292 */ 1293 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1294 PADDR_A (pm1_data_out), 1295 /* 1296 * Actual phase is DATA IN. 1297 * Check against expected direction. 1298 */ 1299 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1300 PADDR_B (data_ovrun), 1301 /* 1302 * Keep track we are moving data from the 1303 * PM1 DATA mini-script. 1304 */ 1305 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1306 0, 1307 /* 1308 * Move the data to memory. 1309 */ 1310 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1311 offsetof (struct sym_ccb, phys.pm1.sg), 1312 SCR_JUMP, 1313 PADDR_A (pm1_data_end), 1314 }/*-------------------------< PM1_DATA_OUT >---------------------*/,{ 1315 /* 1316 * Actual phase is DATA OUT. 1317 * Check against expected direction. 1318 */ 1319 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1320 PADDR_B (data_ovrun), 1321 /* 1322 * Keep track we are moving data from the 1323 * PM1 DATA mini-script. 1324 */ 1325 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1326 0, 1327 /* 1328 * Move the data from memory. 1329 */ 1330 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1331 offsetof (struct sym_ccb, phys.pm1.sg), 1332 }/*-------------------------< PM1_DATA_END >---------------------*/,{ 1333 /* 1334 * Clear the flag that told we were moving 1335 * data from the PM1 DATA mini-script. 1336 */ 1337 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)), 1338 0, 1339 /* 1340 * Return to the previous DATA script which 1341 * is guaranteed by design (if no bug) to be 1342 * the main DATA script for this transfer. 1343 */ 1344 SCR_COPY (4), 1345 RADDR_1 (dsa), 1346 RADDR_1 (scratcha), 1347 SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm1.ret)), 1348 0, 1349 SCR_JUMP, 1350 PADDR_A (pm_data_end), 1351 }/*--------------------------<>----------------------------------*/ 1352 }; 1353 1354 static struct SYM_FWB_SCR SYM_FWB_SCR = { 1355 /*-------------------------< NO_DATA >--------------------------*/ { 1356 SCR_JUMP, 1357 PADDR_B (data_ovrun), 1358 }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{ 1359 /* 1360 * We are jumped here by the C code, if we have 1361 * some target to reset or some disconnected 1362 * job to abort. Since error recovery is a serious 1363 * busyness, we will really reset the SCSI BUS, if 1364 * case of a SCSI interrupt occuring in this path. 1365 */ 1366 1367 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT 1368 /* 1369 * Set initiator mode. 1370 */ 1371 SCR_CLR (SCR_TRG), 1372 0, 1373 #endif 1374 /* 1375 * And try to select this target. 1376 */ 1377 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel), 1378 PADDR_A (reselect), 1379 /* 1380 * Wait for the selection to complete or 1381 * the selection to time out. 1382 */ 1383 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1384 -8, 1385 /* 1386 * Call the C code. 1387 */ 1388 SCR_INT, 1389 SIR_TARGET_SELECTED, 1390 /* 1391 * The C code should let us continue here. 1392 * Send the 'kiss of death' message. 1393 * We expect an immediate disconnect once 1394 * the target has eaten the message. 1395 */ 1396 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1397 0, 1398 SCR_MOVE_TBL ^ SCR_MSG_OUT, 1399 offsetof (struct sym_hcb, abrt_tbl), 1400 SCR_CLR (SCR_ACK|SCR_ATN), 1401 0, 1402 SCR_WAIT_DISC, 1403 0, 1404 /* 1405 * Tell the C code that we are done. 1406 */ 1407 SCR_INT, 1408 SIR_ABORT_SENT, 1409 }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{ 1410 /* 1411 * Jump at scheduler. 1412 */ 1413 SCR_JUMP, 1414 PADDR_A (start), 1415 }/*-------------------------< MSG_IN_ETC >-----------------------*/,{ 1416 /* 1417 * If it is an EXTENDED (variable size message) 1418 * Handle it. 1419 */ 1420 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)), 1421 PADDR_B (msg_extended), 1422 /* 1423 * Let the C code handle any other 1424 * 1 byte message. 1425 */ 1426 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)), 1427 PADDR_B (msg_received), 1428 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)), 1429 PADDR_B (msg_received), 1430 /* 1431 * We donnot handle 2 bytes messages from SCRIPTS. 1432 * So, let the C code deal with these ones too. 1433 */ 1434 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)), 1435 PADDR_B (msg_weird_seen), 1436 SCR_CLR (SCR_ACK), 1437 0, 1438 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1439 HADDR_1 (msgin[1]), 1440 }/*-------------------------< MSG_RECEIVED >---------------------*/,{ 1441 SCR_COPY (4), /* DUMMY READ */ 1442 HADDR_1 (scratch), 1443 RADDR_1 (scratcha), 1444 SCR_INT, 1445 SIR_MSG_RECEIVED, 1446 }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{ 1447 SCR_COPY (4), /* DUMMY READ */ 1448 HADDR_1 (scratch), 1449 RADDR_1 (scratcha), 1450 SCR_INT, 1451 SIR_MSG_WEIRD, 1452 }/*-------------------------< MSG_EXTENDED >---------------------*/,{ 1453 /* 1454 * Clear ACK and get the next byte 1455 * assumed to be the message length. 1456 */ 1457 SCR_CLR (SCR_ACK), 1458 0, 1459 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1460 HADDR_1 (msgin[1]), 1461 /* 1462 * Try to catch some unlikely situations as 0 length 1463 * or too large the length. 1464 */ 1465 SCR_JUMP ^ IFTRUE (DATA (0)), 1466 PADDR_B (msg_weird_seen), 1467 SCR_TO_REG (scratcha), 1468 0, 1469 SCR_REG_REG (sfbr, SCR_ADD, (256-8)), 1470 0, 1471 SCR_JUMP ^ IFTRUE (CARRYSET), 1472 PADDR_B (msg_weird_seen), 1473 /* 1474 * We donnot handle extended messages from SCRIPTS. 1475 * Read the amount of data correponding to the 1476 * message length and call the C code. 1477 */ 1478 SCR_COPY (1), 1479 RADDR_1 (scratcha), 1480 PADDR_B (_sms_b10), 1481 SCR_CLR (SCR_ACK), 1482 0, 1483 }/*-------------------------< _SMS_B10 >-------------------------*/,{ 1484 SCR_MOVE_ABS (0) ^ SCR_MSG_IN, 1485 HADDR_1 (msgin[2]), 1486 SCR_JUMP, 1487 PADDR_B (msg_received), 1488 }/*-------------------------< MSG_BAD >--------------------------*/,{ 1489 /* 1490 * unimplemented message - reject it. 1491 */ 1492 SCR_INT, 1493 SIR_REJECT_TO_SEND, 1494 SCR_SET (SCR_ATN), 1495 0, 1496 SCR_JUMP, 1497 PADDR_A (clrack), 1498 }/*-------------------------< MSG_WEIRD >------------------------*/,{ 1499 /* 1500 * weird message received 1501 * ignore all MSG IN phases and reject it. 1502 */ 1503 SCR_INT, 1504 SIR_REJECT_TO_SEND, 1505 SCR_SET (SCR_ATN), 1506 0, 1507 }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{ 1508 SCR_CLR (SCR_ACK), 1509 0, 1510 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 1511 PADDR_A (dispatch), 1512 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1513 HADDR_1 (scratch), 1514 SCR_JUMP, 1515 PADDR_B (msg_weird1), 1516 }/*-------------------------< WDTR_RESP >------------------------*/,{ 1517 /* 1518 * let the target fetch our answer. 1519 */ 1520 SCR_SET (SCR_ATN), 1521 0, 1522 SCR_CLR (SCR_ACK), 1523 0, 1524 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1525 PADDR_B (nego_bad_phase), 1526 }/*-------------------------< SEND_WDTR >------------------------*/,{ 1527 /* 1528 * Send the M_X_WIDE_REQ 1529 */ 1530 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT, 1531 HADDR_1 (msgout), 1532 SCR_JUMP, 1533 PADDR_B (msg_out_done), 1534 }/*-------------------------< SDTR_RESP >------------------------*/,{ 1535 /* 1536 * let the target fetch our answer. 1537 */ 1538 SCR_SET (SCR_ATN), 1539 0, 1540 SCR_CLR (SCR_ACK), 1541 0, 1542 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1543 PADDR_B (nego_bad_phase), 1544 }/*-------------------------< SEND_SDTR >------------------------*/,{ 1545 /* 1546 * Send the M_X_SYNC_REQ 1547 */ 1548 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT, 1549 HADDR_1 (msgout), 1550 SCR_JUMP, 1551 PADDR_B (msg_out_done), 1552 }/*-------------------------< PPR_RESP >-------------------------*/,{ 1553 /* 1554 * let the target fetch our answer. 1555 */ 1556 SCR_SET (SCR_ATN), 1557 0, 1558 SCR_CLR (SCR_ACK), 1559 0, 1560 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1561 PADDR_B (nego_bad_phase), 1562 }/*-------------------------< SEND_PPR >-------------------------*/,{ 1563 /* 1564 * Send the M_X_PPR_REQ 1565 */ 1566 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT, 1567 HADDR_1 (msgout), 1568 SCR_JUMP, 1569 PADDR_B (msg_out_done), 1570 }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{ 1571 SCR_INT, 1572 SIR_NEGO_PROTO, 1573 SCR_JUMP, 1574 PADDR_A (dispatch), 1575 }/*-------------------------< MSG_OUT >--------------------------*/,{ 1576 /* 1577 * The target requests a message. 1578 * We donnot send messages that may 1579 * require the device to go to bus free. 1580 */ 1581 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1582 HADDR_1 (msgout), 1583 /* 1584 * ... wait for the next phase 1585 * if it's a message out, send it again, ... 1586 */ 1587 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 1588 PADDR_B (msg_out), 1589 }/*-------------------------< MSG_OUT_DONE >---------------------*/,{ 1590 /* 1591 * Let the C code be aware of the 1592 * sent message and clear the message. 1593 */ 1594 SCR_INT, 1595 SIR_MSG_OUT_DONE, 1596 /* 1597 * ... and process the next phase 1598 */ 1599 SCR_JUMP, 1600 PADDR_A (dispatch), 1601 }/*-------------------------< DATA_OVRUN >-----------------------*/,{ 1602 /* 1603 * Zero scratcha that will count the 1604 * extras bytes. 1605 */ 1606 SCR_COPY (4), 1607 PADDR_B (zero), 1608 RADDR_1 (scratcha), 1609 }/*-------------------------< DATA_OVRUN1 >----------------------*/,{ 1610 /* 1611 * The target may want to transfer too much data. 1612 * 1613 * If phase is DATA OUT write 1 byte and count it. 1614 */ 1615 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)), 1616 16, 1617 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT, 1618 HADDR_1 (scratch), 1619 SCR_JUMP, 1620 PADDR_B (data_ovrun2), 1621 /* 1622 * If WSR is set, clear this condition, and 1623 * count this byte. 1624 */ 1625 SCR_FROM_REG (scntl2), 1626 0, 1627 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), 1628 16, 1629 SCR_REG_REG (scntl2, SCR_OR, WSR), 1630 0, 1631 SCR_JUMP, 1632 PADDR_B (data_ovrun2), 1633 /* 1634 * Finally check against DATA IN phase. 1635 * Signal data overrun to the C code 1636 * and jump to dispatcher if not so. 1637 * Read 1 byte otherwise and count it. 1638 */ 1639 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)), 1640 16, 1641 SCR_INT, 1642 SIR_DATA_OVERRUN, 1643 SCR_JUMP, 1644 PADDR_A (dispatch), 1645 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN, 1646 HADDR_1 (scratch), 1647 }/*-------------------------< DATA_OVRUN2 >----------------------*/,{ 1648 /* 1649 * Count this byte. 1650 * This will allow to return a negative 1651 * residual to user. 1652 */ 1653 SCR_REG_REG (scratcha, SCR_ADD, 0x01), 1654 0, 1655 SCR_REG_REG (scratcha1, SCR_ADDC, 0), 1656 0, 1657 SCR_REG_REG (scratcha2, SCR_ADDC, 0), 1658 0, 1659 /* 1660 * .. and repeat as required. 1661 */ 1662 SCR_JUMP, 1663 PADDR_B (data_ovrun1), 1664 }/*-------------------------< ABORT_RESEL >----------------------*/,{ 1665 SCR_SET (SCR_ATN), 1666 0, 1667 SCR_CLR (SCR_ACK), 1668 0, 1669 /* 1670 * send the abort/abortag/reset message 1671 * we expect an immediate disconnect 1672 */ 1673 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1674 0, 1675 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1676 HADDR_1 (msgout), 1677 SCR_CLR (SCR_ACK|SCR_ATN), 1678 0, 1679 SCR_WAIT_DISC, 1680 0, 1681 SCR_INT, 1682 SIR_RESEL_ABORTED, 1683 SCR_JUMP, 1684 PADDR_A (start), 1685 }/*-------------------------< RESEND_IDENT >---------------------*/,{ 1686 /* 1687 * The target stays in MSG OUT phase after having acked 1688 * Identify [+ Tag [+ Extended message ]]. Targets shall 1689 * behave this way on parity error. 1690 * We must send it again all the messages. 1691 */ 1692 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */ 1693 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */ 1694 SCR_JUMP, 1695 PADDR_A (send_ident), 1696 }/*-------------------------< IDENT_BREAK >----------------------*/,{ 1697 SCR_CLR (SCR_ATN), 1698 0, 1699 SCR_JUMP, 1700 PADDR_A (select2), 1701 }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{ 1702 SCR_SET (SCR_ATN), 1703 0, 1704 SCR_JUMP, 1705 PADDR_A (select2), 1706 }/*-------------------------< SDATA_IN >-------------------------*/,{ 1707 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1708 offsetof (struct sym_dsb, sense), 1709 SCR_CALL, 1710 PADDR_A (datai_done), 1711 SCR_JUMP, 1712 PADDR_B (data_ovrun), 1713 }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{ 1714 /* 1715 * Message is an IDENTIFY, but lun is unknown. 1716 * Signal problem to C code for logging the event. 1717 * Send a M_ABORT to clear all pending tasks. 1718 */ 1719 SCR_INT, 1720 SIR_RESEL_BAD_LUN, 1721 SCR_JUMP, 1722 PADDR_B (abort_resel), 1723 }/*-------------------------< BAD_I_T_L >------------------------*/,{ 1724 /* 1725 * We donnot have a task for that I_T_L. 1726 * Signal problem to C code for logging the event. 1727 * Send a M_ABORT message. 1728 */ 1729 SCR_INT, 1730 SIR_RESEL_BAD_I_T_L, 1731 SCR_JUMP, 1732 PADDR_B (abort_resel), 1733 }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{ 1734 /* 1735 * We donnot have a task that matches the tag. 1736 * Signal problem to C code for logging the event. 1737 * Send a M_ABORTTAG message. 1738 */ 1739 SCR_INT, 1740 SIR_RESEL_BAD_I_T_L_Q, 1741 SCR_JUMP, 1742 PADDR_B (abort_resel), 1743 }/*-------------------------< BAD_STATUS >-----------------------*/,{ 1744 /* 1745 * Anything different from INTERMEDIATE 1746 * CONDITION MET should be a bad SCSI status, 1747 * given that GOOD status has already been tested. 1748 * Call the C code. 1749 */ 1750 SCR_COPY (4), 1751 PADDR_B (startpos), 1752 RADDR_1 (scratcha), 1753 SCR_INT ^ IFFALSE (DATA (S_COND_MET)), 1754 SIR_BAD_SCSI_STATUS, 1755 SCR_RETURN, 1756 0, 1757 }/*-------------------------< WSR_MA_HELPER >--------------------*/,{ 1758 /* 1759 * Helper for the C code when WSR bit is set. 1760 * Perform the move of the residual byte. 1761 */ 1762 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1763 offsetof (struct sym_ccb, phys.wresid), 1764 SCR_JUMP, 1765 PADDR_A (dispatch), 1766 1767 #ifdef SYM_OPT_HANDLE_DIR_UNKNOWN 1768 }/*-------------------------< DATA_IO >--------------------------*/,{ 1769 /* 1770 * We jump here if the data direction was unknown at the 1771 * time we had to queue the command to the scripts processor. 1772 * Pointers had been set as follow in this situation: 1773 * savep --> DATA_IO 1774 * lastp --> start pointer when DATA_IN 1775 * wlastp --> start pointer when DATA_OUT 1776 * This script sets savep and lastp according to the 1777 * direction chosen by the target. 1778 */ 1779 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)), 1780 PADDR_B (data_io_out), 1781 }/*-------------------------< DATA_IO_COM >----------------------*/,{ 1782 /* 1783 * Direction is DATA IN. 1784 */ 1785 SCR_COPY (4), 1786 HADDR_1 (ccb_head.lastp), 1787 HADDR_1 (ccb_head.savep), 1788 /* 1789 * Jump to the SCRIPTS according to actual direction. 1790 */ 1791 SCR_COPY (4), 1792 HADDR_1 (ccb_head.savep), 1793 RADDR_1 (temp), 1794 SCR_RETURN, 1795 0, 1796 }/*-------------------------< DATA_IO_OUT >----------------------*/,{ 1797 /* 1798 * Direction is DATA OUT. 1799 */ 1800 SCR_REG_REG (HF_REG, SCR_AND, (~HF_DATA_IN)), 1801 0, 1802 SCR_COPY (4), 1803 HADDR_1 (ccb_head.wlastp), 1804 HADDR_1 (ccb_head.lastp), 1805 SCR_JUMP, 1806 PADDR_B(data_io_com), 1807 #endif /* SYM_OPT_HANDLE_DIR_UNKNOWN */ 1808 1809 }/*-------------------------< ZERO >-----------------------------*/,{ 1810 SCR_DATA_ZERO, 1811 }/*-------------------------< SCRATCH >--------------------------*/,{ 1812 SCR_DATA_ZERO, /* MUST BE BEFORE SCRATCH1 */ 1813 }/*-------------------------< SCRATCH1 >-------------------------*/,{ 1814 SCR_DATA_ZERO, 1815 }/*-------------------------< PREV_DONE >------------------------*/,{ 1816 SCR_DATA_ZERO, /* MUST BE BEFORE DONE_POS ! */ 1817 }/*-------------------------< DONE_POS >-------------------------*/,{ 1818 SCR_DATA_ZERO, 1819 }/*-------------------------< NEXTJOB >--------------------------*/,{ 1820 SCR_DATA_ZERO, /* MUST BE BEFORE STARTPOS ! */ 1821 }/*-------------------------< STARTPOS >-------------------------*/,{ 1822 SCR_DATA_ZERO, 1823 }/*-------------------------< TARGTBL >--------------------------*/,{ 1824 SCR_DATA_ZERO, 1825 }/*--------------------------<>----------------------------------*/ 1826 }; 1827 1828 static struct SYM_FWZ_SCR SYM_FWZ_SCR = { 1829 /*-------------------------< SNOOPTEST >------------------------*/{ 1830 /* 1831 * Read the variable. 1832 */ 1833 SCR_COPY (4), 1834 HADDR_1 (scratch), 1835 RADDR_1 (scratcha), 1836 /* 1837 * Write the variable. 1838 */ 1839 SCR_COPY (4), 1840 RADDR_1 (temp), 1841 HADDR_1 (scratch), 1842 /* 1843 * Read back the variable. 1844 */ 1845 SCR_COPY (4), 1846 HADDR_1 (scratch), 1847 RADDR_1 (temp), 1848 }/*-------------------------< SNOOPEND >-------------------------*/,{ 1849 /* 1850 * And stop. 1851 */ 1852 SCR_INT, 1853 99, 1854 #ifdef SYM_OPT_NO_BUS_MEMORY_MAPPING 1855 /* 1856 * We may use MEMORY MOVE instructions to load the on chip-RAM, 1857 * if it happens that mapping PCI memory is not possible. 1858 * But writing the RAM from the CPU is the preferred method, 1859 * since PCI 2.2 seems to disallow PCI self-mastering. 1860 */ 1861 }/*-------------------------< START_RAM >------------------------*/,{ 1862 /* 1863 * Load the script into on-chip RAM, 1864 * and jump to start point. 1865 */ 1866 SCR_COPY (sizeof(struct SYM_FWA_SCR)), 1867 }/*-------------------------< SCRIPTA0_BA >----------------------*/,{ 1868 0, 1869 PADDR_A (start), 1870 SCR_JUMP, 1871 PADDR_A (init), 1872 #endif /* SYM_OPT_NO_BUS_MEMORY_MAPPING */ 1873 }/*--------------------------<>----------------------------------*/ 1874 }; 1875