1 #ifndef _SIM710_H 2 #define _SIM710_H 3 4 /* 5 * sim710.h - Copyright (C) 1999 Richard Hirst 6 */ 7 8 #include <linux/types.h> 9 10 int sim710_detect(Scsi_Host_Template *); 11 int sim710_command(Scsi_Cmnd *); 12 int sim710_queuecommand(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *)); 13 int sim710_abort(Scsi_Cmnd * SCpnt); 14 int sim710_bus_reset(Scsi_Cmnd * SCpnt); 15 int sim710_dev_reset(Scsi_Cmnd * SCpnt); 16 int sim710_host_reset(Scsi_Cmnd * SCpnt); 17 #ifdef MODULE 18 int sim710_release(struct Scsi_Host *); 19 #else 20 #define sim710_release NULL 21 #endif 22 23 #include <scsi/scsicam.h> 24 25 #define SIM710_SCSI { proc_name: "sim710", \ 26 name: "53c710", \ 27 detect: sim710_detect, \ 28 release: sim710_release, \ 29 queuecommand: sim710_queuecommand, \ 30 eh_abort_handler: sim710_abort, \ 31 eh_device_reset_handler: sim710_dev_reset, \ 32 eh_bus_reset_handler: sim710_bus_reset, \ 33 eh_host_reset_handler: sim710_host_reset, \ 34 bios_param: scsicam_bios_param, \ 35 can_queue: 8, \ 36 this_id: 7, \ 37 sg_tablesize: 128, \ 38 cmd_per_lun: 1, \ 39 use_clustering: DISABLE_CLUSTERING, \ 40 use_new_eh_code: 1} 41 42 #ifndef HOSTS_C 43 44 #ifdef __BIG_ENDIAN 45 #define bE 3 /* 0 for little endian, 3 for big endian */ 46 #else 47 #define bE 0 48 #endif 49 50 /* SCSI control 0 rw, default = 0xc0 */ 51 #define SCNTL0_REG (0x00^bE) 52 #define SCNTL0_ARB1 0x80 /* 0 0 = simple arbitration */ 53 #define SCNTL0_ARB2 0x40 /* 1 1 = full arbitration */ 54 #define SCNTL0_STRT 0x20 /* Start Sequence */ 55 #define SCNTL0_WATN 0x10 /* Select with ATN */ 56 #define SCNTL0_EPC 0x08 /* Enable parity checking */ 57 /* Bit 2 is reserved on 800 series chips */ 58 #define SCNTL0_EPG_700 0x04 /* Enable parity generation */ 59 #define SCNTL0_AAP 0x02 /* ATN/ on parity error */ 60 #define SCNTL0_TRG 0x01 /* Target mode */ 61 62 /* SCSI control 1 rw, default = 0x00 */ 63 64 #define SCNTL1_REG (0x01^bE) 65 #define SCNTL1_EXC 0x80 /* Extra Clock Cycle of Data setup */ 66 #define SCNTL1_ADB 0x40 /* contents of SODL on bus */ 67 #define SCNTL1_ESR_700 0x20 /* Enable SIOP response to selection 68 and reselection */ 69 #define SCNTL1_CON 0x10 /* Connected */ 70 #define SCNTL1_RST 0x08 /* SCSI RST/ */ 71 #define SCNTL1_AESP 0x04 /* Force bad parity */ 72 #define SCNTL1_SND_700 0x02 /* Start SCSI send */ 73 #define SCNTL1_IARB_800 0x02 /* Immediate Arbitration, start 74 arbitration immediately after 75 busfree is detected */ 76 #define SCNTL1_RCV_700 0x01 /* Start SCSI receive */ 77 #define SCNTL1_SST_800 0x01 /* Start SCSI transfer */ 78 79 /* SCSI control 2 rw, */ 80 81 #define SCNTL2_REG_800 (0x02^bE) 82 #define SCNTL2_800_SDU 0x80 /* SCSI disconnect unexpected */ 83 84 /* SCSI control 3 rw */ 85 86 #define SCNTL3_REG_800 (0x03^bE) 87 #define SCNTL3_800_SCF_SHIFT 4 88 #define SCNTL3_800_SCF_MASK 0x70 89 #define SCNTL3_800_SCF2 0x40 /* Synchronous divisor */ 90 #define SCNTL3_800_SCF1 0x20 /* 0x00 = SCLK/3 */ 91 #define SCNTL3_800_SCF0 0x10 /* 0x10 = SCLK/1 */ 92 /* 0x20 = SCLK/1.5 93 0x30 = SCLK/2 94 0x40 = SCLK/3 */ 95 96 #define SCNTL3_800_CCF_SHIFT 0 97 #define SCNTL3_800_CCF_MASK 0x07 98 #define SCNTL3_800_CCF2 0x04 /* 0x00 50.01 to 66 */ 99 #define SCNTL3_800_CCF1 0x02 /* 0x01 16.67 to 25 */ 100 #define SCNTL3_800_CCF0 0x01 /* 0x02 25.01 - 37.5 101 0x03 37.51 - 50 102 0x04 50.01 - 66 */ 103 104 /* 105 * SCSI destination ID rw - the appropriate bit is set for the selected 106 * target ID. This is written by the SCSI SCRIPTS processor. 107 * default = 0x00 108 */ 109 #define SDID_REG_700 (0x02^bE) 110 #define SDID_REG_800 (0x06^bE) 111 112 #define GP_REG_800 (0x07^bE) /* General purpose IO */ 113 #define GP_800_IO1 0x02 114 #define GP_800_IO2 0x01 115 116 /* SCSI interrupt enable rw, default = 0x00 */ 117 #define SIEN_REG_700 (0x03^bE) 118 #define SIEN0_REG_800 (0x40^bE) 119 #define SIEN_MA 0x80 /* Phase mismatch (ini) or ATN (tgt) */ 120 #define SIEN_FC 0x40 /* Function complete */ 121 #define SIEN_700_STO 0x20 /* Selection or reselection timeout */ 122 #define SIEN_800_SEL 0x20 /* Selected */ 123 #define SIEN_700_SEL 0x10 /* Selected or reselected */ 124 #define SIEN_800_RESEL 0x10 /* Reselected */ 125 #define SIEN_SGE 0x08 /* SCSI gross error */ 126 #define SIEN_UDC 0x04 /* Unexpected disconnect */ 127 #define SIEN_RST 0x02 /* SCSI RST/ received */ 128 #define SIEN_PAR 0x01 /* Parity error */ 129 130 /* 131 * SCSI chip ID rw 132 * NCR53c700 : 133 * When arbitrating, the highest bit is used, when reselection or selection 134 * occurs, the chip responds to all IDs for which a bit is set. 135 * default = 0x00 136 */ 137 #define SCID_REG (0x04^bE) 138 /* Bit 7 is reserved on 800 series chips */ 139 #define SCID_800_RRE 0x40 /* Enable response to reselection */ 140 #define SCID_800_SRE 0x20 /* Enable response to selection */ 141 /* Bits four and three are reserved on 800 series chips */ 142 #define SCID_800_ENC_MASK 0x07 /* Encoded SCSI ID */ 143 144 /* SCSI transfer rw, default = 0x00 */ 145 #define SXFER_REG (0x05^bE) 146 #define SXFER_DHP 0x80 /* Disable halt on parity */ 147 148 #define SXFER_TP2 0x40 /* Transfer period msb */ 149 #define SXFER_TP1 0x20 150 #define SXFER_TP0 0x10 /* lsb */ 151 #define SXFER_TP_MASK 0x70 152 /* FIXME : SXFER_TP_SHIFT == 5 is right for '8xx chips */ 153 #define SXFER_TP_SHIFT 5 154 #define SXFER_TP_4 0x00 /* Divisors */ 155 #define SXFER_TP_5 0x10<<1 156 #define SXFER_TP_6 0x20<<1 157 #define SXFER_TP_7 0x30<<1 158 #define SXFER_TP_8 0x40<<1 159 #define SXFER_TP_9 0x50<<1 160 #define SXFER_TP_10 0x60<<1 161 #define SXFER_TP_11 0x70<<1 162 163 #define SXFER_MO3 0x08 /* Max offset msb */ 164 #define SXFER_MO2 0x04 165 #define SXFER_MO1 0x02 166 #define SXFER_MO0 0x01 /* lsb */ 167 #define SXFER_MO_MASK 0x0f 168 #define SXFER_MO_SHIFT 0 169 170 /* 171 * SCSI output data latch rw 172 * The contents of this register are driven onto the SCSI bus when 173 * the Assert Data Bus bit of the SCNTL1 register is set and 174 * the CD, IO, and MSG bits of the SOCL register match the SCSI phase 175 */ 176 #define SODL_REG_700 (0x06^bE) 177 #define SODL_REG_800 (0x54^bE) 178 179 180 /* 181 * SCSI output control latch rw, default = 0 182 * Note that when the chip is being manually programmed as an initiator, 183 * the MSG, CD, and IO bits must be set correctly for the phase the target 184 * is driving the bus in. Otherwise no data transfer will occur due to 185 * phase mismatch. 186 */ 187 188 #define SOCL_REG (0x07^bE) 189 #define SOCL_REQ 0x80 /* REQ */ 190 #define SOCL_ACK 0x40 /* ACK */ 191 #define SOCL_BSY 0x20 /* BSY */ 192 #define SOCL_SEL 0x10 /* SEL */ 193 #define SOCL_ATN 0x08 /* ATN */ 194 #define SOCL_MSG 0x04 /* MSG */ 195 #define SOCL_CD 0x02 /* C/D */ 196 #define SOCL_IO 0x01 /* I/O */ 197 198 /* 199 * SCSI first byte received latch ro 200 * This register contains the first byte received during a block MOVE 201 * SCSI SCRIPTS instruction, including 202 * 203 * Initiator mode Target mode 204 * Message in Command 205 * Status Message out 206 * Data in Data out 207 * 208 * It also contains the selecting or reselecting device's ID and our 209 * ID. 210 * 211 * Note that this is the register the various IF conditionals can 212 * operate on. 213 */ 214 #define SFBR_REG (0x08^bE) 215 216 /* 217 * SCSI input data latch ro 218 * In initiator mode, data is latched into this register on the rising 219 * edge of REQ/. In target mode, data is latched on the rising edge of 220 * ACK/ 221 */ 222 #define SIDL_REG_700 (0x09^bE) 223 #define SIDL_REG_800 (0x50^bE) 224 225 /* 226 * SCSI bus data lines ro 227 * This register reflects the instantaneous status of the SCSI data 228 * lines. Note that SCNTL0 must be set to disable parity checking, 229 * otherwise reading this register will latch new parity. 230 */ 231 #define SBDL_REG_700 (0x0a^bE) 232 #define SBDL_REG_800 (0x58^bE) 233 234 #define SSID_REG_800 (0x0a^bE) 235 #define SSID_800_VAL 0x80 /* Exactly two bits asserted at sel */ 236 #define SSID_800_ENCID_MASK 0x07 /* Device which performed operation */ 237 238 239 240 /* 241 * SCSI bus control lines rw, 242 * instantaneous readout of control lines 243 */ 244 #define SBCL_REG (0x0b^bE) 245 #define SBCL_REQ 0x80 /* REQ ro */ 246 #define SBCL_ACK 0x40 /* ACK ro */ 247 #define SBCL_BSY 0x20 /* BSY ro */ 248 #define SBCL_SEL 0x10 /* SEL ro */ 249 #define SBCL_ATN 0x08 /* ATN ro */ 250 #define SBCL_MSG 0x04 /* MSG ro */ 251 #define SBCL_CD 0x02 /* C/D ro */ 252 #define SBCL_IO 0x01 /* I/O ro */ 253 #define SBCL_PHASE_CMDOUT SBCL_CD 254 #define SBCL_PHASE_DATAIN SBCL_IO 255 #define SBCL_PHASE_DATAOUT 0 256 #define SBCL_PHASE_MSGIN (SBCL_CD|SBCL_IO|SBCL_MSG) 257 #define SBCL_PHASE_MSGOUT (SBCL_CD|SBCL_MSG) 258 #define SBCL_PHASE_STATIN (SBCL_CD|SBCL_IO) 259 #define SBCL_PHASE_MASK (SBCL_CD|SBCL_IO|SBCL_MSG) 260 /* 261 * Synchronous SCSI Clock Control bits 262 * 0 - set by DCNTL 263 * 1 - SCLK / 1.0 264 * 2 - SCLK / 1.5 265 * 3 - SCLK / 2.0 266 */ 267 #define SBCL_SSCF1 0x02 /* wo, -66 only */ 268 #define SBCL_SSCF0 0x01 /* wo, -66 only */ 269 #define SBCL_SSCF_MASK 0x03 270 271 /* 272 * XXX note : when reading the DSTAT and STAT registers to clear interrupts, 273 * insure that 10 clocks elapse between the two 274 */ 275 /* DMA status ro */ 276 #define DSTAT_REG (0x0c^bE) 277 #define DSTAT_DFE 0x80 /* DMA FIFO empty */ 278 #define DSTAT_800_MDPE 0x40 /* Master Data Parity Error */ 279 #define DSTAT_BF 0x20 /* Bus Fault */ 280 #define DSTAT_ABRT 0x10 /* Aborted - set on error */ 281 #define DSTAT_SSI 0x08 /* SCRIPTS single step interrupt */ 282 #define DSTAT_SIR 0x04 /* SCRIPTS interrupt received - 283 set when INT instruction is 284 executed */ 285 #define DSTAT_WTD 0x02 /* Watchdog timeout detected */ 286 #define DSTAT_OPC 0x01 /* Illegal instruction */ 287 #define DSTAT_IID 0x01 /* Same thing, different name */ 288 289 290 #define SSTAT0_REG (0x0d^bE) /* SCSI status 0 ro */ 291 #define SIST0_REG_800 (0x42^bE) /* SCSI status 0 ro */ 292 #define SSTAT0_MA 0x80 /* ini : phase mismatch, 293 * tgt : ATN/ asserted 294 */ 295 #define SSTAT0_CMP 0x40 /* function complete */ 296 #define SSTAT0_700_STO 0x20 /* Selection or reselection timeout */ 297 #define SSTAT0_800_SEL 0x20 /* Selected */ 298 #define SSTAT0_700_SEL 0x10 /* Selected or reselected */ 299 #define SIST0_800_RSL 0x10 /* Reselected */ 300 #define SSTAT0_SGE 0x08 /* SCSI gross error */ 301 #define SSTAT0_UDC 0x04 /* Unexpected disconnect */ 302 #define SSTAT0_RST 0x02 /* SCSI RST/ received */ 303 #define SSTAT0_PAR 0x01 /* Parity error */ 304 305 #define SSTAT1_REG (0x0e^bE) /* SCSI status 1 ro */ 306 #define SSTAT1_ILF 0x80 /* SIDL full */ 307 #define SSTAT1_ORF 0x40 /* SODR full */ 308 #define SSTAT1_OLF 0x20 /* SODL full */ 309 #define SSTAT1_AIP 0x10 /* Arbitration in progress */ 310 #define SSTAT1_LOA 0x08 /* Lost arbitration */ 311 #define SSTAT1_WOA 0x04 /* Won arbitration */ 312 #define SSTAT1_RST 0x02 /* Instant readout of RST/ */ 313 #define SSTAT1_SDP 0x01 /* Instant readout of SDP/ */ 314 315 #define SSTAT2_REG (0x0f^bE) /* SCSI status 2 ro */ 316 #define SSTAT2_FF3 0x80 /* number of bytes in synchronous */ 317 #define SSTAT2_FF2 0x40 /* data FIFO */ 318 #define SSTAT2_FF1 0x20 319 #define SSTAT2_FF0 0x10 320 #define SSTAT2_FF_MASK 0xf0 321 #define SSTAT2_FF_SHIFT 4 322 323 /* 324 * Latched signals, latched on the leading edge of REQ/ for initiators, 325 * ACK/ for targets. 326 */ 327 #define SSTAT2_SDP 0x08 /* SDP */ 328 #define SSTAT2_MSG 0x04 /* MSG */ 329 #define SSTAT2_CD 0x02 /* C/D */ 330 #define SSTAT2_IO 0x01 /* I/O */ 331 #define SSTAT2_PHASE_CMDOUT SSTAT2_CD 332 #define SSTAT2_PHASE_DATAIN SSTAT2_IO 333 #define SSTAT2_PHASE_DATAOUT 0 334 #define SSTAT2_PHASE_MSGIN (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG) 335 #define SSTAT2_PHASE_MSGOUT (SSTAT2_CD|SSTAT2_MSG) 336 #define SSTAT2_PHASE_STATIN (SSTAT2_CD|SSTAT2_IO) 337 #define SSTAT2_PHASE_MASK (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG) 338 339 340 #define DSA_REG 0x10 /* DATA structure address */ 341 342 #define CTEST0_REG_700 (0x14^bE) /* Chip test 0 ro */ 343 #define CTEST0_REG_800 (0x18^bE) /* Chip test 0 ro */ 344 /* 0x80 - 0x04 are reserved */ 345 #define CTEST0_700_RTRG 0x02 /* Real target mode */ 346 #define CTEST0_700_DDIR 0x01 /* Data direction, 1 = 347 * SCSI bus to host, 0 = 348 * host to SCSI. 349 */ 350 351 #define CTEST1_REG_700 (0x15^bE) /* Chip test 1 ro */ 352 #define CTEST1_REG_800 (0x19^bE) /* Chip test 1 ro */ 353 #define CTEST1_FMT3 0x80 /* Identify which byte lanes are empty */ 354 #define CTEST1_FMT2 0x40 /* in the DMA FIFO */ 355 #define CTEST1_FMT1 0x20 356 #define CTEST1_FMT0 0x10 357 358 #define CTEST1_FFL3 0x08 /* Identify which bytes lanes are full */ 359 #define CTEST1_FFL2 0x04 /* in the DMA FIFO */ 360 #define CTEST1_FFL1 0x02 361 #define CTEST1_FFL0 0x01 362 363 #define CTEST2_REG_700 (0x16^bE) /* Chip test 2 ro */ 364 #define CTEST2_REG_800 (0x1a^bE) /* Chip test 2 ro */ 365 366 #define CTEST2_800_DDIR 0x80 /* 1 = SCSI->host */ 367 #define CTEST2_800_SIGP 0x40 /* A copy of SIGP in ISTAT. 368 Reading this register clears */ 369 #define CTEST2_800_CIO 0x20 /* Configured as IO */. 370 #define CTEST2_800_CM 0x10 /* Configured as memory */ 371 372 /* 0x80 - 0x40 are reserved on 700 series chips */ 373 #define CTEST2_700_SOFF 0x20 /* SCSI Offset Compare, 374 * As an initiator, this bit is 375 * one when the synchronous offset 376 * is zero, as a target this bit 377 * is one when the synchronous 378 * offset is at the maximum 379 * defined in SXFER 380 */ 381 #define CTEST2_700_SFP 0x10 /* SCSI FIFO parity bit, 382 * reading CTEST3 unloads a byte 383 * from the FIFO and sets this 384 */ 385 #define CTEST2_700_DFP 0x08 /* DMA FIFO parity bit, 386 * reading CTEST6 unloads a byte 387 * from the FIFO and sets this 388 */ 389 #define CTEST2_TEOP 0x04 /* SCSI true end of process, 390 * indicates a totally finished 391 * transfer 392 */ 393 #define CTEST2_DREQ 0x02 /* Data request signal */ 394 /* 0x01 is reserved on 700 series chips */ 395 #define CTEST2_800_DACK 0x01 396 397 /* 398 * Chip test 3 ro 399 * Unloads the bottom byte of the eight deep SCSI synchronous FIFO, 400 * check SSTAT2 FIFO full bits to determine size. Note that a GROSS 401 * error results if a read is attempted on this register. Also note 402 * that 16 and 32 bit reads of this register will cause corruption. 403 */ 404 #define CTEST3_REG_700 (0x17^bE) 405 /* Chip test 3 rw */ 406 #define CTEST3_REG_800 (0x1b^bE) 407 #define CTEST3_800_V3 0x80 /* Chip revision */ 408 #define CTEST3_800_V2 0x40 409 #define CTEST3_800_V1 0x20 410 #define CTEST3_800_V0 0x10 411 #define CTEST3_800_FLF 0x08 /* Flush DMA FIFO */ 412 #define CTEST3_800_CLF 0x04 /* Clear DMA FIFO */ 413 #define CTEST3_800_FM 0x02 /* Fetch mode pin */ 414 /* bit 0 is reserved on 800 series chips */ 415 416 #define CTEST4_REG_700 (0x18^bE) /* Chip test 4 rw */ 417 #define CTEST4_REG_800 (0x21^bE) /* Chip test 4 rw */ 418 /* 0x80 is reserved on 700 series chips */ 419 #define CTEST4_800_BDIS 0x80 /* Burst mode disable */ 420 #define CTEST4_ZMOD 0x40 /* High impedance mode */ 421 #define CTEST4_SZM 0x20 /* SCSI bus high impedance */ 422 #define CTEST4_700_SLBE 0x10 /* SCSI loopback enabled */ 423 #define CTEST4_800_SRTM 0x10 /* Shadow Register Test Mode */ 424 #define CTEST4_700_SFWR 0x08 /* SCSI FIFO write enable, 425 * redirects writes from SODL 426 * to the SCSI FIFO. 427 */ 428 #define CTEST4_800_MPEE 0x08 /* Enable parity checking 429 during master cycles on PCI 430 bus */ 431 432 /* 433 * These bits send the contents of the CTEST6 register to the appropriate 434 * byte lane of the 32 bit DMA FIFO. Normal operation is zero, otherwise 435 * the high bit means the low two bits select the byte lane. 436 */ 437 #define CTEST4_FBL2 0x04 438 #define CTEST4_FBL1 0x02 439 #define CTEST4_FBL0 0x01 440 #define CTEST4_FBL_MASK 0x07 441 #define CTEST4_FBL_0 0x04 /* Select DMA FIFO byte lane 0 */ 442 #define CTEST4_FBL_1 0x05 /* Select DMA FIFO byte lane 1 */ 443 #define CTEST4_FBL_2 0x06 /* Select DMA FIFO byte lane 2 */ 444 #define CTEST4_FBL_3 0x07 /* Select DMA FIFO byte lane 3 */ 445 #define CTEST4_800_SAVE (CTEST4_800_BDIS) 446 447 448 #define CTEST5_REG_700 (0x19^bE) /* Chip test 5 rw */ 449 #define CTEST5_REG_800 (0x22^bE) /* Chip test 5 rw */ 450 /* 451 * Clock Address Incrementor. When set, it increments the 452 * DNAD register to the next bus size boundary. It automatically 453 * resets itself when the operation is complete. 454 */ 455 #define CTEST5_ADCK 0x80 456 /* 457 * Clock Byte Counter. When set, it decrements the DBC register to 458 * the next bus size boundary. 459 */ 460 #define CTEST5_BBCK 0x40 461 /* 462 * Reset SCSI Offset. Setting this bit to 1 clears the current offset 463 * pointer in the SCSI synchronous offset counter (SSTAT). This bit 464 * is set to 1 if a SCSI Gross Error Condition occurs. The offset should 465 * be cleared when a synchronous transfer fails. When written, it is 466 * automatically cleared after the SCSI synchronous offset counter is 467 * reset. 468 */ 469 /* Bit 5 is reserved on 800 series chips */ 470 #define CTEST5_700_ROFF 0x20 471 /* 472 * Master Control for Set or Reset pulses. When 1, causes the low 473 * four bits of register to set when set, 0 causes the low bits to 474 * clear when set. 475 */ 476 #define CTEST5_MASR 0x10 477 #define CTEST5_DDIR 0x08 /* DMA direction */ 478 /* 479 * Bits 2-0 are reserved on 800 series chips 480 */ 481 #define CTEST5_700_EOP 0x04 /* End of process */ 482 #define CTEST5_700_DREQ 0x02 /* Data request */ 483 #define CTEST5_700_DACK 0x01 /* Data acknowledge */ 484 485 /* 486 * Chip test 6 rw - writing to this register writes to the byte 487 * lane in the DMA FIFO as determined by the FBL bits in the CTEST4 488 * register. 489 */ 490 #define CTEST6_REG_700 (0x1a^bE) 491 #define CTEST6_REG_800 (0x23^bE) 492 493 #define CTEST7_REG (0x1b^bE) /* Chip test 7 rw */ 494 #define CTEST7_10_CDIS 0x80 /* Cache burst disable */ 495 #define CTEST7_10_SC1 0x40 /* Snoop control bits */ 496 #define CTEST7_10_SC0 0x20 497 #define CTEST7_10_SC_MASK 0x60 498 #define CTEST7_STD 0x10 /* Selection timeout disable */ 499 #define CTEST7_DFP 0x08 /* DMA FIFO parity bit for CTEST6 */ 500 #define CTEST7_EVP 0x04 /* 1 = host bus even parity, 0 = odd */ 501 #define CTEST7_10_TT1 0x02 /* Transfer type */ 502 #define CTEST7_DIFF 0x01 /* Differential mode */ 503 504 #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF ) 505 506 507 #define TEMP_REG 0x1c /* through 0x1f Temporary stack rw */ 508 509 #define DFIFO_REG (0x20^bE) /* DMA FIFO rw */ 510 /* 511 * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been 512 * moved into the CTEST8 register. 513 */ 514 #define DFIFO_BO6 0x40 515 #define DFIFO_BO5 0x20 516 #define DFIFO_BO4 0x10 517 #define DFIFO_BO3 0x08 518 #define DFIFO_BO2 0x04 519 #define DFIFO_BO1 0x02 520 #define DFIFO_BO0 0x01 521 #define DFIFO_10_BO_MASK 0x7f /* 7 bit counter */ 522 523 /* 524 * Interrupt status rw 525 * Note that this is the only register which can be read while SCSI 526 * SCRIPTS are being executed. 527 */ 528 #define ISTAT_REG_700 (0x21^bE) 529 #define ISTAT_REG_800 (0x14^bE) 530 #define ISTAT_ABRT 0x80 /* Software abort, write 531 *1 to abort, wait for interrupt. */ 532 #define ISTAT_10_SRST 0x40 /* software reset */ 533 #define ISTAT_10_SIGP 0x20 /* signal script */ 534 #define ISTAT_CON 0x08 /* 1 when connected */ 535 #define ISTAT_800_INTF 0x04 /* Interrupt on the fly */ 536 #define ISTAT_700_PRE 0x04 /* Pointer register empty. 537 * Set to 1 when DSPS and DSP 538 * registers are empty in pipeline 539 * mode, always set otherwise. 540 */ 541 #define ISTAT_SIP 0x02 /* SCSI interrupt pending from 542 * SCSI portion of SIOP see 543 * SSTAT0 544 */ 545 #define ISTAT_DIP 0x01 /* DMA interrupt pending 546 * see DSTAT 547 */ 548 549 #define CTEST8_REG (0x22^bE) /* Chip test 8 rw */ 550 #define CTEST8_10_V3 0x80 /* Chip revision */ 551 #define CTEST8_10_V2 0x40 552 #define CTEST8_10_V1 0x20 553 #define CTEST8_10_V0 0x10 554 #define CTEST8_10_V_MASK 0xf0 555 #define CTEST8_10_FLF 0x08 /* Flush FIFOs */ 556 #define CTEST8_10_CLF 0x04 /* Clear FIFOs */ 557 #define CTEST8_10_FM 0x02 /* Fetch pin mode */ 558 #define CTEST8_10_SM 0x01 /* Snoop pin mode */ 559 560 561 #define LCRC_REG_10 (0x23^bE) 562 563 /* 564 * 0x24 through 0x27 are the DMA byte counter register. Instructions 565 * write their high 8 bits into the DCMD register, the low 24 bits into 566 * the DBC register. 567 * 568 * Function is dependent on the command type being executed. 569 */ 570 571 572 #define DBC_REG 0x24 573 /* 574 * For Block Move Instructions, DBC is a 24 bit quantity representing 575 * the number of bytes to transfer. 576 * For Transfer Control Instructions, DBC is bit fielded as follows : 577 */ 578 /* Bits 20 - 23 should be clear */ 579 #define DBC_TCI_TRUE (1 << 19) /* Jump when true */ 580 #define DBC_TCI_COMPARE_DATA (1 << 18) /* Compare data */ 581 #define DBC_TCI_COMPARE_PHASE (1 << 17) /* Compare phase with DCMD field */ 582 #define DBC_TCI_WAIT_FOR_VALID (1 << 16) /* Wait for REQ */ 583 /* Bits 8 - 15 are reserved on some implementations ? */ 584 #define DBC_TCI_MASK_MASK 0xff00 /* Mask for data compare */ 585 #define DBC_TCI_MASK_SHIFT 8 586 #define DBC_TCI_DATA_MASK 0xff /* Data to be compared */ 587 #define DBC_TCI_DATA_SHIFT 0 588 589 #define DBC_RWRI_IMMEDIATE_MASK 0xff00 /* Immediate data */ 590 #define DBC_RWRI_IMMEDIATE_SHIFT 8 /* Amount to shift */ 591 #define DBC_RWRI_ADDRESS_MASK 0x3f0000 /* Register address */ 592 #define DBC_RWRI_ADDRESS_SHIFT 16 593 594 595 /* 596 * DMA command r/w 597 */ 598 #define DCMD_REG (0x27^bE) 599 #define DCMD_TYPE_MASK 0xc0 /* Masks off type */ 600 #define DCMD_TYPE_BMI 0x00 /* Indicates a Block Move instruction */ 601 #define DCMD_BMI_IO 0x01 /* I/O, CD, and MSG bits selecting */ 602 #define DCMD_BMI_CD 0x02 /* the phase for the block MOVE */ 603 #define DCMD_BMI_MSG 0x04 /* instruction */ 604 605 #define DCMD_BMI_OP_MASK 0x18 /* mask for opcode */ 606 #define DCMD_BMI_OP_MOVE_T 0x00 /* MOVE */ 607 #define DCMD_BMI_OP_MOVE_I 0x08 /* MOVE Initiator */ 608 609 #define DCMD_BMI_INDIRECT 0x20 /* Indirect addressing */ 610 611 #define DCMD_TYPE_TCI 0x80 /* Indicates a Transfer Control 612 instruction */ 613 #define DCMD_TCI_IO 0x01 /* I/O, CD, and MSG bits selecting */ 614 #define DCMD_TCI_CD 0x02 /* the phase for the block MOVE */ 615 #define DCMD_TCI_MSG 0x04 /* instruction */ 616 #define DCMD_TCI_OP_MASK 0x38 /* mask for opcode */ 617 #define DCMD_TCI_OP_JUMP 0x00 /* JUMP */ 618 #define DCMD_TCI_OP_CALL 0x08 /* CALL */ 619 #define DCMD_TCI_OP_RETURN 0x10 /* RETURN */ 620 #define DCMD_TCI_OP_INT 0x18 /* INT */ 621 622 #define DCMD_TYPE_RWRI 0x40 /* Indicates I/O or register Read/Write 623 instruction */ 624 #define DCMD_RWRI_OPC_MASK 0x38 /* Opcode mask */ 625 #define DCMD_RWRI_OPC_WRITE 0x28 /* Write SFBR to register */ 626 #define DCMD_RWRI_OPC_READ 0x30 /* Read register to SFBR */ 627 #define DCMD_RWRI_OPC_MODIFY 0x38 /* Modify in place */ 628 629 #define DCMD_RWRI_OP_MASK 0x07 630 #define DCMD_RWRI_OP_MOVE 0x00 631 #define DCMD_RWRI_OP_SHL 0x01 632 #define DCMD_RWRI_OP_OR 0x02 633 #define DCMD_RWRI_OP_XOR 0x03 634 #define DCMD_RWRI_OP_AND 0x04 635 #define DCMD_RWRI_OP_SHR 0x05 636 #define DCMD_RWRI_OP_ADD 0x06 637 #define DCMD_RWRI_OP_ADDC 0x07 638 639 #define DCMD_TYPE_MMI 0xc0 /* Indicates a Memory Move instruction 640 (three words) */ 641 642 643 #define DNAD_REG 0x28 /* through 0x2b DMA next address for 644 data */ 645 #define DSP_REG 0x2c /* through 0x2f DMA SCRIPTS pointer rw */ 646 #define DSPS_REG 0x30 /* through 0x33 DMA SCRIPTS pointer 647 save rw */ 648 #define DMODE_BL1 0x80 /* Burst length bits */ 649 #define DMODE_BL0 0x40 650 #define DMODE_BL_MASK 0xc0 651 /* Burst lengths (800) */ 652 #define DMODE_BL_2 0x00 /* 2 transfer */ 653 #define DMODE_BL_4 0x40 /* 4 transfers */ 654 #define DMODE_BL_8 0x80 /* 8 transfers */ 655 #define DMODE_BL_16 0xc0 /* 16 transfers */ 656 657 #define DMODE_10_BL_1 0x00 /* 1 transfer */ 658 #define DMODE_10_BL_2 0x40 /* 2 transfers */ 659 #define DMODE_10_BL_4 0x80 /* 4 transfers */ 660 #define DMODE_10_BL_8 0xc0 /* 8 transfers */ 661 #define DMODE_10_FC2 0x20 /* Driven to FC2 pin */ 662 #define DMODE_10_FC1 0x10 /* Driven to FC1 pin */ 663 #define DMODE_710_PD 0x08 /* Program/data on FC0 pin */ 664 #define DMODE_710_UO 0x02 /* User prog. output */ 665 666 #define DMODE_MAN 0x01 /* Manual start mode, 667 * requires a 1 to be written 668 * to the start DMA bit in the DCNTL 669 * register to run scripts 670 */ 671 672 /* NCR53c800 series only */ 673 #define SCRATCHA_REG_800 0x34 /* through 0x37 Scratch A rw */ 674 /* NCR53c710 only */ 675 #define SCRATCHB_REG_10 0x34 /* through 0x37 scratch rw */ 676 677 #define DMODE_REG (0x38^bE) /* DMA mode rw, NCR53c710 and newer */ 678 #define DMODE_800_SIOM 0x20 /* Source IO = 1 */ 679 #define DMODE_800_DIOM 0x10 /* Destination IO = 1 */ 680 #define DMODE_800_ERL 0x08 /* Enable Read Line */ 681 682 #define DIEN_REG (0x39^bE) /* DMA interrupt enable rw */ 683 /* 0x80, 0x40, and 0x20 are reserved on 700-series chips */ 684 #define DIEN_800_MDPE 0x40 /* Master data parity error */ 685 #define DIEN_800_BF 0x20 /* BUS fault */ 686 #define DIEN_700_BF 0x20 /* BUS fault */ 687 #define DIEN_ABRT 0x10 /* Enable aborted interrupt */ 688 #define DIEN_SSI 0x08 /* Enable single step interrupt */ 689 #define DIEN_SIR 0x04 /* Enable SCRIPTS INT command 690 * interrupt 691 */ 692 #define DIEN_700_WTD 0x02 /* Enable watchdog timeout interrupt */ 693 #define DIEN_700_OPC 0x01 /* Enable illegal instruction 694 * interrupt 695 */ 696 #define DIEN_800_IID 0x01 /* Same meaning, different name */ 697 698 /* 699 * DMA watchdog timer rw 700 * set in 16 CLK input periods. 701 */ 702 #define DWT_REG (0x3a^bE) 703 704 /* DMA control rw */ 705 #define DCNTL_REG (0x3b^bE) 706 #define DCNTL_700_CF1 0x80 /* Clock divisor bits */ 707 #define DCNTL_700_CF0 0x40 708 #define DCNTL_700_CF_MASK 0xc0 709 /* Clock divisors Divisor SCLK range (MHZ) */ 710 #define DCNTL_700_CF_2 0x00 /* 2.0 37.51-50.00 */ 711 #define DCNTL_700_CF_1_5 0x40 /* 1.5 25.01-37.50 */ 712 #define DCNTL_700_CF_1 0x80 /* 1.0 16.67-25.00 */ 713 #define DCNTL_700_CF_3 0xc0 /* 3.0 50.01-66.67 (53c700-66) */ 714 715 #define DCNTL_700_S16 0x20 /* Load scripts 16 bits at a time */ 716 #define DCNTL_SSM 0x10 /* Single step mode */ 717 #define DCNTL_700_LLM 0x08 /* Low level mode, can only be set 718 * after selection */ 719 #define DCNTL_800_IRQM 0x08 /* Totem pole IRQ pin */ 720 #define DCNTL_STD 0x04 /* Start DMA / SCRIPTS */ 721 /* 0x02 is reserved */ 722 #define DCNTL_10_COM 0x01 /* 700 software compatibility mode */ 723 #define DCNTL_10_EA 0x20 /* Enable Ack - needed for MVME16x */ 724 725 #define SCRATCHB_REG_800 0x5c /* through 0x5f scratch b rw */ 726 /* NCR53c710 only */ 727 #define ADDER_REG_10 0x3c /* Adder, NCR53c710 only */ 728 729 #define SIEN1_REG_800 (0x41^bE) 730 #define SIEN1_800_STO 0x04 /* selection/reselection timeout */ 731 #define SIEN1_800_GEN 0x02 /* general purpose timer */ 732 #define SIEN1_800_HTH 0x01 /* handshake to handshake */ 733 734 #define SIST1_REG_800 (0x43^bE) 735 #define SIST1_800_STO 0x04 /* selection/reselection timeout */ 736 #define SIST1_800_GEN 0x02 /* general purpose timer */ 737 #define SIST1_800_HTH 0x01 /* handshake to handshake */ 738 739 #define SLPAR_REG_800 (0x44^bE) /* Parity */ 740 741 #define MACNTL_REG_800 (0x46^bE) /* Memory access control */ 742 #define MACNTL_800_TYP3 0x80 743 #define MACNTL_800_TYP2 0x40 744 #define MACNTL_800_TYP1 0x20 745 #define MACNTL_800_TYP0 0x10 746 #define MACNTL_800_DWR 0x08 747 #define MACNTL_800_DRD 0x04 748 #define MACNTL_800_PSCPT 0x02 749 #define MACNTL_800_SCPTS 0x01 750 751 #define GPCNTL_REG_800 (0x47^bE) /* General Purpose Pin Control */ 752 753 /* Timeouts are expressed such that 0=off, 1=100us, doubling after that */ 754 #define STIME0_REG_800 (0x48^bE) /* SCSI Timer Register 0 */ 755 #define STIME0_800_HTH_MASK 0xf0 /* Handshake to Handshake timeout */ 756 #define STIME0_800_HTH_SHIFT 4 757 #define STIME0_800_SEL_MASK 0x0f /* Selection timeout */ 758 #define STIME0_800_SEL_SHIFT 0 759 760 #define STIME1_REG_800 (0x49^bE) 761 #define STIME1_800_GEN_MASK 0x0f /* General purpose timer */ 762 763 #define RESPID_REG_800 (0x4a^bE) /* Response ID, bit fielded. 8 764 bits on narrow chips, 16 on WIDE */ 765 766 #define STEST0_REG_800 (0x4c^bE) 767 #define STEST0_800_SLT 0x08 /* Selection response logic test */ 768 #define STEST0_800_ART 0x04 /* Arbitration priority encoder test */ 769 #define STEST0_800_SOZ 0x02 /* Synchronous offset zero */ 770 #define STEST0_800_SOM 0x01 /* Synchronous offset maximum */ 771 772 #define STEST1_REG_800 (0x4d^bE) 773 #define STEST1_800_SCLK 0x80 /* Disable SCSI clock */ 774 775 #define STEST2_REG_800 (0x4e^bE) 776 #define STEST2_800_SCE 0x80 /* Enable SOCL/SODL */ 777 #define STEST2_800_ROF 0x40 /* Reset SCSI sync offset */ 778 #define STEST2_800_SLB 0x10 /* Enable SCSI loopback mode */ 779 #define STEST2_800_SZM 0x08 /* SCSI high impedance mode */ 780 #define STEST2_800_EXT 0x02 /* Extend REQ/ACK filter 30 to 60ns */ 781 #define STEST2_800_LOW 0x01 /* SCSI low level mode */ 782 783 #define STEST3_REG_800 (0x4f^bE) 784 #define STEST3_800_TE 0x80 /* Enable active negation */ 785 #define STEST3_800_STR 0x40 /* SCSI FIFO test read */ 786 #define STEST3_800_HSC 0x20 /* Halt SCSI clock */ 787 #define STEST3_800_DSI 0x10 /* Disable single initiator response */ 788 #define STEST3_800_TTM 0x04 /* Time test mode */ 789 #define STEST3_800_CSF 0x02 /* Clear SCSI FIFO */ 790 #define STEST3_800_STW 0x01 /* SCSI FIFO test write */ 791 792 #define ISTAT_REG ISTAT_REG_700 793 #define SCRATCH_REG SCRATCHB_REG_10 794 #define ADDER_REG ADDER_REG_10 795 #define SIEN_REG SIEN_REG_700 796 #define SDID_REG SDID_REG_700 797 #define CTEST0_REG CTEST0_REG_700 798 #define CTEST1_REG CTEST1_REG_700 799 #define CTEST2_REG CTEST2_REG_700 800 #define CTEST3_REG CTEST3_REG_700 801 #define CTEST4_REG CTEST4_REG_700 802 #define CTEST5_REG CTEST5_REG_700 803 #define CTEST6_REG CTEST6_REG_700 804 #define SODL_REG SODL_REG_700 805 #define SBDL_REG SBDL_REG_700 806 #define SIDL_REG SIDL_REG_700 807 #define LCRC_REG LCRC_REG_10 808 809 #ifdef MEM_MAPPED 810 #define NCR_read8(address) \ 811 (unsigned int)readb((u32)(host->base) + ((u32)(address))) 812 813 #define NCR_read32(address) \ 814 (unsigned int) readl((u32)(host->base) + (u32)(address)) 815 816 #define NCR_write8(address,value) \ 817 { DEB(DEB_REGS, printk("NCR: %02x => %08x\n", (u32)(value), ((u32)(host->base) + (u32)(address)))); \ 818 *(volatile unsigned char *) \ 819 ((u32)(host->base) + (u32)(address)) = (value); } 820 821 #define NCR_write32(address,value) \ 822 { DEB(DEB_REGS, printk("NCR: %08x => %08x\n", (u32)(value), ((u32)(host->base) + (u32)(address)))); \ 823 *(volatile unsigned long *) \ 824 ((u32)(host->base) + (u32)(address)) = (value); } 825 #else 826 #define NCR_read8(address) \ 827 inb((u32)(host->base) + (address)) 828 829 #define NCR_read32(address) \ 830 inl((u32)(host->base) + (address)) 831 832 #define NCR_write8(address,value) \ 833 { DEB(DEB_REGS, printk("NCR: %02x => %08x\n", (u32)(value), ((u32)(host->base) + (u32)(address)))); \ 834 outb((value), (u32)(host->base) + (u32)(address)); } 835 836 #define NCR_write32(address,value) \ 837 { DEB(DEB_REGS, printk("NCR: %08x => %08x\n", (u32)(value), ((u32)(host->base) + (u32)(address)))); \ 838 outl((value), (u32)(host->base) + (u32)(address)); } 839 #endif 840 841 /* Patch arbitrary 32 bit words in the script */ 842 #define patch_abs_32(script, offset, symbol, value) \ 843 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \ 844 (u32)); ++i) { \ 845 (script)[A_##symbol##_used[i] - (offset)] += (value); \ 846 DEB(DEB_FIXUP, printk("scsi%d: %s reference %d at 0x%x in %s is now 0x%x\n",\ 847 host->host_no, #symbol, i, A_##symbol##_used[i] - \ 848 (int)(offset), #script, (script)[A_##symbol##_used[i] - \ 849 (offset)])); \ 850 } 851 852 #endif 853 #endif 854