1 /*****************************************************************************/
2 /* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3 /* */
4 /* Written By: Keith Mitchell, IBM Corporation */
5 /* Jack Hammer, Adaptec, Inc. */
6 /* David Jeffery, Adaptec, Inc. */
7 /* */
8 /* Copyright (C) 2000 IBM Corporation */
9 /* Copyright (C) 2002,2003 Adaptec, Inc. */
10 /* */
11 /* This program is free software; you can redistribute it and/or modify */
12 /* it under the terms of the GNU General Public License as published by */
13 /* the Free Software Foundation; either version 2 of the License, or */
14 /* (at your option) any later version. */
15 /* */
16 /* This program is distributed in the hope that it will be useful, */
17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19 /* GNU General Public License for more details. */
20 /* */
21 /* NO WARRANTY */
22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26 /* solely responsible for determining the appropriateness of using and */
27 /* distributing the Program and assumes all risks associated with its */
28 /* exercise of rights under this Agreement, including but not limited to */
29 /* the risks and costs of program errors, damage to or loss of data, */
30 /* programs or equipment, and unavailability or interruption of operations. */
31 /* */
32 /* DISCLAIMER OF LIABILITY */
33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40 /* */
41 /* You should have received a copy of the GNU General Public License */
42 /* along with this program; if not, write to the Free Software */
43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44 /* */
45 /* Bugs/Comments/Suggestions about this driver should be mailed to: */
46 /* ipslinux@adaptec.com */
47 /* */
48 /* For system support issues, contact your local IBM Customer support. */
49 /* Directions to find IBM Customer Support for each country can be found at: */
50 /* http://www.ibm.com/planetwide/ */
51 /* */
52 /*****************************************************************************/
53
54 /*****************************************************************************/
55 /* Change Log */
56 /* */
57 /* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58 /* 0.99.03 - Make interrupt routine handle all completed request on the */
59 /* adapter not just the first one */
60 /* - Make sure passthru commands get woken up if we run out of */
61 /* SCBs */
62 /* - Send all of the commands on the queue at once rather than */
63 /* one at a time since the card will support it. */
64 /* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65 /* the interface to the utilities to change */
66 /* - Fix error recovery code */
67 /* 0.99.05 - Fix an oops when we get certain passthru commands */
68 /* 1.00.00 - Initial Public Release */
69 /* Functionally equivalent to 0.99.05 */
70 /* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71 /* - Change version to 3.60 to coincide with release numbering. */
72 /* 3.60.01 - Remove bogus error check in passthru routine */
73 /* 3.60.02 - Make DCDB direction based on lookup table */
74 /* - Only allow one DCDB command to a SCSI ID at a time */
75 /* 4.00.00 - Add support for ServeRAID 4 */
76 /* 4.00.01 - Add support for First Failure Data Capture */
77 /* 4.00.02 - Fix problem with PT DCDB with no buffer */
78 /* 4.00.03 - Add alternative passthru interface */
79 /* - Add ability to flash BIOS */
80 /* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81 /* 4.00.05 - Remove wish_block from init routine */
82 /* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83 /* 2.3.18 and later */
84 /* - Sync with other changes from the 2.3 kernels */
85 /* 4.00.06 - Fix timeout with initial FFDC command */
86 /* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87 /* 4.10.00 - Add support for ServeRAID 4M/4L */
88 /* 4.10.13 - Fix for dynamic unload and proc file system */
89 /* 4.20.03 - Rename version to coincide with new release schedules */
90 /* Performance fixes */
91 /* Fix truncation of /proc files with cat */
92 /* Merge in changes through kernel 2.4.0test1ac21 */
93 /* 4.20.13 - Fix some failure cases / reset code */
94 /* - Hook into the reboot_notifier to flush the controller cache */
95 /* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96 /* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97 /* - Add IPSSEND Flash Support */
98 /* - Set Sense Data for Unknown SCSI Command */
99 /* - Use Slot Number from NVRAM Page 5 */
100 /* - Restore caller's DCDB Structure */
101 /* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102 /* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103 /* - Don't release HA Lock in ips_next() until SC taken off queue */
104 /* - Unregister SCSI device in ips_release() */
105 /* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106 /* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107 /* Code Clean-Up for 2.4.x kernel */
108 /* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109 /* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110 /* - Don't Issue Internal FFDC Command if there are Active Commands */
111 /* - Close Window for getting too many IOCTL's active */
112 /* 4.80.00 - Make ia64 Safe */
113 /* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114 /* - Adjustments to Device Queue Depth */
115 /* 4.80.14 - Take all semaphores off stack */
116 /* - Clean Up New_IOCTL path */
117 /* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118 /* - 5 second delay needed after resetting an i960 adapter */
119 /* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120 /* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121 /* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122 /* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123 /* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124 /* 4.90.11 - Don't actually RESET unless it's physically required */
125 /* - Remove unused compile options */
126 /* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127 /* - Get rid on IOCTL_NEW_COMMAND code */
128 /* - Add Extended DCDB Commands for Tape Support in 5I */
129 /* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130 /* 5.10.15 - remove unused code (sem, macros, etc.) */
131 /* 5.30.00 - use __devexit_p() */
132 /* 6.00.00 - Add 6x Adapters and Battery Flash */
133 /* 6.10.00 - Remove 1G Addressing Limitations */
134 /* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135 /* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136 /* 7.10.xx - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137 /* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138 /* - Fix sort order of 7k */
139 /* - Remove 3 unused "inline" functions */
140 /*****************************************************************************/
141
142 /*
143 * Conditional Compilation directives for this driver:
144 *
145 * IPS_DEBUG - Turn on debugging info
146 *
147 * Parameters:
148 *
149 * debug:<number> - Set debug level to <number>
150 * NOTE: only works when IPS_DEBUG compile directive is used.
151 * 1 - Normal debug messages
152 * 2 - Verbose debug messages
153 * 11 - Method trace (non interrupt)
154 * 12 - Method trace (includes interrupt)
155 *
156 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
157 * nommap - Don't use memory mapped I/O
158 * ioctlsize - Initial size of the IOCTL buffer
159 */
160
161 #include <asm/io.h>
162 #include <asm/byteorder.h>
163 #include <asm/page.h>
164 #include <linux/stddef.h>
165 #include <linux/version.h>
166 #include <linux/string.h>
167 #include <linux/errno.h>
168 #include <linux/kernel.h>
169 #include <linux/ioport.h>
170 #include <linux/slab.h>
171 #include <linux/delay.h>
172 #include <linux/pci.h>
173 #include <linux/proc_fs.h>
174 #include <linux/reboot.h>
175 #include <linux/interrupt.h>
176
177 #include <linux/blkdev.h>
178 #include <linux/types.h>
179
180 #include <scsi/sg.h>
181
182 #include "scsi.h"
183
184 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0)
185 #include "hosts.h"
186 #else
187 #include <scsi/scsi_host.h>
188 #endif
189
190 #include "ips.h"
191
192 #include <linux/module.h>
193
194 #include <linux/stat.h>
195 #include <linux/config.h>
196
197 #include <linux/spinlock.h>
198 #include <linux/init.h>
199
200 #include <linux/smp.h>
201
202 #ifdef MODULE
203 static char *ips = NULL;
204 MODULE_PARM(ips, "s");
205 #endif
206
207 /*
208 * DRIVER_VER
209 */
210 #define IPS_VERSION_HIGH "7.10"
211 #define IPS_VERSION_LOW ".18 "
212
213 #if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
214 #warning "This driver has only been tested on the x86/ia64/x86_64 platforms"
215 #endif
216
217 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0)
218 #include <linux/blk.h>
219 #include "sd.h"
220 #define IPS_SG_ADDRESS(sg) ((sg)->address)
221 #define IPS_LOCK_SAVE(lock,flags) spin_lock_irqsave(&io_request_lock,flags)
222 #define IPS_UNLOCK_RESTORE(lock,flags) spin_unlock_irqrestore(&io_request_lock,flags)
223 #ifndef __devexit_p
224 #define __devexit_p(x) x
225 #endif
226 #else
227 #define IPS_SG_ADDRESS(sg) (page_address((sg)->page) ? \
228 page_address((sg)->page)+(sg)->offset : 0)
229 #define IPS_LOCK_SAVE(lock,flags) do{spin_lock(lock);(void)flags;}while(0)
230 #define IPS_UNLOCK_RESTORE(lock,flags) do{spin_unlock(lock);(void)flags;}while(0)
231 #endif
232
233 #define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
234 SCSI_DATA_NONE == scb->scsi_cmd->sc_data_direction) ? \
235 PCI_DMA_BIDIRECTIONAL : \
236 scsi_to_pci_dma_dir(scb->scsi_cmd->sc_data_direction))
237
238 #ifdef IPS_DEBUG
239 #define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
240 #define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
241 #define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
242 #else
243 #define METHOD_TRACE(s, i)
244 #define DEBUG(i, s)
245 #define DEBUG_VAR(i, s, v...)
246 #endif
247
248 /*
249 * global variables
250 */
251 static const char ips_name[] = "ips";
252 static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
253 static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
254 static unsigned int ips_next_controller;
255 static unsigned int ips_num_controllers;
256 static unsigned int ips_released_controllers;
257 static int ips_hotplug;
258 static int ips_cmd_timeout = 60;
259 static int ips_reset_timeout = 60 * 5;
260 static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
261 static int ips_force_i2o = 1; /* Always use I2O command delivery */
262 static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
263 static int ips_cd_boot; /* Booting from Manager CD */
264 static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
265 static dma_addr_t ips_flashbusaddr;
266 static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
267 static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
268 static Scsi_Host_Template ips_driver_template = {
269 .detect = ips_detect,
270 .release = ips_release,
271 .info = ips_info,
272 .queuecommand = ips_queue,
273 .eh_abort_handler = ips_eh_abort,
274 .eh_host_reset_handler = ips_eh_reset,
275 .proc_name = "ips",
276 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
277 .proc_info = ips_proc_info,
278 .slave_configure = ips_slave_configure,
279 #else
280 .proc_info = ips_proc24_info,
281 .select_queue_depths = ips_select_queue_depth,
282 #endif
283 .bios_param = ips_biosparam,
284 .this_id = -1,
285 .sg_tablesize = IPS_MAX_SG,
286 .cmd_per_lun = 3,
287 .use_clustering = ENABLE_CLUSTERING,
288 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
289 .use_new_eh_code = 1,
290 #endif
291 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
292 .highmem_io = 1,
293 #endif
294 };
295
296 IPS_DEFINE_COMPAT_TABLE( Compatable ); /* Version Compatability Table */
297
298
299 /* This table describes all ServeRAID Adapters */
300 static struct pci_device_id ips_pci_table[] = {
301 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
302 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
303 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
304 { 0, }
305 };
306
307 MODULE_DEVICE_TABLE( pci, ips_pci_table );
308
309 static char ips_hot_plug_name[] = "ips";
310
311 static int __devinit ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
312 static void __devexit ips_remove_device(struct pci_dev *pci_dev);
313
314 struct pci_driver ips_pci_driver = {
315 .name = ips_hot_plug_name,
316 .id_table = ips_pci_table,
317 .probe = ips_insert_device,
318 .remove = __devexit_p(ips_remove_device),
319 };
320
321
322 /*
323 * Necessary forward function protoypes
324 */
325 static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
326
327 #define MAX_ADAPTER_NAME 15
328
329 static char ips_adapter_name[][30] = {
330 "ServeRAID",
331 "ServeRAID II",
332 "ServeRAID on motherboard",
333 "ServeRAID on motherboard",
334 "ServeRAID 3H",
335 "ServeRAID 3L",
336 "ServeRAID 4H",
337 "ServeRAID 4M",
338 "ServeRAID 4L",
339 "ServeRAID 4Mx",
340 "ServeRAID 4Lx",
341 "ServeRAID 5i",
342 "ServeRAID 5i",
343 "ServeRAID 6M",
344 "ServeRAID 6i",
345 "ServeRAID 7t",
346 "ServeRAID 7k",
347 "ServeRAID 7M"
348 };
349
350 static struct notifier_block ips_notifier = {
351 ips_halt, NULL, 0
352 };
353
354 /*
355 * Direction table
356 */
357 static char ips_command_direction[] = {
358 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
359 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
360 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
361 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
362 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
363 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
364 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
365 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
366 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
367 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
368 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
369 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
370 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
371 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
372 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
373 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
374 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
375 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
376 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
377 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
378 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
379 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
380 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
381 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
382 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
383 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
384 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
385 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
386 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
387 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
388 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
389 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
390 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
391 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
392 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
393 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
394 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
395 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
396 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
397 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
398 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
399 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
400 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
401 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
402 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
403 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
404 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
405 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
406 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
407 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
408 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
409 };
410
411 /*
412 * Function prototypes
413 */
414 int ips_detect(Scsi_Host_Template *);
415 int ips_release(struct Scsi_Host *);
416 int ips_eh_abort(Scsi_Cmnd *);
417 int ips_eh_reset(Scsi_Cmnd *);
418 int ips_queue(Scsi_Cmnd *, void (*)(Scsi_Cmnd *));
419 const char *ips_info(struct Scsi_Host *);
420 irqreturn_t do_ipsintr(int, void *, struct pt_regs *);
421 static int ips_hainit(ips_ha_t *);
422 static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
423 static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
424 static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
425 static int ips_online(ips_ha_t *, ips_scb_t *);
426 static int ips_inquiry(ips_ha_t *, ips_scb_t *);
427 static int ips_rdcap(ips_ha_t *, ips_scb_t *);
428 static int ips_msense(ips_ha_t *, ips_scb_t *);
429 static int ips_reqsen(ips_ha_t *, ips_scb_t *);
430 static int ips_deallocatescbs(ips_ha_t *, int);
431 static int ips_allocatescbs(ips_ha_t *);
432 static int ips_reset_copperhead(ips_ha_t *);
433 static int ips_reset_copperhead_memio(ips_ha_t *);
434 static int ips_reset_morpheus(ips_ha_t *);
435 static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
436 static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
437 static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
438 static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
439 static int ips_isintr_copperhead(ips_ha_t *);
440 static int ips_isintr_copperhead_memio(ips_ha_t *);
441 static int ips_isintr_morpheus(ips_ha_t *);
442 static int ips_wait(ips_ha_t *, int, int);
443 static int ips_write_driver_status(ips_ha_t *, int);
444 static int ips_read_adapter_status(ips_ha_t *, int);
445 static int ips_read_subsystem_parameters(ips_ha_t *, int);
446 static int ips_read_config(ips_ha_t *, int);
447 static int ips_clear_adapter(ips_ha_t *, int);
448 static int ips_readwrite_page5(ips_ha_t *, int, int);
449 static int ips_init_copperhead(ips_ha_t *);
450 static int ips_init_copperhead_memio(ips_ha_t *);
451 static int ips_init_morpheus(ips_ha_t *);
452 static int ips_isinit_copperhead(ips_ha_t *);
453 static int ips_isinit_copperhead_memio(ips_ha_t *);
454 static int ips_isinit_morpheus(ips_ha_t *);
455 static int ips_erase_bios(ips_ha_t *);
456 static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
457 static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
458 static int ips_erase_bios_memio(ips_ha_t *);
459 static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
460 static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
461 static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
462 static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
463 static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
464 static void ips_free_flash_copperhead(ips_ha_t * ha);
465 static void ips_get_bios_version(ips_ha_t *, int);
466 static void ips_identify_controller(ips_ha_t *);
467 static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
468 static void ips_enable_int_copperhead(ips_ha_t *);
469 static void ips_enable_int_copperhead_memio(ips_ha_t *);
470 static void ips_enable_int_morpheus(ips_ha_t *);
471 static int ips_intr_copperhead(ips_ha_t *);
472 static int ips_intr_morpheus(ips_ha_t *);
473 static void ips_next(ips_ha_t *, int);
474 static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
475 static void ipsintr_done(ips_ha_t *, struct ips_scb *);
476 static void ips_done(ips_ha_t *, ips_scb_t *);
477 static void ips_free(ips_ha_t *);
478 static void ips_init_scb(ips_ha_t *, ips_scb_t *);
479 static void ips_freescb(ips_ha_t *, ips_scb_t *);
480 static void ips_setup_funclist(ips_ha_t *);
481 static void ips_statinit(ips_ha_t *);
482 static void ips_statinit_memio(ips_ha_t *);
483 static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
484 static void ips_ffdc_reset(ips_ha_t *, int);
485 static void ips_ffdc_time(ips_ha_t *);
486 static uint32_t ips_statupd_copperhead(ips_ha_t *);
487 static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
488 static uint32_t ips_statupd_morpheus(ips_ha_t *);
489 static ips_scb_t *ips_getscb(ips_ha_t *);
490 static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
491 static void ips_putq_wait_tail(ips_wait_queue_t *, Scsi_Cmnd *);
492 static void ips_putq_copp_tail(ips_copp_queue_t *,
493 ips_copp_wait_item_t *);
494 static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
495 static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
496 static Scsi_Cmnd *ips_removeq_wait_head(ips_wait_queue_t *);
497 static Scsi_Cmnd *ips_removeq_wait(ips_wait_queue_t *, Scsi_Cmnd *);
498 static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
499 ips_copp_wait_item_t *);
500 static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
501
502 static int ips_is_passthru(Scsi_Cmnd *);
503 static int ips_make_passthru(ips_ha_t *, Scsi_Cmnd *, ips_scb_t *, int);
504 static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
505 static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
506 static void ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data,
507 unsigned int count);
508 static void ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned int count);
509
510 int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
511 static int ips_host_info(ips_ha_t *, char *, off_t, int);
512 static void copy_mem_info(IPS_INFOSTR *, char *, int);
513 static int copy_info(IPS_INFOSTR *, char *, ...);
514 static int ips_get_version_info(ips_ha_t * ha, dma_addr_t, int intr);
515 static void ips_version_check(ips_ha_t * ha, int intr);
516 static int ips_abort_init(ips_ha_t * ha, int index);
517 static int ips_init_phase2(int index);
518
519 static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
520 static int ips_register_scsi(int index);
521 /*--------------------------------------------------------------------------*/
522 /* Exported Functions */
523 /*--------------------------------------------------------------------------*/
524
525 /****************************************************************************/
526 /* */
527 /* Routine Name: ips_setup */
528 /* */
529 /* Routine Description: */
530 /* */
531 /* setup parameters to the driver */
532 /* */
533 /****************************************************************************/
534 static int
ips_setup(char * ips_str)535 ips_setup(char *ips_str)
536 {
537
538 int i;
539 char *key;
540 char *value;
541 IPS_OPTION options[] = {
542 {"noi2o", &ips_force_i2o, 0},
543 {"nommap", &ips_force_memio, 0},
544 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
545 {"cdboot", &ips_cd_boot, 0},
546 {"maxcmds", &MaxLiteCmds, 32},
547 };
548
549 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
550 /* Search for value */
551 while ((key = strsep(&ips_str, ",."))) {
552 if (!*key)
553 continue;
554 value = strchr(key, ':');
555 if (value)
556 *value++ = '\0';
557 /*
558 * We now have key/value pairs.
559 * Update the variables
560 */
561 for (i = 0; i < (sizeof (options) / sizeof (options[0])); i++) {
562 if (strnicmp
563 (key, options[i].option_name,
564 strlen(options[i].option_name)) == 0) {
565 if (value)
566 *options[i].option_flag =
567 simple_strtoul(value, NULL, 0);
568 else
569 *options[i].option_flag =
570 options[i].option_value;
571 break;
572 }
573 }
574 }
575
576 return (1);
577 }
578
579 __setup("ips=", ips_setup);
580
581 /****************************************************************************/
582 /* */
583 /* Routine Name: ips_detect */
584 /* */
585 /* Routine Description: */
586 /* */
587 /* Detect and initialize the driver */
588 /* */
589 /* NOTE: this routine is called under the io_request_lock spinlock */
590 /* */
591 /****************************************************************************/
592 int
ips_detect(Scsi_Host_Template * SHT)593 ips_detect(Scsi_Host_Template * SHT)
594 {
595 int i;
596
597 METHOD_TRACE("ips_detect", 1);
598
599 #ifdef MODULE
600 if (ips)
601 ips_setup(ips);
602 #endif
603
604 for (i = 0; i < ips_num_controllers; i++) {
605 if (ips_register_scsi(i))
606 ips_free(ips_ha[i]);
607 ips_released_controllers++;
608 }
609 ips_hotplug = 1;
610 return (ips_num_controllers);
611 }
612
613 /****************************************************************************/
614 /* configure the function pointers to use the functions that will work */
615 /* with the found version of the adapter */
616 /****************************************************************************/
617 static void
ips_setup_funclist(ips_ha_t * ha)618 ips_setup_funclist(ips_ha_t * ha)
619 {
620
621 /*
622 * Setup Functions
623 */
624 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
625 /* morpheus / marco / sebring */
626 ha->func.isintr = ips_isintr_morpheus;
627 ha->func.isinit = ips_isinit_morpheus;
628 ha->func.issue = ips_issue_i2o_memio;
629 ha->func.init = ips_init_morpheus;
630 ha->func.statupd = ips_statupd_morpheus;
631 ha->func.reset = ips_reset_morpheus;
632 ha->func.intr = ips_intr_morpheus;
633 ha->func.enableint = ips_enable_int_morpheus;
634 } else if (IPS_USE_MEMIO(ha)) {
635 /* copperhead w/MEMIO */
636 ha->func.isintr = ips_isintr_copperhead_memio;
637 ha->func.isinit = ips_isinit_copperhead_memio;
638 ha->func.init = ips_init_copperhead_memio;
639 ha->func.statupd = ips_statupd_copperhead_memio;
640 ha->func.statinit = ips_statinit_memio;
641 ha->func.reset = ips_reset_copperhead_memio;
642 ha->func.intr = ips_intr_copperhead;
643 ha->func.erasebios = ips_erase_bios_memio;
644 ha->func.programbios = ips_program_bios_memio;
645 ha->func.verifybios = ips_verify_bios_memio;
646 ha->func.enableint = ips_enable_int_copperhead_memio;
647 if (IPS_USE_I2O_DELIVER(ha))
648 ha->func.issue = ips_issue_i2o_memio;
649 else
650 ha->func.issue = ips_issue_copperhead_memio;
651 } else {
652 /* copperhead */
653 ha->func.isintr = ips_isintr_copperhead;
654 ha->func.isinit = ips_isinit_copperhead;
655 ha->func.init = ips_init_copperhead;
656 ha->func.statupd = ips_statupd_copperhead;
657 ha->func.statinit = ips_statinit;
658 ha->func.reset = ips_reset_copperhead;
659 ha->func.intr = ips_intr_copperhead;
660 ha->func.erasebios = ips_erase_bios;
661 ha->func.programbios = ips_program_bios;
662 ha->func.verifybios = ips_verify_bios;
663 ha->func.enableint = ips_enable_int_copperhead;
664
665 if (IPS_USE_I2O_DELIVER(ha))
666 ha->func.issue = ips_issue_i2o;
667 else
668 ha->func.issue = ips_issue_copperhead;
669 }
670 }
671
672 /****************************************************************************/
673 /* */
674 /* Routine Name: ips_release */
675 /* */
676 /* Routine Description: */
677 /* */
678 /* Remove a driver */
679 /* */
680 /****************************************************************************/
681 int
ips_release(struct Scsi_Host * sh)682 ips_release(struct Scsi_Host *sh)
683 {
684 ips_scb_t *scb;
685 ips_ha_t *ha;
686 int i;
687
688 METHOD_TRACE("ips_release", 1);
689
690 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
691
692 if (i == IPS_MAX_ADAPTERS) {
693 printk(KERN_WARNING
694 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
695 BUG();
696 return (FALSE);
697 }
698
699 ha = IPS_HA(sh);
700
701 if (!ha)
702 return (FALSE);
703
704 /* flush the cache on the controller */
705 scb = &ha->scbs[ha->max_cmds - 1];
706
707 ips_init_scb(ha, scb);
708
709 scb->timeout = ips_cmd_timeout;
710 scb->cdb[0] = IPS_CMD_FLUSH;
711
712 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
713 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
714 scb->cmd.flush_cache.state = IPS_NORM_STATE;
715 scb->cmd.flush_cache.reserved = 0;
716 scb->cmd.flush_cache.reserved2 = 0;
717 scb->cmd.flush_cache.reserved3 = 0;
718 scb->cmd.flush_cache.reserved4 = 0;
719
720 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
721
722 /* send command */
723 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
724 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
725
726 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
727
728 ips_sh[i] = NULL;
729 ips_ha[i] = NULL;
730
731 /* free extra memory */
732 ips_free(ha);
733
734 /* Free I/O Region */
735 if (ha->io_addr)
736 release_region(ha->io_addr, ha->io_len);
737
738 /* free IRQ */
739 free_irq(ha->irq, ha);
740
741 IPS_REMOVE_HOST(sh);
742 scsi_host_put(sh);
743
744 ips_released_controllers++;
745
746 return (FALSE);
747 }
748
749 /****************************************************************************/
750 /* */
751 /* Routine Name: ips_halt */
752 /* */
753 /* Routine Description: */
754 /* */
755 /* Perform cleanup when the system reboots */
756 /* */
757 /****************************************************************************/
758 static int
ips_halt(struct notifier_block * nb,ulong event,void * buf)759 ips_halt(struct notifier_block *nb, ulong event, void *buf)
760 {
761 ips_scb_t *scb;
762 ips_ha_t *ha;
763 int i;
764
765 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
766 (event != SYS_POWER_OFF))
767 return (NOTIFY_DONE);
768
769 for (i = 0; i < ips_next_controller; i++) {
770 ha = (ips_ha_t *) ips_ha[i];
771
772 if (!ha)
773 continue;
774
775 if (!ha->active)
776 continue;
777
778 /* flush the cache on the controller */
779 scb = &ha->scbs[ha->max_cmds - 1];
780
781 ips_init_scb(ha, scb);
782
783 scb->timeout = ips_cmd_timeout;
784 scb->cdb[0] = IPS_CMD_FLUSH;
785
786 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
787 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
788 scb->cmd.flush_cache.state = IPS_NORM_STATE;
789 scb->cmd.flush_cache.reserved = 0;
790 scb->cmd.flush_cache.reserved2 = 0;
791 scb->cmd.flush_cache.reserved3 = 0;
792 scb->cmd.flush_cache.reserved4 = 0;
793
794 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
795
796 /* send command */
797 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
798 IPS_FAILURE)
799 IPS_PRINTK(KERN_WARNING, ha->pcidev,
800 "Incomplete Flush.\n");
801 else
802 IPS_PRINTK(KERN_WARNING, ha->pcidev,
803 "Flushing Complete.\n");
804 }
805
806 return (NOTIFY_OK);
807 }
808
809 /****************************************************************************/
810 /* */
811 /* Routine Name: ips_eh_abort */
812 /* */
813 /* Routine Description: */
814 /* */
815 /* Abort a command (using the new error code stuff) */
816 /* Note: this routine is called under the io_request_lock */
817 /****************************************************************************/
818 int
ips_eh_abort(Scsi_Cmnd * SC)819 ips_eh_abort(Scsi_Cmnd * SC)
820 {
821 ips_ha_t *ha;
822 ips_copp_wait_item_t *item;
823 int ret;
824
825 METHOD_TRACE("ips_eh_abort", 1);
826
827 if (!SC)
828 return (FAILED);
829
830 ha = (ips_ha_t *) SC->device->host->hostdata;
831
832 if (!ha)
833 return (FAILED);
834
835 if (!ha->active)
836 return (FAILED);
837
838 if (SC->serial_number != SC->serial_number_at_timeout) {
839 /* HMM, looks like a bogus command */
840 DEBUG(1, "Abort called with bogus scsi command");
841
842 return (FAILED);
843 }
844
845 /* See if the command is on the copp queue */
846 item = ha->copp_waitlist.head;
847 while ((item) && (item->scsi_cmd != SC))
848 item = item->next;
849
850 if (item) {
851 /* Found it */
852 ips_removeq_copp(&ha->copp_waitlist, item);
853 ret = (SUCCESS);
854
855 /* See if the command is on the wait queue */
856 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
857 /* command not sent yet */
858 ret = (SUCCESS);
859 } else {
860 /* command must have already been sent */
861 ret = (FAILED);
862 }
863 return ret;
864 }
865
866 /****************************************************************************/
867 /* */
868 /* Routine Name: ips_eh_reset */
869 /* */
870 /* Routine Description: */
871 /* */
872 /* Reset the controller (with new eh error code) */
873 /* */
874 /* NOTE: this routine is called under the io_request_lock spinlock */
875 /* */
876 /****************************************************************************/
877 int
ips_eh_reset(Scsi_Cmnd * SC)878 ips_eh_reset(Scsi_Cmnd * SC)
879 {
880 int ret;
881 int i;
882 ips_ha_t *ha;
883 ips_scb_t *scb;
884 ips_copp_wait_item_t *item;
885
886 METHOD_TRACE("ips_eh_reset", 1);
887
888 #ifdef NO_IPS_RESET
889 return (FAILED);
890 #else
891
892 if (!SC) {
893 DEBUG(1, "Reset called with NULL scsi command");
894
895 return (FAILED);
896 }
897
898 ha = (ips_ha_t *) SC->device->host->hostdata;
899
900 if (!ha) {
901 DEBUG(1, "Reset called with NULL ha struct");
902
903 return (FAILED);
904 }
905
906 if (!ha->active)
907 return (FAILED);
908
909 /* See if the command is on the copp queue */
910 item = ha->copp_waitlist.head;
911 while ((item) && (item->scsi_cmd != SC))
912 item = item->next;
913
914 if (item) {
915 /* Found it */
916 ips_removeq_copp(&ha->copp_waitlist, item);
917 return (SUCCESS);
918 }
919
920 /* See if the command is on the wait queue */
921 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
922 /* command not sent yet */
923 return (SUCCESS);
924 }
925
926 /* An explanation for the casual observer: */
927 /* Part of the function of a RAID controller is automatic error */
928 /* detection and recovery. As such, the only problem that physically */
929 /* resetting an adapter will ever fix is when, for some reason, */
930 /* the driver is not successfully communicating with the adapter. */
931 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
932 /* then there's no real purpose in a physical reset. This will complete */
933 /* much faster and avoids any problems that might be caused by a */
934 /* physical reset ( such as having to fail all the outstanding I/O's ). */
935
936 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
937 scb = &ha->scbs[ha->max_cmds - 1];
938
939 ips_init_scb(ha, scb);
940
941 scb->timeout = ips_cmd_timeout;
942 scb->cdb[0] = IPS_CMD_FLUSH;
943
944 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
945 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
946 scb->cmd.flush_cache.state = IPS_NORM_STATE;
947 scb->cmd.flush_cache.reserved = 0;
948 scb->cmd.flush_cache.reserved2 = 0;
949 scb->cmd.flush_cache.reserved3 = 0;
950 scb->cmd.flush_cache.reserved4 = 0;
951
952 /* Attempt the flush command */
953 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
954 if (ret == IPS_SUCCESS) {
955 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
956 "Reset Request - Flushed Cache\n");
957 return (SUCCESS);
958 }
959 }
960
961 /* Either we can't communicate with the adapter or it's an IOCTL request */
962 /* from a utility. A physical reset is needed at this point. */
963
964 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
965
966 /*
967 * command must have already been sent
968 * reset the controller
969 */
970 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
971 ret = (*ha->func.reset) (ha);
972
973 if (!ret) {
974 Scsi_Cmnd *scsi_cmd;
975
976 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
977 "Controller reset failed - controller now offline.\n");
978
979 /* Now fail all of the active commands */
980 DEBUG_VAR(1, "(%s%d) Failing active commands",
981 ips_name, ha->host_num);
982
983 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
984 scb->scsi_cmd->result = DID_ERROR << 16;
985 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
986 ips_freescb(ha, scb);
987 }
988
989 /* Now fail all of the pending commands */
990 DEBUG_VAR(1, "(%s%d) Failing pending commands",
991 ips_name, ha->host_num);
992
993 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
994 scsi_cmd->result = DID_ERROR;
995 scsi_cmd->scsi_done(scsi_cmd);
996 }
997
998 ha->active = FALSE;
999 return (FAILED);
1000 }
1001
1002 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
1003 Scsi_Cmnd *scsi_cmd;
1004
1005 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
1006 "Controller reset failed - controller now offline.\n");
1007
1008 /* Now fail all of the active commands */
1009 DEBUG_VAR(1, "(%s%d) Failing active commands",
1010 ips_name, ha->host_num);
1011
1012 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1013 scb->scsi_cmd->result = DID_ERROR << 16;
1014 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1015 ips_freescb(ha, scb);
1016 }
1017
1018 /* Now fail all of the pending commands */
1019 DEBUG_VAR(1, "(%s%d) Failing pending commands",
1020 ips_name, ha->host_num);
1021
1022 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
1023 scsi_cmd->result = DID_ERROR << 16;
1024 scsi_cmd->scsi_done(scsi_cmd);
1025 }
1026
1027 ha->active = FALSE;
1028 return (FAILED);
1029 }
1030
1031 /* FFDC */
1032 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
1033 struct timeval tv;
1034
1035 do_gettimeofday(&tv);
1036 ha->last_ffdc = tv.tv_sec;
1037 ha->reset_count++;
1038 ips_ffdc_reset(ha, IPS_INTR_IORL);
1039 }
1040
1041 /* Now fail all of the active commands */
1042 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
1043
1044 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1045 scb->scsi_cmd->result =
1046 (DID_RESET << 16) | (SUGGEST_RETRY << 24);
1047 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1048 ips_freescb(ha, scb);
1049 }
1050
1051 /* Reset DCDB active command bits */
1052 for (i = 1; i < ha->nbus; i++)
1053 ha->dcdb_active[i - 1] = 0;
1054
1055 /* Reset the number of active IOCTLs */
1056 ha->num_ioctl = 0;
1057
1058 ips_next(ha, IPS_INTR_IORL);
1059
1060 return (SUCCESS);
1061 #endif /* NO_IPS_RESET */
1062
1063 }
1064
1065 /****************************************************************************/
1066 /* */
1067 /* Routine Name: ips_queue */
1068 /* */
1069 /* Routine Description: */
1070 /* */
1071 /* Send a command to the controller */
1072 /* */
1073 /* NOTE: */
1074 /* Linux obtains io_request_lock before calling this function */
1075 /* */
1076 /****************************************************************************/
1077 int
ips_queue(Scsi_Cmnd * SC,void (* done)(Scsi_Cmnd *))1078 ips_queue(Scsi_Cmnd * SC, void (*done) (Scsi_Cmnd *))
1079 {
1080 ips_ha_t *ha;
1081 ips_passthru_t *pt;
1082
1083 METHOD_TRACE("ips_queue", 1);
1084
1085 ha = (ips_ha_t *) SC->device->host->hostdata;
1086
1087 if (!ha)
1088 return (1);
1089
1090 if (!ha->active)
1091 return (DID_ERROR);
1092
1093 if (ips_is_passthru(SC)) {
1094 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1095 SC->result = DID_BUS_BUSY << 16;
1096 done(SC);
1097
1098 return (0);
1099 }
1100 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1101 SC->result = DID_BUS_BUSY << 16;
1102 done(SC);
1103
1104 return (0);
1105 }
1106
1107 SC->scsi_done = done;
1108
1109 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1110 ips_name,
1111 ha->host_num,
1112 SC->cmnd[0],
1113 SC->device->channel, SC->device->id, SC->device->lun);
1114
1115 /* Check for command to initiator IDs */
1116 if ((SC->device->channel > 0)
1117 && (SC->device->id == ha->ha_id[SC->device->channel])) {
1118 SC->result = DID_NO_CONNECT << 16;
1119 done(SC);
1120
1121 return (0);
1122 }
1123
1124 if (ips_is_passthru(SC)) {
1125
1126 ips_copp_wait_item_t *scratch;
1127
1128 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1129 /* There can never be any system activity ( network or disk ), but check */
1130 /* anyway just as a good practice. */
1131 pt = (ips_passthru_t *) SC->request_buffer;
1132 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1133 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1134 if (ha->scb_activelist.count != 0) {
1135 SC->result = DID_BUS_BUSY << 16;
1136 done(SC);
1137 return (0);
1138 }
1139 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1140 ips_eh_reset(SC);
1141 SC->result = DID_OK << 16;
1142 SC->scsi_done(SC);
1143 return (0);
1144 }
1145
1146 /* allocate space for the scribble */
1147 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1148
1149 if (!scratch) {
1150 SC->result = DID_ERROR << 16;
1151 done(SC);
1152
1153 return (0);
1154 }
1155
1156 scratch->scsi_cmd = SC;
1157 scratch->next = NULL;
1158
1159 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1160 } else {
1161 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1162 }
1163
1164 ips_next(ha, IPS_INTR_IORL);
1165
1166 return (0);
1167 }
1168
1169 /****************************************************************************/
1170 /* */
1171 /* Routine Name: ips_biosparam */
1172 /* */
1173 /* Routine Description: */
1174 /* */
1175 /* Set bios geometry for the controller */
1176 /* */
1177 /****************************************************************************/
1178 static int
1179 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
ips_biosparam(Disk * disk,kdev_t dev,int geom[])1180 ips_biosparam(Disk * disk, kdev_t dev, int geom[])
1181 {
1182 ips_ha_t *ha = (ips_ha_t *) disk->device->host->hostdata;
1183 unsigned long capacity = disk->capacity;
1184 #else
1185 ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1186 sector_t capacity, int geom[])
1187 {
1188 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1189 #endif
1190 int heads;
1191 int sectors;
1192 int cylinders;
1193
1194 METHOD_TRACE("ips_biosparam", 1);
1195
1196 if (!ha)
1197 /* ?!?! host adater info invalid */
1198 return (0);
1199
1200 if (!ha->active)
1201 return (0);
1202
1203 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1204 /* ?!?! Enquiry command failed */
1205 return (0);
1206
1207 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1208 heads = IPS_NORM_HEADS;
1209 sectors = IPS_NORM_SECTORS;
1210 } else {
1211 heads = IPS_COMP_HEADS;
1212 sectors = IPS_COMP_SECTORS;
1213 }
1214
1215 cylinders = (unsigned long) capacity / (heads * sectors);
1216
1217 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1218 heads, sectors, cylinders);
1219
1220 geom[0] = heads;
1221 geom[1] = sectors;
1222 geom[2] = cylinders;
1223
1224 return (0);
1225 }
1226
1227 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1228
1229 /* ips_proc24_info is a wrapper around ips_proc_info *
1230 * for compatibility with the 2.4 scsi parameters */
1231 static int
1232 ips_proc24_info(char *buffer, char **start, off_t offset, int length,
1233 int hostno, int func)
1234 {
1235 int i;
1236
1237 for (i = 0; i < ips_next_controller; i++) {
1238 if (ips_sh[i] && ips_sh[i]->host_no == hostno) {
1239 return ips_proc_info(ips_sh[i], buffer, start,
1240 offset, length, func);
1241 }
1242 }
1243 return -EINVAL;
1244 }
1245
1246 /****************************************************************************/
1247 /* */
1248 /* Routine Name: ips_select_queue_depth */
1249 /* */
1250 /* Routine Description: */
1251 /* */
1252 /* Select queue depths for the devices on the contoller */
1253 /* */
1254 /****************************************************************************/
1255 static void
1256 ips_select_queue_depth(struct Scsi_Host *host, Scsi_Device * scsi_devs)
1257 {
1258 Scsi_Device *device;
1259 ips_ha_t *ha;
1260 int count = 0;
1261 int min;
1262
1263 ha = IPS_HA(host);
1264 min = ha->max_cmds / 4;
1265
1266 for (device = scsi_devs; device; device = device->next) {
1267 if (device->host == host) {
1268 if ((device->channel == 0) && (device->type == 0))
1269 count++;
1270 }
1271 }
1272
1273 for (device = scsi_devs; device; device = device->next) {
1274 if (device->host == host) {
1275 if ((device->channel == 0) && (device->type == 0)) {
1276 device->queue_depth =
1277 (ha->max_cmds - 1) / count;
1278 if (device->queue_depth < min)
1279 device->queue_depth = min;
1280 } else {
1281 device->queue_depth = 2;
1282 }
1283
1284 if (device->queue_depth < 2)
1285 device->queue_depth = 2;
1286 }
1287 }
1288 }
1289
1290 #else
1291 /****************************************************************************/
1292 /* */
1293 /* Routine Name: ips_slave_configure */
1294 /* */
1295 /* Routine Description: */
1296 /* */
1297 /* Set queue depths on devices once scan is complete */
1298 /* */
1299 /****************************************************************************/
1300 int
1301 ips_slave_configure(Scsi_Device * SDptr)
1302 {
1303 ips_ha_t *ha;
1304 int min;
1305
1306 ha = IPS_HA(SDptr->host);
1307 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1308 min = ha->max_cmds / 2;
1309 if (ha->enq->ucLogDriveCount <= 2)
1310 min = ha->max_cmds - 1;
1311 scsi_adjust_queue_depth(SDptr, MSG_ORDERED_TAG, min);
1312 }
1313 return 0;
1314 }
1315 #endif
1316
1317 /****************************************************************************/
1318 /* */
1319 /* Routine Name: do_ipsintr */
1320 /* */
1321 /* Routine Description: */
1322 /* */
1323 /* Wrapper for the interrupt handler */
1324 /* */
1325 /****************************************************************************/
1326 irqreturn_t
1327 do_ipsintr(int irq, void *dev_id, struct pt_regs * regs)
1328 {
1329 ips_ha_t *ha;
1330 unsigned long cpu_flags;
1331 struct Scsi_Host *host;
1332 int irqstatus;
1333
1334 METHOD_TRACE("do_ipsintr", 2);
1335
1336 ha = (ips_ha_t *) dev_id;
1337 if (!ha)
1338 return IRQ_NONE;
1339 host = ips_sh[ha->host_num];
1340 /* interrupt during initialization */
1341 if (!host) {
1342 (*ha->func.intr) (ha);
1343 return IRQ_HANDLED;
1344 }
1345
1346 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
1347
1348 if (!ha->active) {
1349 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
1350 return IRQ_HANDLED;
1351 }
1352
1353 irqstatus = (*ha->func.intr) (ha);
1354
1355 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
1356
1357 /* start the next command */
1358 ips_next(ha, IPS_INTR_ON);
1359 return IRQ_RETVAL(irqstatus);
1360 }
1361
1362 /****************************************************************************/
1363 /* */
1364 /* Routine Name: ips_intr_copperhead */
1365 /* */
1366 /* Routine Description: */
1367 /* */
1368 /* Polling interrupt handler */
1369 /* */
1370 /* ASSUMES interrupts are disabled */
1371 /* */
1372 /****************************************************************************/
1373 int
1374 ips_intr_copperhead(ips_ha_t * ha)
1375 {
1376 ips_stat_t *sp;
1377 ips_scb_t *scb;
1378 IPS_STATUS cstatus;
1379 int intrstatus;
1380
1381 METHOD_TRACE("ips_intr", 2);
1382
1383 if (!ha)
1384 return 0;
1385
1386 if (!ha->active)
1387 return 0;
1388
1389 intrstatus = (*ha->func.isintr) (ha);
1390
1391 if (!intrstatus) {
1392 /*
1393 * Unexpected/Shared interrupt
1394 */
1395
1396 return 0;
1397 }
1398
1399 while (TRUE) {
1400 sp = &ha->sp;
1401
1402 intrstatus = (*ha->func.isintr) (ha);
1403
1404 if (!intrstatus)
1405 break;
1406 else
1407 cstatus.value = (*ha->func.statupd) (ha);
1408
1409 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1410 /* Spurious Interupt ? */
1411 continue;
1412 }
1413
1414 ips_chkstatus(ha, &cstatus);
1415 scb = (ips_scb_t *) sp->scb_addr;
1416
1417 /*
1418 * use the callback function to finish things up
1419 * NOTE: interrupts are OFF for this
1420 */
1421 (*scb->callback) (ha, scb);
1422 } /* end while */
1423 return 1;
1424 }
1425
1426 /****************************************************************************/
1427 /* */
1428 /* Routine Name: ips_intr_morpheus */
1429 /* */
1430 /* Routine Description: */
1431 /* */
1432 /* Polling interrupt handler */
1433 /* */
1434 /* ASSUMES interrupts are disabled */
1435 /* */
1436 /****************************************************************************/
1437 int
1438 ips_intr_morpheus(ips_ha_t * ha)
1439 {
1440 ips_stat_t *sp;
1441 ips_scb_t *scb;
1442 IPS_STATUS cstatus;
1443 int intrstatus;
1444
1445 METHOD_TRACE("ips_intr_morpheus", 2);
1446
1447 if (!ha)
1448 return 0;
1449
1450 if (!ha->active)
1451 return 0;
1452
1453 intrstatus = (*ha->func.isintr) (ha);
1454
1455 if (!intrstatus) {
1456 /*
1457 * Unexpected/Shared interrupt
1458 */
1459
1460 return 0;
1461 }
1462
1463 while (TRUE) {
1464 sp = &ha->sp;
1465
1466 intrstatus = (*ha->func.isintr) (ha);
1467
1468 if (!intrstatus)
1469 break;
1470 else
1471 cstatus.value = (*ha->func.statupd) (ha);
1472
1473 if (cstatus.value == 0xffffffff)
1474 /* No more to process */
1475 break;
1476
1477 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1478 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1479 "Spurious interrupt; no ccb.\n");
1480
1481 continue;
1482 }
1483
1484 ips_chkstatus(ha, &cstatus);
1485 scb = (ips_scb_t *) sp->scb_addr;
1486
1487 /*
1488 * use the callback function to finish things up
1489 * NOTE: interrupts are OFF for this
1490 */
1491 (*scb->callback) (ha, scb);
1492 } /* end while */
1493 return 1;
1494 }
1495
1496 /****************************************************************************/
1497 /* */
1498 /* Routine Name: ips_info */
1499 /* */
1500 /* Routine Description: */
1501 /* */
1502 /* Return info about the driver */
1503 /* */
1504 /****************************************************************************/
1505 const char *
1506 ips_info(struct Scsi_Host *SH)
1507 {
1508 static char buffer[256];
1509 char *bp;
1510 ips_ha_t *ha;
1511
1512 METHOD_TRACE("ips_info", 1);
1513
1514 ha = IPS_HA(SH);
1515
1516 if (!ha)
1517 return (NULL);
1518
1519 bp = &buffer[0];
1520 memset(bp, 0, sizeof (buffer));
1521
1522 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1523 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1524
1525 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1526 strcat(bp, " <");
1527 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1528 strcat(bp, ">");
1529 }
1530
1531 return (bp);
1532 }
1533
1534 /****************************************************************************/
1535 /* */
1536 /* Routine Name: ips_proc_info */
1537 /* */
1538 /* Routine Description: */
1539 /* */
1540 /* The passthru interface for the driver */
1541 /* */
1542 /****************************************************************************/
1543 int
1544 ips_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset,
1545 int length, int func)
1546 {
1547 int i;
1548 int ret;
1549 ips_ha_t *ha = NULL;
1550
1551 METHOD_TRACE("ips_proc_info", 1);
1552
1553 /* Find our host structure */
1554 for (i = 0; i < ips_next_controller; i++) {
1555 if (ips_sh[i]) {
1556 if (ips_sh[i] == host) {
1557 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1558 break;
1559 }
1560 }
1561 }
1562
1563 if (!ha)
1564 return (-EINVAL);
1565
1566 if (func) {
1567 /* write */
1568 return (0);
1569 } else {
1570 /* read */
1571 if (start)
1572 *start = buffer;
1573
1574 ret = ips_host_info(ha, buffer, offset, length);
1575
1576 return (ret);
1577 }
1578 }
1579
1580 /*--------------------------------------------------------------------------*/
1581 /* Helper Functions */
1582 /*--------------------------------------------------------------------------*/
1583
1584 /****************************************************************************/
1585 /* */
1586 /* Routine Name: ips_is_passthru */
1587 /* */
1588 /* Routine Description: */
1589 /* */
1590 /* Determine if the specified SCSI command is really a passthru command */
1591 /* */
1592 /****************************************************************************/
1593 static int
1594 ips_is_passthru(Scsi_Cmnd * SC)
1595 {
1596 METHOD_TRACE("ips_is_passthru", 1);
1597
1598 if (!SC)
1599 return (0);
1600
1601 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1602 (SC->device->channel == 0) &&
1603 (SC->device->id == IPS_ADAPTER_ID) &&
1604 (SC->device->lun == 0) && SC->request_buffer) {
1605 if ((!SC->use_sg) && SC->request_bufflen &&
1606 (((char *) SC->request_buffer)[0] == 'C') &&
1607 (((char *) SC->request_buffer)[1] == 'O') &&
1608 (((char *) SC->request_buffer)[2] == 'P') &&
1609 (((char *) SC->request_buffer)[3] == 'P'))
1610 return 1;
1611 else if (SC->use_sg) {
1612 struct scatterlist *sg = SC->request_buffer;
1613 char *buffer = IPS_SG_ADDRESS(sg);
1614 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1615 buffer[2] == 'P' && buffer[3] == 'P')
1616 return 1;
1617 }
1618 }
1619 return 0;
1620 }
1621
1622 /****************************************************************************/
1623 /* */
1624 /* Routine Name: ips_alloc_passthru_buffer */
1625 /* */
1626 /* Routine Description: */
1627 /* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1628 /* is too small or doesn't exist */
1629 /****************************************************************************/
1630 static int
1631 ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1632 {
1633 void *bigger_buf;
1634 dma_addr_t dma_busaddr;
1635
1636 if (ha->ioctl_data && length <= ha->ioctl_len)
1637 return 0;
1638 /* there is no buffer or it's not big enough, allocate a new one */
1639 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1640 if (bigger_buf) {
1641 /* free the old memory */
1642 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1643 ha->ioctl_busaddr);
1644 /* use the new memory */
1645 ha->ioctl_data = (char *) bigger_buf;
1646 ha->ioctl_len = length;
1647 ha->ioctl_busaddr = dma_busaddr;
1648 } else {
1649 return -1;
1650 }
1651 return 0;
1652 }
1653
1654 /****************************************************************************/
1655 /* */
1656 /* Routine Name: ips_make_passthru */
1657 /* */
1658 /* Routine Description: */
1659 /* */
1660 /* Make a passthru command out of the info in the Scsi block */
1661 /* */
1662 /****************************************************************************/
1663 static int
1664 ips_make_passthru(ips_ha_t * ha, Scsi_Cmnd * SC, ips_scb_t * scb, int intr)
1665 {
1666 ips_passthru_t *pt;
1667 int length = 0;
1668 int ret;
1669
1670 METHOD_TRACE("ips_make_passthru", 1);
1671
1672 if (!SC->use_sg) {
1673 length = SC->request_bufflen;
1674 } else {
1675 struct scatterlist *sg = SC->request_buffer;
1676 int i;
1677 for (i = 0; i < SC->use_sg; i++)
1678 length += sg[i].length;
1679 }
1680 if (length < sizeof (ips_passthru_t)) {
1681 /* wrong size */
1682 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1683 ips_name, ha->host_num);
1684 return (IPS_FAILURE);
1685 }
1686 if (ips_alloc_passthru_buffer(ha, length)) {
1687 /* allocation failure! If ha->ioctl_data exists, use it to return
1688 some error codes. Return a failed command to the scsi layer. */
1689 if (ha->ioctl_data) {
1690 pt = (ips_passthru_t *) ha->ioctl_data;
1691 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1692 pt->BasicStatus = 0x0B;
1693 pt->ExtendedStatus = 0x00;
1694 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1695 }
1696 return IPS_FAILURE;
1697 }
1698 ha->ioctl_datasize = length;
1699
1700 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1701 pt = (ips_passthru_t *) ha->ioctl_data;
1702
1703 /*
1704 * Some notes about the passthru interface used
1705 *
1706 * IF the scsi op_code == 0x0d then we assume
1707 * that the data came along with/goes with the
1708 * packet we received from the sg driver. In this
1709 * case the CmdBSize field of the pt structure is
1710 * used for the size of the buffer.
1711 */
1712
1713 switch (pt->CoppCmd) {
1714 case IPS_NUMCTRLS:
1715 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1716 &ips_num_controllers, sizeof (int));
1717 ips_scmd_buf_write(SC, ha->ioctl_data,
1718 sizeof (ips_passthru_t) + sizeof (int));
1719 SC->result = DID_OK << 16;
1720
1721 return (IPS_SUCCESS_IMM);
1722
1723 case IPS_COPPUSRCMD:
1724 case IPS_COPPIOCCMD:
1725 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1726 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1727 /* wrong size */
1728 DEBUG_VAR(1,
1729 "(%s%d) Passthru structure wrong size",
1730 ips_name, ha->host_num);
1731
1732 return (IPS_FAILURE);
1733 }
1734
1735 if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
1736 pt->CoppCP.cmd.flashfw.op_code ==
1737 IPS_CMD_RW_BIOSFW) {
1738 ret = ips_flash_copperhead(ha, pt, scb);
1739 ips_scmd_buf_write(SC, ha->ioctl_data,
1740 sizeof (ips_passthru_t));
1741 return ret;
1742 }
1743 if (ips_usrcmd(ha, pt, scb))
1744 return (IPS_SUCCESS);
1745 else
1746 return (IPS_FAILURE);
1747 }
1748
1749 break;
1750
1751 } /* end switch */
1752
1753 return (IPS_FAILURE);
1754 }
1755
1756 /****************************************************************************/
1757 /* Routine Name: ips_flash_copperhead */
1758 /* Routine Description: */
1759 /* Flash the BIOS/FW on a Copperhead style controller */
1760 /****************************************************************************/
1761 static int
1762 ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1763 {
1764 int datasize;
1765
1766 /* Trombone is the only copperhead that can do packet flash, but only
1767 * for firmware. No one said it had to make sence. */
1768 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1769 if (ips_usrcmd(ha, pt, scb))
1770 return IPS_SUCCESS;
1771 else
1772 return IPS_FAILURE;
1773 }
1774 pt->BasicStatus = 0x0B;
1775 pt->ExtendedStatus = 0;
1776 scb->scsi_cmd->result = DID_OK << 16;
1777 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1778 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1779 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1780 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1781 pt->BasicStatus = 0;
1782 return ips_flash_bios(ha, pt, scb);
1783 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1784 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1785 ha->flash_data = ips_FlashData;
1786 ha->flash_busaddr = ips_flashbusaddr;
1787 ha->flash_len = PAGE_SIZE << 7;
1788 ha->flash_datasize = 0;
1789 } else if (!ha->flash_data) {
1790 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1791 pt->CoppCP.cmd.flashfw.count;
1792 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1793 datasize,
1794 &ha->flash_busaddr);
1795 if (!ha->flash_data){
1796 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1797 return IPS_FAILURE;
1798 }
1799 ha->flash_datasize = 0;
1800 ha->flash_len = datasize;
1801 } else
1802 return IPS_FAILURE;
1803 } else {
1804 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1805 ha->flash_len) {
1806 ips_free_flash_copperhead(ha);
1807 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1808 "failed size sanity check\n");
1809 return IPS_FAILURE;
1810 }
1811 }
1812 if (!ha->flash_data)
1813 return IPS_FAILURE;
1814 pt->BasicStatus = 0;
1815 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1816 pt->CoppCP.cmd.flashfw.count);
1817 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1818 if (pt->CoppCP.cmd.flashfw.packet_num ==
1819 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1820 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1821 return ips_flash_bios(ha, pt, scb);
1822 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1823 return ips_flash_firmware(ha, pt, scb);
1824 }
1825 return IPS_SUCCESS_IMM;
1826 }
1827
1828 /****************************************************************************/
1829 /* Routine Name: ips_flash_bios */
1830 /* Routine Description: */
1831 /* flashes the bios of a copperhead adapter */
1832 /****************************************************************************/
1833 static int
1834 ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1835 {
1836
1837 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1838 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1839 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1840 (!ha->func.verifybios))
1841 goto error;
1842 if ((*ha->func.erasebios) (ha)) {
1843 DEBUG_VAR(1,
1844 "(%s%d) flash bios failed - unable to erase flash",
1845 ips_name, ha->host_num);
1846 goto error;
1847 } else
1848 if ((*ha->func.programbios) (ha,
1849 ha->flash_data +
1850 IPS_BIOS_HEADER,
1851 ha->flash_datasize -
1852 IPS_BIOS_HEADER, 0)) {
1853 DEBUG_VAR(1,
1854 "(%s%d) flash bios failed - unable to flash",
1855 ips_name, ha->host_num);
1856 goto error;
1857 } else
1858 if ((*ha->func.verifybios) (ha,
1859 ha->flash_data +
1860 IPS_BIOS_HEADER,
1861 ha->flash_datasize -
1862 IPS_BIOS_HEADER, 0)) {
1863 DEBUG_VAR(1,
1864 "(%s%d) flash bios failed - unable to verify flash",
1865 ips_name, ha->host_num);
1866 goto error;
1867 }
1868 ips_free_flash_copperhead(ha);
1869 return IPS_SUCCESS_IMM;
1870 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1871 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1872 if (!ha->func.erasebios)
1873 goto error;
1874 if ((*ha->func.erasebios) (ha)) {
1875 DEBUG_VAR(1,
1876 "(%s%d) flash bios failed - unable to erase flash",
1877 ips_name, ha->host_num);
1878 goto error;
1879 }
1880 return IPS_SUCCESS_IMM;
1881 }
1882 error:
1883 pt->BasicStatus = 0x0B;
1884 pt->ExtendedStatus = 0x00;
1885 ips_free_flash_copperhead(ha);
1886 return IPS_FAILURE;
1887 }
1888
1889 /****************************************************************************/
1890 /* */
1891 /* Routine Name: ips_fill_scb_sg_single */
1892 /* */
1893 /* Routine Description: */
1894 /* Fill in a single scb sg_list element from an address */
1895 /* return a -1 if a breakup occurred */
1896 /****************************************************************************/
1897 static int
1898 ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1899 ips_scb_t * scb, int indx, unsigned int e_len)
1900 {
1901
1902 int ret_val = 0;
1903
1904 if ((scb->data_len + e_len) > ha->max_xfer) {
1905 e_len = ha->max_xfer - scb->data_len;
1906 scb->breakup = indx;
1907 ++scb->sg_break;
1908 ret_val = -1;
1909 } else {
1910 scb->breakup = 0;
1911 scb->sg_break = 0;
1912 }
1913 if (IPS_USE_ENH_SGLIST(ha)) {
1914 scb->sg_list.enh_list[indx].address_lo =
1915 cpu_to_le32(pci_dma_lo32(busaddr));
1916 scb->sg_list.enh_list[indx].address_hi =
1917 cpu_to_le32(pci_dma_hi32(busaddr));
1918 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1919 } else {
1920 scb->sg_list.std_list[indx].address =
1921 cpu_to_le32(pci_dma_lo32(busaddr));
1922 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1923 }
1924
1925 ++scb->sg_len;
1926 scb->data_len += e_len;
1927 return ret_val;
1928 }
1929
1930 /****************************************************************************/
1931 /* Routine Name: ips_flash_firmware */
1932 /* Routine Description: */
1933 /* flashes the firmware of a copperhead adapter */
1934 /****************************************************************************/
1935 static int
1936 ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1937 {
1938 IPS_SG_LIST sg_list;
1939 uint32_t cmd_busaddr;
1940
1941 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1942 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1943 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1944 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1945 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1946 } else {
1947 pt->BasicStatus = 0x0B;
1948 pt->ExtendedStatus = 0x00;
1949 ips_free_flash_copperhead(ha);
1950 return IPS_FAILURE;
1951 }
1952 /* Save the S/G list pointer so it doesn't get clobbered */
1953 sg_list.list = scb->sg_list.list;
1954 cmd_busaddr = scb->scb_busaddr;
1955 /* copy in the CP */
1956 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1957 /* FIX stuff that might be wrong */
1958 scb->sg_list.list = sg_list.list;
1959 scb->scb_busaddr = cmd_busaddr;
1960 scb->bus = scb->scsi_cmd->device->channel;
1961 scb->target_id = scb->scsi_cmd->device->id;
1962 scb->lun = scb->scsi_cmd->device->lun;
1963 scb->sg_len = 0;
1964 scb->data_len = 0;
1965 scb->flags = 0;
1966 scb->op_code = 0;
1967 scb->callback = ipsintr_done;
1968 scb->timeout = ips_cmd_timeout;
1969
1970 scb->data_len = ha->flash_datasize;
1971 scb->data_busaddr =
1972 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1973 IPS_DMA_DIR(scb));
1974 scb->flags |= IPS_SCB_MAP_SINGLE;
1975 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1976 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1977 if (pt->TimeOut)
1978 scb->timeout = pt->TimeOut;
1979 scb->scsi_cmd->result = DID_OK << 16;
1980 return IPS_SUCCESS;
1981 }
1982
1983 /****************************************************************************/
1984 /* Routine Name: ips_free_flash_copperhead */
1985 /* Routine Description: */
1986 /* release the memory resources used to hold the flash image */
1987 /****************************************************************************/
1988 static void
1989 ips_free_flash_copperhead(ips_ha_t * ha)
1990 {
1991 if (ha->flash_data == ips_FlashData)
1992 test_and_clear_bit(0, &ips_FlashDataInUse);
1993 else if (ha->flash_data)
1994 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
1995 ha->flash_busaddr);
1996 ha->flash_data = NULL;
1997 }
1998
1999 /****************************************************************************/
2000 /* */
2001 /* Routine Name: ips_usrcmd */
2002 /* */
2003 /* Routine Description: */
2004 /* */
2005 /* Process a user command and make it ready to send */
2006 /* */
2007 /****************************************************************************/
2008 static int
2009 ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
2010 {
2011 IPS_SG_LIST sg_list;
2012 uint32_t cmd_busaddr;
2013
2014 METHOD_TRACE("ips_usrcmd", 1);
2015
2016 if ((!scb) || (!pt) || (!ha))
2017 return (0);
2018
2019 /* Save the S/G list pointer so it doesn't get clobbered */
2020 sg_list.list = scb->sg_list.list;
2021 cmd_busaddr = scb->scb_busaddr;
2022 /* copy in the CP */
2023 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
2024 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
2025
2026 /* FIX stuff that might be wrong */
2027 scb->sg_list.list = sg_list.list;
2028 scb->scb_busaddr = cmd_busaddr;
2029 scb->bus = scb->scsi_cmd->device->channel;
2030 scb->target_id = scb->scsi_cmd->device->id;
2031 scb->lun = scb->scsi_cmd->device->lun;
2032 scb->sg_len = 0;
2033 scb->data_len = 0;
2034 scb->flags = 0;
2035 scb->op_code = 0;
2036 scb->callback = ipsintr_done;
2037 scb->timeout = ips_cmd_timeout;
2038 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
2039
2040 /* we don't support DCDB/READ/WRITE Scatter Gather */
2041 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
2042 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
2043 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
2044 return (0);
2045
2046 if (pt->CmdBSize) {
2047 scb->data_len = pt->CmdBSize;
2048 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
2049 } else {
2050 scb->data_busaddr = 0L;
2051 }
2052
2053 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
2054 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
2055 (unsigned long) &scb->
2056 dcdb -
2057 (unsigned long) scb);
2058
2059 if (pt->CmdBSize) {
2060 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
2061 scb->dcdb.buffer_pointer =
2062 cpu_to_le32(scb->data_busaddr);
2063 else
2064 scb->cmd.basic_io.sg_addr =
2065 cpu_to_le32(scb->data_busaddr);
2066 }
2067
2068 /* set timeouts */
2069 if (pt->TimeOut) {
2070 scb->timeout = pt->TimeOut;
2071
2072 if (pt->TimeOut <= 10)
2073 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
2074 else if (pt->TimeOut <= 60)
2075 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
2076 else
2077 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
2078 }
2079
2080 /* assume success */
2081 scb->scsi_cmd->result = DID_OK << 16;
2082
2083 /* success */
2084 return (1);
2085 }
2086
2087 /****************************************************************************/
2088 /* */
2089 /* Routine Name: ips_cleanup_passthru */
2090 /* */
2091 /* Routine Description: */
2092 /* */
2093 /* Cleanup after a passthru command */
2094 /* */
2095 /****************************************************************************/
2096 static void
2097 ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
2098 {
2099 ips_passthru_t *pt;
2100
2101 METHOD_TRACE("ips_cleanup_passthru", 1);
2102
2103 if ((!scb) || (!scb->scsi_cmd) || (!scb->scsi_cmd->request_buffer)) {
2104 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
2105 ips_name, ha->host_num);
2106
2107 return;
2108 }
2109 pt = (ips_passthru_t *) ha->ioctl_data;
2110
2111 /* Copy data back to the user */
2112 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2113 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2114
2115 pt->BasicStatus = scb->basic_status;
2116 pt->ExtendedStatus = scb->extended_status;
2117 pt->AdapterType = ha->ad_type;
2118
2119 if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
2120 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2121 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2122 ips_free_flash_copperhead(ha);
2123
2124 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2125 }
2126
2127 /****************************************************************************/
2128 /* */
2129 /* Routine Name: ips_host_info */
2130 /* */
2131 /* Routine Description: */
2132 /* */
2133 /* The passthru interface for the driver */
2134 /* */
2135 /****************************************************************************/
2136 static int
2137 ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len)
2138 {
2139 IPS_INFOSTR info;
2140
2141 METHOD_TRACE("ips_host_info", 1);
2142
2143 info.buffer = ptr;
2144 info.length = len;
2145 info.offset = offset;
2146 info.pos = 0;
2147 info.localpos = 0;
2148
2149 copy_info(&info, "\nIBM ServeRAID General Information:\n\n");
2150
2151 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2152 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2153 copy_info(&info, "\tController Type : %s\n",
2154 ips_adapter_name[ha->ad_type - 1]);
2155 else
2156 copy_info(&info,
2157 "\tController Type : Unknown\n");
2158
2159 if (ha->io_addr)
2160 copy_info(&info,
2161 "\tIO region : 0x%lx (%d bytes)\n",
2162 ha->io_addr, ha->io_len);
2163
2164 if (ha->mem_addr) {
2165 copy_info(&info,
2166 "\tMemory region : 0x%lx (%d bytes)\n",
2167 ha->mem_addr, ha->mem_len);
2168 copy_info(&info,
2169 "\tShared memory address : 0x%lx\n",
2170 ha->mem_ptr);
2171 }
2172
2173 copy_info(&info, "\tIRQ number : %d\n", ha->irq);
2174
2175 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2176 /* That keeps everything happy for "text" operations on the proc file. */
2177
2178 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2179 if (ha->nvram->bios_low[3] == 0) {
2180 copy_info(&info,
2181 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2182 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2183 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2184 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2185 ha->nvram->bios_low[2]);
2186
2187 } else {
2188 copy_info(&info,
2189 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2190 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2191 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2192 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2193 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2194 }
2195
2196 }
2197
2198 if (ha->enq->CodeBlkVersion[7] == 0) {
2199 copy_info(&info,
2200 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2201 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2202 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2203 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2204 ha->enq->CodeBlkVersion[6]);
2205 } else {
2206 copy_info(&info,
2207 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2208 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2209 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2210 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2211 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2212 }
2213
2214 if (ha->enq->BootBlkVersion[7] == 0) {
2215 copy_info(&info,
2216 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2217 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2218 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2219 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2220 ha->enq->BootBlkVersion[6]);
2221 } else {
2222 copy_info(&info,
2223 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2224 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2225 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2226 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2227 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2228 }
2229
2230 copy_info(&info, "\tDriver Version : %s%s\n",
2231 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2232
2233 copy_info(&info, "\tDriver Build : %d\n",
2234 IPS_BUILD_IDENT);
2235
2236 copy_info(&info, "\tMax Physical Devices : %d\n",
2237 ha->enq->ucMaxPhysicalDevices);
2238 copy_info(&info, "\tMax Active Commands : %d\n",
2239 ha->max_cmds);
2240 copy_info(&info, "\tCurrent Queued Commands : %d\n",
2241 ha->scb_waitlist.count);
2242 copy_info(&info, "\tCurrent Active Commands : %d\n",
2243 ha->scb_activelist.count - ha->num_ioctl);
2244 copy_info(&info, "\tCurrent Queued PT Commands : %d\n",
2245 ha->copp_waitlist.count);
2246 copy_info(&info, "\tCurrent Active PT Commands : %d\n",
2247 ha->num_ioctl);
2248
2249 copy_info(&info, "\n");
2250
2251 return (info.localpos);
2252 }
2253
2254 /****************************************************************************/
2255 /* */
2256 /* Routine Name: copy_mem_info */
2257 /* */
2258 /* Routine Description: */
2259 /* */
2260 /* Copy data into an IPS_INFOSTR structure */
2261 /* */
2262 /****************************************************************************/
2263 static void
2264 copy_mem_info(IPS_INFOSTR * info, char *data, int len)
2265 {
2266 METHOD_TRACE("copy_mem_info", 1);
2267
2268 if (info->pos + len < info->offset) {
2269 info->pos += len;
2270 return;
2271 }
2272
2273 if (info->pos < info->offset) {
2274 data += (info->offset - info->pos);
2275 len -= (info->offset - info->pos);
2276 info->pos += (info->offset - info->pos);
2277 }
2278
2279 if (info->localpos + len > info->length)
2280 len = info->length - info->localpos;
2281
2282 if (len > 0) {
2283 memcpy(info->buffer + info->localpos, data, len);
2284 info->pos += len;
2285 info->localpos += len;
2286 }
2287 }
2288
2289 /****************************************************************************/
2290 /* */
2291 /* Routine Name: copy_info */
2292 /* */
2293 /* Routine Description: */
2294 /* */
2295 /* printf style wrapper for an info structure */
2296 /* */
2297 /****************************************************************************/
2298 static int
2299 copy_info(IPS_INFOSTR * info, char *fmt, ...)
2300 {
2301 va_list args;
2302 char buf[128];
2303 int len;
2304
2305 METHOD_TRACE("copy_info", 1);
2306
2307 va_start(args, fmt);
2308 len = vsprintf(buf, fmt, args);
2309 va_end(args);
2310
2311 copy_mem_info(info, buf, len);
2312
2313 return (len);
2314 }
2315
2316 /****************************************************************************/
2317 /* */
2318 /* Routine Name: ips_identify_controller */
2319 /* */
2320 /* Routine Description: */
2321 /* */
2322 /* Identify this controller */
2323 /* */
2324 /****************************************************************************/
2325 static void
2326 ips_identify_controller(ips_ha_t * ha)
2327 {
2328 METHOD_TRACE("ips_identify_controller", 1);
2329
2330 switch (ha->device_id) {
2331 case IPS_DEVICEID_COPPERHEAD:
2332 if (ha->revision_id <= IPS_REVID_SERVERAID) {
2333 ha->ad_type = IPS_ADTYPE_SERVERAID;
2334 } else if (ha->revision_id == IPS_REVID_SERVERAID2) {
2335 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2336 } else if (ha->revision_id == IPS_REVID_NAVAJO) {
2337 ha->ad_type = IPS_ADTYPE_NAVAJO;
2338 } else if ((ha->revision_id == IPS_REVID_SERVERAID2)
2339 && (ha->slot_num == 0)) {
2340 ha->ad_type = IPS_ADTYPE_KIOWA;
2341 } else if ((ha->revision_id >= IPS_REVID_CLARINETP1) &&
2342 (ha->revision_id <= IPS_REVID_CLARINETP3)) {
2343 if (ha->enq->ucMaxPhysicalDevices == 15)
2344 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2345 else
2346 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2347 } else if ((ha->revision_id >= IPS_REVID_TROMBONE32) &&
2348 (ha->revision_id <= IPS_REVID_TROMBONE64)) {
2349 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2350 }
2351 break;
2352
2353 case IPS_DEVICEID_MORPHEUS:
2354 switch (ha->subdevice_id) {
2355 case IPS_SUBDEVICEID_4L:
2356 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2357 break;
2358
2359 case IPS_SUBDEVICEID_4M:
2360 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2361 break;
2362
2363 case IPS_SUBDEVICEID_4MX:
2364 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2365 break;
2366
2367 case IPS_SUBDEVICEID_4LX:
2368 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2369 break;
2370
2371 case IPS_SUBDEVICEID_5I2:
2372 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2373 break;
2374
2375 case IPS_SUBDEVICEID_5I1:
2376 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2377 break;
2378 }
2379
2380 break;
2381
2382 case IPS_DEVICEID_MARCO:
2383 switch (ha->subdevice_id) {
2384 case IPS_SUBDEVICEID_6M:
2385 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2386 break;
2387 case IPS_SUBDEVICEID_6I:
2388 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2389 break;
2390 case IPS_SUBDEVICEID_7k:
2391 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2392 break;
2393 case IPS_SUBDEVICEID_7M:
2394 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2395 break;
2396 }
2397 break;
2398 }
2399 }
2400
2401 /****************************************************************************/
2402 /* */
2403 /* Routine Name: ips_get_bios_version */
2404 /* */
2405 /* Routine Description: */
2406 /* */
2407 /* Get the BIOS revision number */
2408 /* */
2409 /****************************************************************************/
2410 static void
2411 ips_get_bios_version(ips_ha_t * ha, int intr)
2412 {
2413 ips_scb_t *scb;
2414 int ret;
2415 uint8_t major;
2416 uint8_t minor;
2417 uint8_t subminor;
2418 uint8_t *buffer;
2419 char hexDigits[] =
2420 { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
2421 'D', 'E', 'F' };
2422
2423 METHOD_TRACE("ips_get_bios_version", 1);
2424
2425 major = 0;
2426 minor = 0;
2427
2428 strncpy(ha->bios_version, " ?", 8);
2429
2430 if (ha->device_id == IPS_DEVICEID_COPPERHEAD) {
2431 if (IPS_USE_MEMIO(ha)) {
2432 /* Memory Mapped I/O */
2433
2434 /* test 1st byte */
2435 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2436 if (ha->revision_id == IPS_REVID_TROMBONE64)
2437 udelay(25); /* 25 us */
2438
2439 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2440 return;
2441
2442 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2443 if (ha->revision_id == IPS_REVID_TROMBONE64)
2444 udelay(25); /* 25 us */
2445
2446 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2447 return;
2448
2449 /* Get Major version */
2450 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2451 if (ha->revision_id == IPS_REVID_TROMBONE64)
2452 udelay(25); /* 25 us */
2453
2454 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2455
2456 /* Get Minor version */
2457 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2458 if (ha->revision_id == IPS_REVID_TROMBONE64)
2459 udelay(25); /* 25 us */
2460 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2461
2462 /* Get SubMinor version */
2463 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2464 if (ha->revision_id == IPS_REVID_TROMBONE64)
2465 udelay(25); /* 25 us */
2466 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2467
2468 } else {
2469 /* Programmed I/O */
2470
2471 /* test 1st byte */
2472 outl(0, ha->io_addr + IPS_REG_FLAP);
2473 if (ha->revision_id == IPS_REVID_TROMBONE64)
2474 udelay(25); /* 25 us */
2475
2476 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2477 return;
2478
2479 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
2480 if (ha->revision_id == IPS_REVID_TROMBONE64)
2481 udelay(25); /* 25 us */
2482
2483 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2484 return;
2485
2486 /* Get Major version */
2487 outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP);
2488 if (ha->revision_id == IPS_REVID_TROMBONE64)
2489 udelay(25); /* 25 us */
2490
2491 major = inb(ha->io_addr + IPS_REG_FLDP);
2492
2493 /* Get Minor version */
2494 outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP);
2495 if (ha->revision_id == IPS_REVID_TROMBONE64)
2496 udelay(25); /* 25 us */
2497
2498 minor = inb(ha->io_addr + IPS_REG_FLDP);
2499
2500 /* Get SubMinor version */
2501 outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP);
2502 if (ha->revision_id == IPS_REVID_TROMBONE64)
2503 udelay(25); /* 25 us */
2504
2505 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2506
2507 }
2508 } else {
2509 /* Morpheus Family - Send Command to the card */
2510
2511 buffer = ha->ioctl_data;
2512
2513 memset(buffer, 0, 0x1000);
2514
2515 scb = &ha->scbs[ha->max_cmds - 1];
2516
2517 ips_init_scb(ha, scb);
2518
2519 scb->timeout = ips_cmd_timeout;
2520 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2521
2522 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2523 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2524 scb->cmd.flashfw.type = 1;
2525 scb->cmd.flashfw.direction = 0;
2526 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2527 scb->cmd.flashfw.total_packets = 1;
2528 scb->cmd.flashfw.packet_num = 0;
2529 scb->data_len = 0x1000;
2530 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2531
2532 /* issue the command */
2533 if (((ret =
2534 ips_send_wait(ha, scb, ips_cmd_timeout,
2535 intr)) == IPS_FAILURE)
2536 || (ret == IPS_SUCCESS_IMM)
2537 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2538 /* Error occurred */
2539
2540 return;
2541 }
2542
2543 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2544 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2545 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2546 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2547 } else {
2548 return;
2549 }
2550 }
2551
2552 ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4];
2553 ha->bios_version[1] = '.';
2554 ha->bios_version[2] = hexDigits[major & 0x0F];
2555 ha->bios_version[3] = hexDigits[subminor];
2556 ha->bios_version[4] = '.';
2557 ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4];
2558 ha->bios_version[6] = hexDigits[minor & 0x0F];
2559 ha->bios_version[7] = 0;
2560 }
2561
2562 /****************************************************************************/
2563 /* */
2564 /* Routine Name: ips_hainit */
2565 /* */
2566 /* Routine Description: */
2567 /* */
2568 /* Initialize the controller */
2569 /* */
2570 /* NOTE: Assumes to be called from with a lock */
2571 /* */
2572 /****************************************************************************/
2573 static int
2574 ips_hainit(ips_ha_t * ha)
2575 {
2576 int i;
2577 struct timeval tv;
2578
2579 METHOD_TRACE("ips_hainit", 1);
2580
2581 if (!ha)
2582 return (0);
2583
2584 if (ha->func.statinit)
2585 (*ha->func.statinit) (ha);
2586
2587 if (ha->func.enableint)
2588 (*ha->func.enableint) (ha);
2589
2590 /* Send FFDC */
2591 ha->reset_count = 1;
2592 do_gettimeofday(&tv);
2593 ha->last_ffdc = tv.tv_sec;
2594 ips_ffdc_reset(ha, IPS_INTR_IORL);
2595
2596 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2597 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2598 "unable to read config from controller.\n");
2599
2600 return (0);
2601 }
2602 /* end if */
2603 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2604 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2605 "unable to read controller status.\n");
2606
2607 return (0);
2608 }
2609
2610 /* Identify this controller */
2611 ips_identify_controller(ha);
2612
2613 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2614 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2615 "unable to read subsystem parameters.\n");
2616
2617 return (0);
2618 }
2619
2620 /* write nvram user page 5 */
2621 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2622 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2623 "unable to write driver info to controller.\n");
2624
2625 return (0);
2626 }
2627
2628 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2629 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2630 ips_clear_adapter(ha, IPS_INTR_IORL);
2631
2632 /* set limits on SID, LUN, BUS */
2633 ha->ntargets = IPS_MAX_TARGETS + 1;
2634 ha->nlun = 1;
2635 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2636
2637 switch (ha->conf->logical_drive[0].ucStripeSize) {
2638 case 4:
2639 ha->max_xfer = 0x10000;
2640 break;
2641
2642 case 5:
2643 ha->max_xfer = 0x20000;
2644 break;
2645
2646 case 6:
2647 ha->max_xfer = 0x40000;
2648 break;
2649
2650 case 7:
2651 default:
2652 ha->max_xfer = 0x80000;
2653 break;
2654 }
2655
2656 /* setup max concurrent commands */
2657 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2658 /* Use the new method */
2659 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2660 } else {
2661 /* use the old method */
2662 switch (ha->conf->logical_drive[0].ucStripeSize) {
2663 case 4:
2664 ha->max_cmds = 32;
2665 break;
2666
2667 case 5:
2668 ha->max_cmds = 16;
2669 break;
2670
2671 case 6:
2672 ha->max_cmds = 8;
2673 break;
2674
2675 case 7:
2676 default:
2677 ha->max_cmds = 4;
2678 break;
2679 }
2680 }
2681
2682 /* Limit the Active Commands on a Lite Adapter */
2683 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2684 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2685 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2686 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2687 ha->max_cmds = MaxLiteCmds;
2688 }
2689
2690 /* set controller IDs */
2691 ha->ha_id[0] = IPS_ADAPTER_ID;
2692 for (i = 1; i < ha->nbus; i++) {
2693 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2694 ha->dcdb_active[i - 1] = 0;
2695 }
2696
2697 return (1);
2698 }
2699
2700 /****************************************************************************/
2701 /* */
2702 /* Routine Name: ips_next */
2703 /* */
2704 /* Routine Description: */
2705 /* */
2706 /* Take the next command off the queue and send it to the controller */
2707 /* */
2708 /****************************************************************************/
2709 static void
2710 ips_next(ips_ha_t * ha, int intr)
2711 {
2712 ips_scb_t *scb;
2713 Scsi_Cmnd *SC;
2714 Scsi_Cmnd *p;
2715 Scsi_Cmnd *q;
2716 ips_copp_wait_item_t *item;
2717 int ret;
2718 unsigned long cpu_flags = 0;
2719 struct Scsi_Host *host;
2720 METHOD_TRACE("ips_next", 1);
2721
2722 if (!ha)
2723 return;
2724 host = ips_sh[ha->host_num];
2725 /*
2726 * Block access to the queue function so
2727 * this command won't time out
2728 */
2729 if (intr == IPS_INTR_ON)
2730 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2731
2732 if ((ha->subsys->param[3] & 0x300000)
2733 && (ha->scb_activelist.count == 0)) {
2734 struct timeval tv;
2735
2736 do_gettimeofday(&tv);
2737
2738 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2739 ha->last_ffdc = tv.tv_sec;
2740 ips_ffdc_time(ha);
2741 }
2742 }
2743
2744 /*
2745 * Send passthru commands
2746 * These have priority over normal I/O
2747 * but shouldn't affect performance too much
2748 * since we limit the number that can be active
2749 * on the card at any one time
2750 */
2751 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2752 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2753
2754 item = ips_removeq_copp_head(&ha->copp_waitlist);
2755 ha->num_ioctl++;
2756 if (intr == IPS_INTR_ON)
2757 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
2758 scb->scsi_cmd = item->scsi_cmd;
2759 kfree(item);
2760
2761 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2762
2763 if (intr == IPS_INTR_ON)
2764 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2765 switch (ret) {
2766 case IPS_FAILURE:
2767 if (scb->scsi_cmd) {
2768 scb->scsi_cmd->result = DID_ERROR << 16;
2769 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2770 }
2771
2772 ips_freescb(ha, scb);
2773 break;
2774 case IPS_SUCCESS_IMM:
2775 if (scb->scsi_cmd) {
2776 scb->scsi_cmd->result = DID_OK << 16;
2777 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2778 }
2779
2780 ips_freescb(ha, scb);
2781 break;
2782 default:
2783 break;
2784 } /* end case */
2785
2786 if (ret != IPS_SUCCESS) {
2787 ha->num_ioctl--;
2788 continue;
2789 }
2790
2791 ret = ips_send_cmd(ha, scb);
2792
2793 if (ret == IPS_SUCCESS)
2794 ips_putq_scb_head(&ha->scb_activelist, scb);
2795 else
2796 ha->num_ioctl--;
2797
2798 switch (ret) {
2799 case IPS_FAILURE:
2800 if (scb->scsi_cmd) {
2801 scb->scsi_cmd->result = DID_ERROR << 16;
2802 }
2803
2804 ips_freescb(ha, scb);
2805 break;
2806 case IPS_SUCCESS_IMM:
2807 ips_freescb(ha, scb);
2808 break;
2809 default:
2810 break;
2811 } /* end case */
2812
2813 }
2814
2815 /*
2816 * Send "Normal" I/O commands
2817 */
2818
2819 p = ha->scb_waitlist.head;
2820 while ((p) && (scb = ips_getscb(ha))) {
2821 if ((p->device->channel > 0)
2822 && (ha->
2823 dcdb_active[p->device->channel -
2824 1] & (1 << p->device->id))) {
2825 ips_freescb(ha, scb);
2826 p = (Scsi_Cmnd *) p->host_scribble;
2827 continue;
2828 }
2829
2830 q = p;
2831 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2832
2833 if (intr == IPS_INTR_ON)
2834 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); /* Unlock HA after command is taken off queue */
2835
2836 SC->result = DID_OK;
2837 SC->host_scribble = NULL;
2838
2839 memset(SC->sense_buffer, 0, sizeof (SC->sense_buffer));
2840
2841 scb->target_id = SC->device->id;
2842 scb->lun = SC->device->lun;
2843 scb->bus = SC->device->channel;
2844 scb->scsi_cmd = SC;
2845 scb->breakup = 0;
2846 scb->data_len = 0;
2847 scb->callback = ipsintr_done;
2848 scb->timeout = ips_cmd_timeout;
2849 memset(&scb->cmd, 0, 16);
2850
2851 /* copy in the CDB */
2852 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2853
2854 /* Now handle the data buffer */
2855 if (SC->use_sg) {
2856 struct scatterlist *sg;
2857 int i;
2858
2859 sg = SC->request_buffer;
2860 scb->sg_count = pci_map_sg(ha->pcidev, sg, SC->use_sg,
2861 scsi_to_pci_dma_dir(SC->
2862 sc_data_direction));
2863 scb->flags |= IPS_SCB_MAP_SG;
2864 for (i = 0; i < scb->sg_count; i++) {
2865 if (ips_fill_scb_sg_single
2866 (ha, sg_dma_address(&sg[i]), scb, i,
2867 sg_dma_len(&sg[i])) < 0)
2868 break;
2869 }
2870 scb->dcdb.transfer_length = scb->data_len;
2871 } else {
2872 if (SC->request_bufflen) {
2873 scb->data_busaddr =
2874 pci_map_single(ha->pcidev,
2875 SC->request_buffer,
2876 SC->request_bufflen,
2877 scsi_to_pci_dma_dir(SC->
2878 sc_data_direction));
2879 scb->flags |= IPS_SCB_MAP_SINGLE;
2880 ips_fill_scb_sg_single(ha, scb->data_busaddr,
2881 scb, 0,
2882 SC->request_bufflen);
2883 scb->dcdb.transfer_length = scb->data_len;
2884 } else {
2885 scb->data_busaddr = 0L;
2886 scb->sg_len = 0;
2887 scb->data_len = 0;
2888 scb->dcdb.transfer_length = 0;
2889 }
2890
2891 }
2892
2893 scb->dcdb.cmd_attribute =
2894 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2895
2896 /* Allow a WRITE BUFFER Command to Have no Data */
2897 /* This is Used by Tape Flash Utilites */
2898 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && (scb->data_len == 0))
2899 scb->dcdb.cmd_attribute = 0;
2900
2901 if (!(scb->dcdb.cmd_attribute & 0x3))
2902 scb->dcdb.transfer_length = 0;
2903
2904 if (scb->data_len >= IPS_MAX_XFER) {
2905 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2906 scb->dcdb.transfer_length = 0;
2907 }
2908 if (intr == IPS_INTR_ON)
2909 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2910
2911 ret = ips_send_cmd(ha, scb);
2912
2913 switch (ret) {
2914 case IPS_SUCCESS:
2915 ips_putq_scb_head(&ha->scb_activelist, scb);
2916 break;
2917 case IPS_FAILURE:
2918 if (scb->scsi_cmd) {
2919 scb->scsi_cmd->result = DID_ERROR << 16;
2920 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2921 }
2922
2923 if (scb->bus)
2924 ha->dcdb_active[scb->bus - 1] &=
2925 ~(1 << scb->target_id);
2926
2927 ips_freescb(ha, scb);
2928 break;
2929 case IPS_SUCCESS_IMM:
2930 if (scb->scsi_cmd)
2931 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2932
2933 if (scb->bus)
2934 ha->dcdb_active[scb->bus - 1] &=
2935 ~(1 << scb->target_id);
2936
2937 ips_freescb(ha, scb);
2938 break;
2939 default:
2940 break;
2941 } /* end case */
2942
2943 p = (Scsi_Cmnd *) p->host_scribble;
2944
2945 } /* end while */
2946
2947 if (intr == IPS_INTR_ON)
2948 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
2949 }
2950
2951 /****************************************************************************/
2952 /* */
2953 /* Routine Name: ips_putq_scb_head */
2954 /* */
2955 /* Routine Description: */
2956 /* */
2957 /* Add an item to the head of the queue */
2958 /* */
2959 /* ASSUMED to be called from within the HA lock */
2960 /* */
2961 /****************************************************************************/
2962 static void
2963 ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2964 {
2965 METHOD_TRACE("ips_putq_scb_head", 1);
2966
2967 if (!item)
2968 return;
2969
2970 item->q_next = queue->head;
2971 queue->head = item;
2972
2973 if (!queue->tail)
2974 queue->tail = item;
2975
2976 queue->count++;
2977 }
2978
2979 /****************************************************************************/
2980 /* */
2981 /* Routine Name: ips_removeq_scb_head */
2982 /* */
2983 /* Routine Description: */
2984 /* */
2985 /* Remove the head of the queue */
2986 /* */
2987 /* ASSUMED to be called from within the HA lock */
2988 /* */
2989 /****************************************************************************/
2990 static ips_scb_t *
2991 ips_removeq_scb_head(ips_scb_queue_t * queue)
2992 {
2993 ips_scb_t *item;
2994
2995 METHOD_TRACE("ips_removeq_scb_head", 1);
2996
2997 item = queue->head;
2998
2999 if (!item) {
3000 return (NULL);
3001 }
3002
3003 queue->head = item->q_next;
3004 item->q_next = NULL;
3005
3006 if (queue->tail == item)
3007 queue->tail = NULL;
3008
3009 queue->count--;
3010
3011 return (item);
3012 }
3013
3014 /****************************************************************************/
3015 /* */
3016 /* Routine Name: ips_removeq_scb */
3017 /* */
3018 /* Routine Description: */
3019 /* */
3020 /* Remove an item from a queue */
3021 /* */
3022 /* ASSUMED to be called from within the HA lock */
3023 /* */
3024 /****************************************************************************/
3025 static ips_scb_t *
3026 ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
3027 {
3028 ips_scb_t *p;
3029
3030 METHOD_TRACE("ips_removeq_scb", 1);
3031
3032 if (!item)
3033 return (NULL);
3034
3035 if (item == queue->head) {
3036 return (ips_removeq_scb_head(queue));
3037 }
3038
3039 p = queue->head;
3040
3041 while ((p) && (item != p->q_next))
3042 p = p->q_next;
3043
3044 if (p) {
3045 /* found a match */
3046 p->q_next = item->q_next;
3047
3048 if (!item->q_next)
3049 queue->tail = p;
3050
3051 item->q_next = NULL;
3052 queue->count--;
3053
3054 return (item);
3055 }
3056
3057 return (NULL);
3058 }
3059
3060 /****************************************************************************/
3061 /* */
3062 /* Routine Name: ips_putq_wait_tail */
3063 /* */
3064 /* Routine Description: */
3065 /* */
3066 /* Add an item to the tail of the queue */
3067 /* */
3068 /* ASSUMED to be called from within the HA lock */
3069 /* */
3070 /****************************************************************************/
3071 static void
3072 ips_putq_wait_tail(ips_wait_queue_t * queue, Scsi_Cmnd * item)
3073 {
3074 METHOD_TRACE("ips_putq_wait_tail", 1);
3075
3076 if (!item)
3077 return;
3078
3079 item->host_scribble = NULL;
3080
3081 if (queue->tail)
3082 queue->tail->host_scribble = (char *) item;
3083
3084 queue->tail = item;
3085
3086 if (!queue->head)
3087 queue->head = item;
3088
3089 queue->count++;
3090 }
3091
3092 /****************************************************************************/
3093 /* */
3094 /* Routine Name: ips_removeq_wait_head */
3095 /* */
3096 /* Routine Description: */
3097 /* */
3098 /* Remove the head of the queue */
3099 /* */
3100 /* ASSUMED to be called from within the HA lock */
3101 /* */
3102 /****************************************************************************/
3103 static Scsi_Cmnd *
3104 ips_removeq_wait_head(ips_wait_queue_t * queue)
3105 {
3106 Scsi_Cmnd *item;
3107
3108 METHOD_TRACE("ips_removeq_wait_head", 1);
3109
3110 item = queue->head;
3111
3112 if (!item) {
3113 return (NULL);
3114 }
3115
3116 queue->head = (Scsi_Cmnd *) item->host_scribble;
3117 item->host_scribble = NULL;
3118
3119 if (queue->tail == item)
3120 queue->tail = NULL;
3121
3122 queue->count--;
3123
3124 return (item);
3125 }
3126
3127 /****************************************************************************/
3128 /* */
3129 /* Routine Name: ips_removeq_wait */
3130 /* */
3131 /* Routine Description: */
3132 /* */
3133 /* Remove an item from a queue */
3134 /* */
3135 /* ASSUMED to be called from within the HA lock */
3136 /* */
3137 /****************************************************************************/
3138 static Scsi_Cmnd *
3139 ips_removeq_wait(ips_wait_queue_t * queue, Scsi_Cmnd * item)
3140 {
3141 Scsi_Cmnd *p;
3142
3143 METHOD_TRACE("ips_removeq_wait", 1);
3144
3145 if (!item)
3146 return (NULL);
3147
3148 if (item == queue->head) {
3149 return (ips_removeq_wait_head(queue));
3150 }
3151
3152 p = queue->head;
3153
3154 while ((p) && (item != (Scsi_Cmnd *) p->host_scribble))
3155 p = (Scsi_Cmnd *) p->host_scribble;
3156
3157 if (p) {
3158 /* found a match */
3159 p->host_scribble = item->host_scribble;
3160
3161 if (!item->host_scribble)
3162 queue->tail = p;
3163
3164 item->host_scribble = NULL;
3165 queue->count--;
3166
3167 return (item);
3168 }
3169
3170 return (NULL);
3171 }
3172
3173 /****************************************************************************/
3174 /* */
3175 /* Routine Name: ips_putq_copp_tail */
3176 /* */
3177 /* Routine Description: */
3178 /* */
3179 /* Add an item to the tail of the queue */
3180 /* */
3181 /* ASSUMED to be called from within the HA lock */
3182 /* */
3183 /****************************************************************************/
3184 static void
3185 ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3186 {
3187 METHOD_TRACE("ips_putq_copp_tail", 1);
3188
3189 if (!item)
3190 return;
3191
3192 item->next = NULL;
3193
3194 if (queue->tail)
3195 queue->tail->next = item;
3196
3197 queue->tail = item;
3198
3199 if (!queue->head)
3200 queue->head = item;
3201
3202 queue->count++;
3203 }
3204
3205 /****************************************************************************/
3206 /* */
3207 /* Routine Name: ips_removeq_copp_head */
3208 /* */
3209 /* Routine Description: */
3210 /* */
3211 /* Remove the head of the queue */
3212 /* */
3213 /* ASSUMED to be called from within the HA lock */
3214 /* */
3215 /****************************************************************************/
3216 static ips_copp_wait_item_t *
3217 ips_removeq_copp_head(ips_copp_queue_t * queue)
3218 {
3219 ips_copp_wait_item_t *item;
3220
3221 METHOD_TRACE("ips_removeq_copp_head", 1);
3222
3223 item = queue->head;
3224
3225 if (!item) {
3226 return (NULL);
3227 }
3228
3229 queue->head = item->next;
3230 item->next = NULL;
3231
3232 if (queue->tail == item)
3233 queue->tail = NULL;
3234
3235 queue->count--;
3236
3237 return (item);
3238 }
3239
3240 /****************************************************************************/
3241 /* */
3242 /* Routine Name: ips_removeq_copp */
3243 /* */
3244 /* Routine Description: */
3245 /* */
3246 /* Remove an item from a queue */
3247 /* */
3248 /* ASSUMED to be called from within the HA lock */
3249 /* */
3250 /****************************************************************************/
3251 static ips_copp_wait_item_t *
3252 ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3253 {
3254 ips_copp_wait_item_t *p;
3255
3256 METHOD_TRACE("ips_removeq_copp", 1);
3257
3258 if (!item)
3259 return (NULL);
3260
3261 if (item == queue->head) {
3262 return (ips_removeq_copp_head(queue));
3263 }
3264
3265 p = queue->head;
3266
3267 while ((p) && (item != p->next))
3268 p = p->next;
3269
3270 if (p) {
3271 /* found a match */
3272 p->next = item->next;
3273
3274 if (!item->next)
3275 queue->tail = p;
3276
3277 item->next = NULL;
3278 queue->count--;
3279
3280 return (item);
3281 }
3282
3283 return (NULL);
3284 }
3285
3286 /****************************************************************************/
3287 /* */
3288 /* Routine Name: ipsintr_blocking */
3289 /* */
3290 /* Routine Description: */
3291 /* */
3292 /* Finalize an interrupt for internal commands */
3293 /* */
3294 /****************************************************************************/
3295 static void
3296 ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3297 {
3298 METHOD_TRACE("ipsintr_blocking", 2);
3299
3300 ips_freescb(ha, scb);
3301 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3302 ha->waitflag = FALSE;
3303
3304 return;
3305 }
3306 }
3307
3308 /****************************************************************************/
3309 /* */
3310 /* Routine Name: ipsintr_done */
3311 /* */
3312 /* Routine Description: */
3313 /* */
3314 /* Finalize an interrupt for non-internal commands */
3315 /* */
3316 /****************************************************************************/
3317 static void
3318 ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3319 {
3320 METHOD_TRACE("ipsintr_done", 2);
3321
3322 if (!scb) {
3323 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3324 "Spurious interrupt; scb NULL.\n");
3325
3326 return;
3327 }
3328
3329 if (scb->scsi_cmd == NULL) {
3330 /* unexpected interrupt */
3331 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3332 "Spurious interrupt; scsi_cmd not set.\n");
3333
3334 return;
3335 }
3336
3337 ips_done(ha, scb);
3338 }
3339
3340 /****************************************************************************/
3341 /* */
3342 /* Routine Name: ips_done */
3343 /* */
3344 /* Routine Description: */
3345 /* */
3346 /* Do housekeeping on completed commands */
3347 /* ASSUMED to be called form within the request lock */
3348 /****************************************************************************/
3349 static void
3350 ips_done(ips_ha_t * ha, ips_scb_t * scb)
3351 {
3352 int ret;
3353
3354 METHOD_TRACE("ips_done", 1);
3355
3356 if (!scb)
3357 return;
3358
3359 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3360 ips_cleanup_passthru(ha, scb);
3361 ha->num_ioctl--;
3362 } else {
3363 /*
3364 * Check to see if this command had too much
3365 * data and had to be broke up. If so, queue
3366 * the rest of the data and continue.
3367 */
3368 if ((scb->breakup) || (scb->sg_break)) {
3369 /* we had a data breakup */
3370 scb->data_len = 0;
3371
3372 if (scb->sg_count) {
3373 /* S/G request */
3374 struct scatterlist *sg;
3375 int ips_sg_index = 0;
3376 int sg_dma_index;
3377
3378 sg = scb->scsi_cmd->request_buffer;
3379
3380 /* Spin forward to last dma chunk */
3381 sg_dma_index = scb->breakup;
3382
3383 /* Take care of possible partial on last chunk */
3384 ips_fill_scb_sg_single(ha,
3385 sg_dma_address(&sg
3386 [sg_dma_index]),
3387 scb, ips_sg_index++,
3388 sg_dma_len(&sg
3389 [sg_dma_index]));
3390
3391 for (; sg_dma_index < scb->sg_count;
3392 sg_dma_index++) {
3393 if (ips_fill_scb_sg_single
3394 (ha,
3395 sg_dma_address(&sg[sg_dma_index]),
3396 scb, ips_sg_index++,
3397 sg_dma_len(&sg[sg_dma_index])) < 0)
3398 break;
3399
3400 }
3401
3402 } else {
3403 /* Non S/G Request */
3404 (void) ips_fill_scb_sg_single(ha,
3405 scb->
3406 data_busaddr +
3407 (scb->sg_break *
3408 ha->max_xfer),
3409 scb, 0,
3410 scb->scsi_cmd->
3411 request_bufflen -
3412 (scb->sg_break *
3413 ha->max_xfer));
3414 }
3415
3416 scb->dcdb.transfer_length = scb->data_len;
3417 scb->dcdb.cmd_attribute |=
3418 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3419
3420 if (!(scb->dcdb.cmd_attribute & 0x3))
3421 scb->dcdb.transfer_length = 0;
3422
3423 if (scb->data_len >= IPS_MAX_XFER) {
3424 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3425 scb->dcdb.transfer_length = 0;
3426 }
3427
3428 ret = ips_send_cmd(ha, scb);
3429
3430 switch (ret) {
3431 case IPS_FAILURE:
3432 if (scb->scsi_cmd) {
3433 scb->scsi_cmd->result = DID_ERROR << 16;
3434 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3435 }
3436
3437 ips_freescb(ha, scb);
3438 break;
3439 case IPS_SUCCESS_IMM:
3440 if (scb->scsi_cmd) {
3441 scb->scsi_cmd->result = DID_ERROR << 16;
3442 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3443 }
3444
3445 ips_freescb(ha, scb);
3446 break;
3447 default:
3448 break;
3449 } /* end case */
3450
3451 return;
3452 }
3453 } /* end if passthru */
3454
3455 if (scb->bus) {
3456 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3457 }
3458
3459 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3460
3461 ips_freescb(ha, scb);
3462 }
3463
3464 /****************************************************************************/
3465 /* */
3466 /* Routine Name: ips_map_status */
3467 /* */
3468 /* Routine Description: */
3469 /* */
3470 /* Map Controller Error codes to Linux Error Codes */
3471 /* */
3472 /****************************************************************************/
3473 static int
3474 ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3475 {
3476 int errcode;
3477 int device_error;
3478 uint32_t transfer_len;
3479 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3480
3481 METHOD_TRACE("ips_map_status", 1);
3482
3483 if (scb->bus) {
3484 DEBUG_VAR(2,
3485 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3486 ips_name, ha->host_num,
3487 scb->scsi_cmd->device->channel,
3488 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3489 scb->basic_status, scb->extended_status,
3490 scb->extended_status ==
3491 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3492 scb->extended_status ==
3493 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3494 scb->extended_status ==
3495 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3496 }
3497
3498 /* default driver error */
3499 errcode = DID_ERROR;
3500 device_error = 0;
3501
3502 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3503 case IPS_CMD_TIMEOUT:
3504 errcode = DID_TIME_OUT;
3505 break;
3506
3507 case IPS_INVAL_OPCO:
3508 case IPS_INVAL_CMD_BLK:
3509 case IPS_INVAL_PARM_BLK:
3510 case IPS_LD_ERROR:
3511 case IPS_CMD_CMPLT_WERROR:
3512 break;
3513
3514 case IPS_PHYS_DRV_ERROR:
3515 switch (scb->extended_status) {
3516 case IPS_ERR_SEL_TO:
3517 if (scb->bus)
3518 errcode = DID_NO_CONNECT;
3519
3520 break;
3521
3522 case IPS_ERR_OU_RUN:
3523 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3524 (scb->cmd.dcdb.op_code ==
3525 IPS_CMD_EXTENDED_DCDB_SG)) {
3526 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3527 transfer_len = tapeDCDB->transfer_length;
3528 } else {
3529 transfer_len =
3530 (uint32_t) scb->dcdb.transfer_length;
3531 }
3532
3533 if ((scb->bus) && (transfer_len < scb->data_len)) {
3534 /* Underrun - set default to no error */
3535 errcode = DID_OK;
3536
3537 /* Restrict access to physical DASD */
3538 if ((scb->scsi_cmd->cmnd[0] == INQUIRY) &&
3539 ((((char *) scb->scsi_cmd->
3540 buffer)[0] & 0x1f) == TYPE_DISK)) {
3541 /* underflow -- no error */
3542 /* restrict access to physical DASD */
3543 errcode = DID_TIME_OUT;
3544 break;
3545 }
3546 } else
3547 errcode = DID_ERROR;
3548
3549 break;
3550
3551 case IPS_ERR_RECOVERY:
3552 /* don't fail recovered errors */
3553 if (scb->bus)
3554 errcode = DID_OK;
3555
3556 break;
3557
3558 case IPS_ERR_HOST_RESET:
3559 case IPS_ERR_DEV_RESET:
3560 errcode = DID_RESET;
3561 break;
3562
3563 case IPS_ERR_CKCOND:
3564 if (scb->bus) {
3565 if ((scb->cmd.dcdb.op_code ==
3566 IPS_CMD_EXTENDED_DCDB)
3567 || (scb->cmd.dcdb.op_code ==
3568 IPS_CMD_EXTENDED_DCDB_SG)) {
3569 tapeDCDB =
3570 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3571 memcpy(scb->scsi_cmd->sense_buffer,
3572 tapeDCDB->sense_info,
3573 sizeof (scb->scsi_cmd->
3574 sense_buffer));
3575 } else {
3576 memcpy(scb->scsi_cmd->sense_buffer,
3577 scb->dcdb.sense_info,
3578 sizeof (scb->scsi_cmd->
3579 sense_buffer));
3580 }
3581 device_error = 2; /* check condition */
3582 }
3583
3584 errcode = DID_OK;
3585
3586 break;
3587
3588 default:
3589 errcode = DID_ERROR;
3590 break;
3591
3592 } /* end switch */
3593 } /* end switch */
3594
3595 scb->scsi_cmd->result = device_error | (errcode << 16);
3596
3597 return (1);
3598 }
3599
3600 /****************************************************************************/
3601 /* */
3602 /* Routine Name: ips_send_wait */
3603 /* */
3604 /* Routine Description: */
3605 /* */
3606 /* Send a command to the controller and wait for it to return */
3607 /* */
3608 /* The FFDC Time Stamp use this function for the callback, but doesn't */
3609 /* actually need to wait. */
3610 /****************************************************************************/
3611 static int
3612 ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3613 {
3614 int ret;
3615
3616 METHOD_TRACE("ips_send_wait", 1);
3617
3618 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3619 ha->waitflag = TRUE;
3620 ha->cmd_in_progress = scb->cdb[0];
3621 }
3622 scb->callback = ipsintr_blocking;
3623 ret = ips_send_cmd(ha, scb);
3624
3625 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3626 return (ret);
3627
3628 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3629 ret = ips_wait(ha, timeout, intr);
3630
3631 return (ret);
3632 }
3633
3634 /****************************************************************************/
3635 /* */
3636 /* Routine Name: ips_scmd_buf_write */
3637 /* */
3638 /* Routine Description: */
3639 /* Write data to Scsi_Cmnd request_buffer at proper offsets */
3640 /****************************************************************************/
3641 static void
3642 ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data, unsigned
3643 int count)
3644 {
3645 if (scmd->use_sg) {
3646 int i;
3647 unsigned int min_cnt, xfer_cnt;
3648 char *cdata = (char *) data;
3649 struct scatterlist *sg = scmd->request_buffer;
3650 for (i = 0, xfer_cnt = 0;
3651 (i < scmd->use_sg) && (xfer_cnt < count); i++) {
3652 if (!IPS_SG_ADDRESS(&sg[i]))
3653 return;
3654 min_cnt = min(count - xfer_cnt, sg[i].length);
3655 memcpy(IPS_SG_ADDRESS(&sg[i]), &cdata[xfer_cnt],
3656 min_cnt);
3657 xfer_cnt += min_cnt;
3658 }
3659
3660 } else {
3661 unsigned int min_cnt = min(count, scmd->request_bufflen);
3662 memcpy(scmd->request_buffer, data, min_cnt);
3663 }
3664 }
3665
3666 /****************************************************************************/
3667 /* */
3668 /* Routine Name: ips_scmd_buf_read */
3669 /* */
3670 /* Routine Description: */
3671 /* Copy data from a Scsi_Cmnd to a new, linear buffer */
3672 /****************************************************************************/
3673 static void
3674 ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned
3675 int count)
3676 {
3677 if (scmd->use_sg) {
3678 int i;
3679 unsigned int min_cnt, xfer_cnt;
3680 char *cdata = (char *) data;
3681 struct scatterlist *sg = scmd->request_buffer;
3682 for (i = 0, xfer_cnt = 0;
3683 (i < scmd->use_sg) && (xfer_cnt < count); i++) {
3684 if (!IPS_SG_ADDRESS(&sg[i]))
3685 return;
3686 min_cnt = min(count - xfer_cnt, sg[i].length);
3687 memcpy(&cdata[xfer_cnt], IPS_SG_ADDRESS(&sg[i]),
3688 min_cnt);
3689 xfer_cnt += min_cnt;
3690 }
3691
3692 } else {
3693 unsigned int min_cnt = min(count, scmd->request_bufflen);
3694 memcpy(data, scmd->request_buffer, min_cnt);
3695 }
3696 }
3697
3698 /****************************************************************************/
3699 /* */
3700 /* Routine Name: ips_send_cmd */
3701 /* */
3702 /* Routine Description: */
3703 /* */
3704 /* Map SCSI commands to ServeRAID commands for logical drives */
3705 /* */
3706 /****************************************************************************/
3707 static int
3708 ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3709 {
3710 int ret;
3711 char *sp;
3712 int device_error;
3713 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3714 int TimeOut;
3715
3716 METHOD_TRACE("ips_send_cmd", 1);
3717
3718 ret = IPS_SUCCESS;
3719
3720 if (!scb->scsi_cmd) {
3721 /* internal command */
3722
3723 if (scb->bus > 0) {
3724 /* Controller commands can't be issued */
3725 /* to real devices -- fail them */
3726 if ((ha->waitflag == TRUE) &&
3727 (ha->cmd_in_progress == scb->cdb[0])) {
3728 ha->waitflag = FALSE;
3729 }
3730
3731 return (1);
3732 }
3733 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3734 /* command to logical bus -- interpret */
3735 ret = IPS_SUCCESS_IMM;
3736
3737 switch (scb->scsi_cmd->cmnd[0]) {
3738 case ALLOW_MEDIUM_REMOVAL:
3739 case REZERO_UNIT:
3740 case ERASE:
3741 case WRITE_FILEMARKS:
3742 case SPACE:
3743 scb->scsi_cmd->result = DID_ERROR << 16;
3744 break;
3745
3746 case START_STOP:
3747 scb->scsi_cmd->result = DID_OK << 16;
3748
3749 case TEST_UNIT_READY:
3750 case INQUIRY:
3751 if (scb->target_id == IPS_ADAPTER_ID) {
3752 /*
3753 * Either we have a TUR
3754 * or we have a SCSI inquiry
3755 */
3756 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3757 scb->scsi_cmd->result = DID_OK << 16;
3758
3759 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3760 IPS_SCSI_INQ_DATA inquiry;
3761
3762 memset(&inquiry, 0,
3763 sizeof (IPS_SCSI_INQ_DATA));
3764
3765 inquiry.DeviceType =
3766 IPS_SCSI_INQ_TYPE_PROCESSOR;
3767 inquiry.DeviceTypeQualifier =
3768 IPS_SCSI_INQ_LU_CONNECTED;
3769 inquiry.Version = IPS_SCSI_INQ_REV2;
3770 inquiry.ResponseDataFormat =
3771 IPS_SCSI_INQ_RD_REV2;
3772 inquiry.AdditionalLength = 31;
3773 inquiry.Flags[0] =
3774 IPS_SCSI_INQ_Address16;
3775 inquiry.Flags[1] =
3776 IPS_SCSI_INQ_WBus16 |
3777 IPS_SCSI_INQ_Sync;
3778 strncpy(inquiry.VendorId, "IBM ",
3779 8);
3780 strncpy(inquiry.ProductId,
3781 "SERVERAID ", 16);
3782 strncpy(inquiry.ProductRevisionLevel,
3783 "1.00", 4);
3784
3785 ips_scmd_buf_write(scb->scsi_cmd,
3786 &inquiry,
3787 sizeof (inquiry));
3788
3789 scb->scsi_cmd->result = DID_OK << 16;
3790 }
3791 } else {
3792 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3793 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3794 scb->cmd.logical_info.reserved = 0;
3795 scb->cmd.logical_info.reserved2 = 0;
3796 scb->data_len = sizeof (IPS_LD_INFO);
3797 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3798 scb->flags = 0;
3799 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3800 ret = IPS_SUCCESS;
3801 }
3802
3803 break;
3804
3805 case REQUEST_SENSE:
3806 ips_reqsen(ha, scb);
3807 scb->scsi_cmd->result = DID_OK << 16;
3808 break;
3809
3810 case READ_6:
3811 case WRITE_6:
3812 if (!scb->sg_len) {
3813 scb->cmd.basic_io.op_code =
3814 (scb->scsi_cmd->cmnd[0] ==
3815 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3816 scb->cmd.basic_io.enhanced_sg = 0;
3817 scb->cmd.basic_io.sg_addr =
3818 cpu_to_le32(scb->data_busaddr);
3819 } else {
3820 scb->cmd.basic_io.op_code =
3821 (scb->scsi_cmd->cmnd[0] ==
3822 READ_6) ? IPS_CMD_READ_SG :
3823 IPS_CMD_WRITE_SG;
3824 scb->cmd.basic_io.enhanced_sg =
3825 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3826 scb->cmd.basic_io.sg_addr =
3827 cpu_to_le32(scb->sg_busaddr);
3828 }
3829
3830 scb->cmd.basic_io.segment_4G = 0;
3831 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3832 scb->cmd.basic_io.log_drv = scb->target_id;
3833 scb->cmd.basic_io.sg_count = scb->sg_len;
3834
3835 if (scb->cmd.basic_io.lba)
3836 scb->cmd.basic_io.lba =
3837 cpu_to_le32(le32_to_cpu
3838 (scb->cmd.basic_io.lba) +
3839 le16_to_cpu(scb->cmd.basic_io.
3840 sector_count));
3841 else
3842 scb->cmd.basic_io.lba =
3843 (((scb->scsi_cmd->
3844 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3845 cmnd[2] << 8) |
3846 (scb->scsi_cmd->cmnd[3]));
3847
3848 scb->cmd.basic_io.sector_count =
3849 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3850
3851 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3852 scb->cmd.basic_io.sector_count =
3853 cpu_to_le16(256);
3854
3855 ret = IPS_SUCCESS;
3856 break;
3857
3858 case READ_10:
3859 case WRITE_10:
3860 if (!scb->sg_len) {
3861 scb->cmd.basic_io.op_code =
3862 (scb->scsi_cmd->cmnd[0] ==
3863 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3864 scb->cmd.basic_io.enhanced_sg = 0;
3865 scb->cmd.basic_io.sg_addr =
3866 cpu_to_le32(scb->data_busaddr);
3867 } else {
3868 scb->cmd.basic_io.op_code =
3869 (scb->scsi_cmd->cmnd[0] ==
3870 READ_10) ? IPS_CMD_READ_SG :
3871 IPS_CMD_WRITE_SG;
3872 scb->cmd.basic_io.enhanced_sg =
3873 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3874 scb->cmd.basic_io.sg_addr =
3875 cpu_to_le32(scb->sg_busaddr);
3876 }
3877
3878 scb->cmd.basic_io.segment_4G = 0;
3879 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3880 scb->cmd.basic_io.log_drv = scb->target_id;
3881 scb->cmd.basic_io.sg_count = scb->sg_len;
3882
3883 if (scb->cmd.basic_io.lba)
3884 scb->cmd.basic_io.lba =
3885 cpu_to_le32(le32_to_cpu
3886 (scb->cmd.basic_io.lba) +
3887 le16_to_cpu(scb->cmd.basic_io.
3888 sector_count));
3889 else
3890 scb->cmd.basic_io.lba =
3891 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3892 scsi_cmd->
3893 cmnd[3]
3894 << 16) |
3895 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3896 scsi_cmd->cmnd[5]);
3897
3898 scb->cmd.basic_io.sector_count =
3899 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3900
3901 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3902 /*
3903 * This is a null condition
3904 * we don't have to do anything
3905 * so just return
3906 */
3907 scb->scsi_cmd->result = DID_OK << 16;
3908 } else
3909 ret = IPS_SUCCESS;
3910
3911 break;
3912
3913 case RESERVE:
3914 case RELEASE:
3915 scb->scsi_cmd->result = DID_OK << 16;
3916 break;
3917
3918 case MODE_SENSE:
3919 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3920 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3921 scb->cmd.basic_io.segment_4G = 0;
3922 scb->cmd.basic_io.enhanced_sg = 0;
3923 scb->data_len = sizeof (*ha->enq);
3924 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3925 ret = IPS_SUCCESS;
3926 break;
3927
3928 case READ_CAPACITY:
3929 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3930 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3931 scb->cmd.logical_info.reserved = 0;
3932 scb->cmd.logical_info.reserved2 = 0;
3933 scb->cmd.logical_info.reserved3 = 0;
3934 scb->data_len = sizeof (IPS_LD_INFO);
3935 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3936 scb->flags = 0;
3937 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3938 ret = IPS_SUCCESS;
3939 break;
3940
3941 case SEND_DIAGNOSTIC:
3942 case REASSIGN_BLOCKS:
3943 case FORMAT_UNIT:
3944 case SEEK_10:
3945 case VERIFY:
3946 case READ_DEFECT_DATA:
3947 case READ_BUFFER:
3948 case WRITE_BUFFER:
3949 scb->scsi_cmd->result = DID_OK << 16;
3950 break;
3951
3952 default:
3953 /* Set the Return Info to appear like the Command was */
3954 /* attempted, a Check Condition occurred, and Sense */
3955 /* Data indicating an Invalid CDB OpCode is returned. */
3956 sp = (char *) scb->scsi_cmd->sense_buffer;
3957 memset(sp, 0, sizeof (scb->scsi_cmd->sense_buffer));
3958
3959 sp[0] = 0x70; /* Error Code */
3960 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3961 sp[7] = 0x0A; /* Additional Sense Length */
3962 sp[12] = 0x20; /* ASC = Invalid OpCode */
3963 sp[13] = 0x00; /* ASCQ */
3964
3965 device_error = 2; /* Indicate Check Condition */
3966 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3967 break;
3968 } /* end switch */
3969 }
3970 /* end if */
3971 if (ret == IPS_SUCCESS_IMM)
3972 return (ret);
3973
3974 /* setup DCDB */
3975 if (scb->bus > 0) {
3976
3977 /* If we already know the Device is Not there, no need to attempt a Command */
3978 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3979 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3980 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3981 return (IPS_SUCCESS_IMM);
3982 }
3983
3984 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3985 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3986 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3987 (unsigned long) &scb->
3988 dcdb -
3989 (unsigned long) scb);
3990 scb->cmd.dcdb.reserved = 0;
3991 scb->cmd.dcdb.reserved2 = 0;
3992 scb->cmd.dcdb.reserved3 = 0;
3993 scb->cmd.dcdb.segment_4G = 0;
3994 scb->cmd.dcdb.enhanced_sg = 0;
3995
3996 TimeOut = scb->scsi_cmd->timeout_per_command;
3997
3998 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3999 if (!scb->sg_len) {
4000 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
4001 } else {
4002 scb->cmd.dcdb.op_code =
4003 IPS_CMD_EXTENDED_DCDB_SG;
4004 scb->cmd.dcdb.enhanced_sg =
4005 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
4006 }
4007
4008 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
4009 tapeDCDB->device_address =
4010 ((scb->bus - 1) << 4) | scb->target_id;
4011 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
4012 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
4013
4014 if (TimeOut) {
4015 if (TimeOut < (10 * HZ))
4016 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
4017 else if (TimeOut < (60 * HZ))
4018 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
4019 else if (TimeOut < (1200 * HZ))
4020 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
4021 }
4022
4023 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
4024 tapeDCDB->reserved_for_LUN = 0;
4025 tapeDCDB->transfer_length = scb->data_len;
4026 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
4027 tapeDCDB->buffer_pointer =
4028 cpu_to_le32(scb->sg_busaddr);
4029 else
4030 tapeDCDB->buffer_pointer =
4031 cpu_to_le32(scb->data_busaddr);
4032 tapeDCDB->sg_count = scb->sg_len;
4033 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
4034 tapeDCDB->scsi_status = 0;
4035 tapeDCDB->reserved = 0;
4036 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
4037 scb->scsi_cmd->cmd_len);
4038 } else {
4039 if (!scb->sg_len) {
4040 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
4041 } else {
4042 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
4043 scb->cmd.dcdb.enhanced_sg =
4044 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
4045 }
4046
4047 scb->dcdb.device_address =
4048 ((scb->bus - 1) << 4) | scb->target_id;
4049 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
4050
4051 if (TimeOut) {
4052 if (TimeOut < (10 * HZ))
4053 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
4054 else if (TimeOut < (60 * HZ))
4055 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
4056 else if (TimeOut < (1200 * HZ))
4057 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
4058 }
4059
4060 scb->dcdb.transfer_length = scb->data_len;
4061 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
4062 scb->dcdb.transfer_length = 0;
4063 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
4064 scb->dcdb.buffer_pointer =
4065 cpu_to_le32(scb->sg_busaddr);
4066 else
4067 scb->dcdb.buffer_pointer =
4068 cpu_to_le32(scb->data_busaddr);
4069 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
4070 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
4071 scb->dcdb.sg_count = scb->sg_len;
4072 scb->dcdb.reserved = 0;
4073 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
4074 scb->scsi_cmd->cmd_len);
4075 scb->dcdb.scsi_status = 0;
4076 scb->dcdb.reserved2[0] = 0;
4077 scb->dcdb.reserved2[1] = 0;
4078 scb->dcdb.reserved2[2] = 0;
4079 }
4080 }
4081
4082 return ((*ha->func.issue) (ha, scb));
4083 }
4084
4085 /****************************************************************************/
4086 /* */
4087 /* Routine Name: ips_chk_status */
4088 /* */
4089 /* Routine Description: */
4090 /* */
4091 /* Check the status of commands to logical drives */
4092 /* Assumed to be called with the HA lock */
4093 /****************************************************************************/
4094 static void
4095 ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
4096 {
4097 ips_scb_t *scb;
4098 ips_stat_t *sp;
4099 uint8_t basic_status;
4100 uint8_t ext_status;
4101 int errcode;
4102
4103 METHOD_TRACE("ips_chkstatus", 1);
4104
4105 scb = &ha->scbs[pstatus->fields.command_id];
4106 scb->basic_status = basic_status =
4107 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
4108 scb->extended_status = ext_status = pstatus->fields.extended_status;
4109
4110 sp = &ha->sp;
4111 sp->residue_len = 0;
4112 sp->scb_addr = (void *) scb;
4113
4114 /* Remove the item from the active queue */
4115 ips_removeq_scb(&ha->scb_activelist, scb);
4116
4117 if (!scb->scsi_cmd)
4118 /* internal commands are handled in do_ipsintr */
4119 return;
4120
4121 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
4122 ips_name,
4123 ha->host_num,
4124 scb->cdb[0],
4125 scb->cmd.basic_io.command_id,
4126 scb->bus, scb->target_id, scb->lun);
4127
4128 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
4129 /* passthru - just returns the raw result */
4130 return;
4131
4132 errcode = DID_OK;
4133
4134 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
4135 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
4136
4137 if (scb->bus == 0) {
4138 if ((basic_status & IPS_GSC_STATUS_MASK) ==
4139 IPS_CMD_RECOVERED_ERROR) {
4140 DEBUG_VAR(1,
4141 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4142 ips_name, ha->host_num,
4143 scb->cmd.basic_io.op_code,
4144 basic_status, ext_status);
4145 }
4146
4147 switch (scb->scsi_cmd->cmnd[0]) {
4148 case ALLOW_MEDIUM_REMOVAL:
4149 case REZERO_UNIT:
4150 case ERASE:
4151 case WRITE_FILEMARKS:
4152 case SPACE:
4153 errcode = DID_ERROR;
4154 break;
4155
4156 case START_STOP:
4157 break;
4158
4159 case TEST_UNIT_READY:
4160 if (!ips_online(ha, scb)) {
4161 errcode = DID_TIME_OUT;
4162 }
4163 break;
4164
4165 case INQUIRY:
4166 if (ips_online(ha, scb)) {
4167 ips_inquiry(ha, scb);
4168 } else {
4169 errcode = DID_TIME_OUT;
4170 }
4171 break;
4172
4173 case REQUEST_SENSE:
4174 ips_reqsen(ha, scb);
4175 break;
4176
4177 case READ_6:
4178 case WRITE_6:
4179 case READ_10:
4180 case WRITE_10:
4181 case RESERVE:
4182 case RELEASE:
4183 break;
4184
4185 case MODE_SENSE:
4186 if (!ips_online(ha, scb)
4187 || !ips_msense(ha, scb)) {
4188 errcode = DID_ERROR;
4189 }
4190 break;
4191
4192 case READ_CAPACITY:
4193 if (ips_online(ha, scb))
4194 ips_rdcap(ha, scb);
4195 else {
4196 errcode = DID_TIME_OUT;
4197 }
4198 break;
4199
4200 case SEND_DIAGNOSTIC:
4201 case REASSIGN_BLOCKS:
4202 break;
4203
4204 case FORMAT_UNIT:
4205 errcode = DID_ERROR;
4206 break;
4207
4208 case SEEK_10:
4209 case VERIFY:
4210 case READ_DEFECT_DATA:
4211 case READ_BUFFER:
4212 case WRITE_BUFFER:
4213 break;
4214
4215 default:
4216 errcode = DID_ERROR;
4217 } /* end switch */
4218
4219 scb->scsi_cmd->result = errcode << 16;
4220 } else { /* bus == 0 */
4221 /* restrict access to physical drives */
4222 if ((scb->scsi_cmd->cmnd[0] == INQUIRY) &&
4223 ((((char *) scb->scsi_cmd->buffer)[0] & 0x1f) ==
4224 TYPE_DISK)) {
4225
4226 scb->scsi_cmd->result = DID_TIME_OUT << 16;
4227 }
4228 } /* else */
4229 } else { /* recovered error / success */
4230 if (scb->bus == 0) {
4231 DEBUG_VAR(1,
4232 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4233 ips_name, ha->host_num,
4234 scb->cmd.basic_io.op_code, basic_status,
4235 ext_status);
4236 }
4237
4238 ips_map_status(ha, scb, sp);
4239 } /* else */
4240 }
4241
4242 /****************************************************************************/
4243 /* */
4244 /* Routine Name: ips_online */
4245 /* */
4246 /* Routine Description: */
4247 /* */
4248 /* Determine if a logical drive is online */
4249 /* */
4250 /****************************************************************************/
4251 static int
4252 ips_online(ips_ha_t * ha, ips_scb_t * scb)
4253 {
4254 METHOD_TRACE("ips_online", 1);
4255
4256 if (scb->target_id >= IPS_MAX_LD)
4257 return (0);
4258
4259 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4260 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4261 return (0);
4262 }
4263
4264 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4265 IPS_LD_OFFLINE
4266 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4267 IPS_LD_FREE
4268 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4269 IPS_LD_CRS
4270 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4271 IPS_LD_SYS)
4272 return (1);
4273 else
4274 return (0);
4275 }
4276
4277 /****************************************************************************/
4278 /* */
4279 /* Routine Name: ips_inquiry */
4280 /* */
4281 /* Routine Description: */
4282 /* */
4283 /* Simulate an inquiry command to a logical drive */
4284 /* */
4285 /****************************************************************************/
4286 static int
4287 ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4288 {
4289 IPS_SCSI_INQ_DATA inquiry;
4290
4291 METHOD_TRACE("ips_inquiry", 1);
4292
4293 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4294
4295 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4296 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4297 inquiry.Version = IPS_SCSI_INQ_REV2;
4298 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4299 inquiry.AdditionalLength = 31;
4300 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4301 inquiry.Flags[1] =
4302 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4303 strncpy(inquiry.VendorId, "IBM ", 8);
4304 strncpy(inquiry.ProductId, "SERVERAID ", 16);
4305 strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
4306
4307 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4308
4309 return (1);
4310 }
4311
4312 /****************************************************************************/
4313 /* */
4314 /* Routine Name: ips_rdcap */
4315 /* */
4316 /* Routine Description: */
4317 /* */
4318 /* Simulate a read capacity command to a logical drive */
4319 /* */
4320 /****************************************************************************/
4321 static int
4322 ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4323 {
4324 IPS_SCSI_CAPACITY cap;
4325
4326 METHOD_TRACE("ips_rdcap", 1);
4327
4328 if (scb->scsi_cmd->bufflen < 8)
4329 return (0);
4330
4331 cap.lba =
4332 cpu_to_be32(le32_to_cpu
4333 (ha->logical_drive_info->
4334 drive_info[scb->target_id].sector_count) - 1);
4335 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4336
4337 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4338
4339 return (1);
4340 }
4341
4342 /****************************************************************************/
4343 /* */
4344 /* Routine Name: ips_msense */
4345 /* */
4346 /* Routine Description: */
4347 /* */
4348 /* Simulate a mode sense command to a logical drive */
4349 /* */
4350 /****************************************************************************/
4351 static int
4352 ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4353 {
4354 uint16_t heads;
4355 uint16_t sectors;
4356 uint32_t cylinders;
4357 IPS_SCSI_MODE_PAGE_DATA mdata;
4358
4359 METHOD_TRACE("ips_msense", 1);
4360
4361 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4362 (ha->enq->ucMiscFlag & 0x8) == 0) {
4363 heads = IPS_NORM_HEADS;
4364 sectors = IPS_NORM_SECTORS;
4365 } else {
4366 heads = IPS_COMP_HEADS;
4367 sectors = IPS_COMP_SECTORS;
4368 }
4369
4370 cylinders =
4371 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4372 1) / (heads * sectors);
4373
4374 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4375
4376 mdata.hdr.BlockDescLength = 8;
4377
4378 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4379 case 0x03: /* page 3 */
4380 mdata.pdata.pg3.PageCode = 3;
4381 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4382 mdata.hdr.DataLength =
4383 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4384 mdata.pdata.pg3.TracksPerZone = 0;
4385 mdata.pdata.pg3.AltSectorsPerZone = 0;
4386 mdata.pdata.pg3.AltTracksPerZone = 0;
4387 mdata.pdata.pg3.AltTracksPerVolume = 0;
4388 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4389 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4390 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4391 mdata.pdata.pg3.TrackSkew = 0;
4392 mdata.pdata.pg3.CylinderSkew = 0;
4393 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4394 break;
4395
4396 case 0x4:
4397 mdata.pdata.pg4.PageCode = 4;
4398 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4399 mdata.hdr.DataLength =
4400 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4401 mdata.pdata.pg4.CylindersHigh =
4402 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4403 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4404 mdata.pdata.pg4.Heads = heads;
4405 mdata.pdata.pg4.WritePrecompHigh = 0;
4406 mdata.pdata.pg4.WritePrecompLow = 0;
4407 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4408 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4409 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4410 mdata.pdata.pg4.LandingZoneHigh = 0;
4411 mdata.pdata.pg4.LandingZoneLow = 0;
4412 mdata.pdata.pg4.flags = 0;
4413 mdata.pdata.pg4.RotationalOffset = 0;
4414 mdata.pdata.pg4.MediumRotationRate = 0;
4415 break;
4416 case 0x8:
4417 mdata.pdata.pg8.PageCode = 8;
4418 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4419 mdata.hdr.DataLength =
4420 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4421 /* everything else is left set to 0 */
4422 break;
4423
4424 default:
4425 return (0);
4426 } /* end switch */
4427
4428 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4429
4430 return (1);
4431 }
4432
4433 /****************************************************************************/
4434 /* */
4435 /* Routine Name: ips_reqsen */
4436 /* */
4437 /* Routine Description: */
4438 /* */
4439 /* Simulate a request sense command to a logical drive */
4440 /* */
4441 /****************************************************************************/
4442 static int
4443 ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4444 {
4445 IPS_SCSI_REQSEN reqsen;
4446
4447 METHOD_TRACE("ips_reqsen", 1);
4448
4449 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4450
4451 reqsen.ResponseCode =
4452 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4453 reqsen.AdditionalLength = 10;
4454 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4455 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4456
4457 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4458
4459 return (1);
4460 }
4461
4462 /****************************************************************************/
4463 /* */
4464 /* Routine Name: ips_free */
4465 /* */
4466 /* Routine Description: */
4467 /* */
4468 /* Free any allocated space for this controller */
4469 /* */
4470 /****************************************************************************/
4471 static void
4472 ips_free(ips_ha_t * ha)
4473 {
4474
4475 METHOD_TRACE("ips_free", 1);
4476
4477 if (ha) {
4478 if (ha->enq) {
4479 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4480 ha->enq, ha->enq_busaddr);
4481 ha->enq = NULL;
4482 }
4483
4484 if (ha->conf) {
4485 kfree(ha->conf);
4486 ha->conf = NULL;
4487 }
4488
4489 if (ha->adapt) {
4490 pci_free_consistent(ha->pcidev,
4491 sizeof (IPS_ADAPTER) +
4492 sizeof (IPS_IO_CMD), ha->adapt,
4493 ha->adapt->hw_status_start);
4494 ha->adapt = NULL;
4495 }
4496
4497 if (ha->logical_drive_info) {
4498 pci_free_consistent(ha->pcidev,
4499 sizeof (IPS_LD_INFO),
4500 ha->logical_drive_info,
4501 ha->logical_drive_info_dma_addr);
4502 ha->logical_drive_info = NULL;
4503 }
4504
4505 if (ha->nvram) {
4506 kfree(ha->nvram);
4507 ha->nvram = NULL;
4508 }
4509
4510 if (ha->subsys) {
4511 kfree(ha->subsys);
4512 ha->subsys = NULL;
4513 }
4514
4515 if (ha->ioctl_data) {
4516 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4517 ha->ioctl_data, ha->ioctl_busaddr);
4518 ha->ioctl_data = NULL;
4519 ha->ioctl_datasize = 0;
4520 ha->ioctl_len = 0;
4521 }
4522 ips_deallocatescbs(ha, ha->max_cmds);
4523
4524 /* free memory mapped (if applicable) */
4525 if (ha->mem_ptr) {
4526 iounmap(ha->ioremap_ptr);
4527 ha->ioremap_ptr = NULL;
4528 ha->mem_ptr = NULL;
4529 }
4530
4531 if (ha->mem_addr)
4532 release_mem_region(ha->mem_addr, ha->mem_len);
4533 ha->mem_addr = 0;
4534
4535 }
4536 }
4537
4538 /****************************************************************************/
4539 /* */
4540 /* Routine Name: ips_deallocatescbs */
4541 /* */
4542 /* Routine Description: */
4543 /* */
4544 /* Free the command blocks */
4545 /* */
4546 /****************************************************************************/
4547 static int
4548 ips_deallocatescbs(ips_ha_t * ha, int cmds)
4549 {
4550 if (ha->scbs) {
4551 pci_free_consistent(ha->pcidev,
4552 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4553 ha->scbs->sg_list.list,
4554 ha->scbs->sg_busaddr);
4555 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4556 ha->scbs, ha->scbs->scb_busaddr);
4557 ha->scbs = NULL;
4558 } /* end if */
4559 return 1;
4560 }
4561
4562 /****************************************************************************/
4563 /* */
4564 /* Routine Name: ips_allocatescbs */
4565 /* */
4566 /* Routine Description: */
4567 /* */
4568 /* Allocate the command blocks */
4569 /* */
4570 /****************************************************************************/
4571 static int
4572 ips_allocatescbs(ips_ha_t * ha)
4573 {
4574 ips_scb_t *scb_p;
4575 IPS_SG_LIST ips_sg;
4576 int i;
4577 dma_addr_t command_dma, sg_dma;
4578
4579 METHOD_TRACE("ips_allocatescbs", 1);
4580
4581 /* Allocate memory for the SCBs */
4582 ha->scbs =
4583 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4584 &command_dma);
4585 if (ha->scbs == NULL)
4586 return 0;
4587 ips_sg.list =
4588 pci_alloc_consistent(ha->pcidev,
4589 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4590 ha->max_cmds, &sg_dma);
4591 if (ips_sg.list == NULL) {
4592 pci_free_consistent(ha->pcidev,
4593 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4594 command_dma);
4595 return 0;
4596 }
4597
4598 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4599
4600 for (i = 0; i < ha->max_cmds; i++) {
4601 scb_p = &ha->scbs[i];
4602 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4603 /* set up S/G list */
4604 if (IPS_USE_ENH_SGLIST(ha)) {
4605 scb_p->sg_list.enh_list =
4606 ips_sg.enh_list + i * IPS_MAX_SG;
4607 scb_p->sg_busaddr =
4608 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4609 } else {
4610 scb_p->sg_list.std_list =
4611 ips_sg.std_list + i * IPS_MAX_SG;
4612 scb_p->sg_busaddr =
4613 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4614 }
4615
4616 /* add to the free list */
4617 if (i < ha->max_cmds - 1) {
4618 scb_p->q_next = ha->scb_freelist;
4619 ha->scb_freelist = scb_p;
4620 }
4621 }
4622
4623 /* success */
4624 return (1);
4625 }
4626
4627 /****************************************************************************/
4628 /* */
4629 /* Routine Name: ips_init_scb */
4630 /* */
4631 /* Routine Description: */
4632 /* */
4633 /* Initialize a CCB to default values */
4634 /* */
4635 /****************************************************************************/
4636 static void
4637 ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4638 {
4639 IPS_SG_LIST sg_list;
4640 uint32_t cmd_busaddr, sg_busaddr;
4641 METHOD_TRACE("ips_init_scb", 1);
4642
4643 if (scb == NULL)
4644 return;
4645
4646 sg_list.list = scb->sg_list.list;
4647 cmd_busaddr = scb->scb_busaddr;
4648 sg_busaddr = scb->sg_busaddr;
4649 /* zero fill */
4650 memset(scb, 0, sizeof (ips_scb_t));
4651 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4652
4653 /* Initialize dummy command bucket */
4654 ha->dummy->op_code = 0xFF;
4655 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4656 + sizeof (IPS_ADAPTER));
4657 ha->dummy->command_id = IPS_MAX_CMDS;
4658
4659 /* set bus address of scb */
4660 scb->scb_busaddr = cmd_busaddr;
4661 scb->sg_busaddr = sg_busaddr;
4662 scb->sg_list.list = sg_list.list;
4663
4664 /* Neptune Fix */
4665 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4666 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4667 + sizeof (IPS_ADAPTER));
4668 }
4669
4670 /****************************************************************************/
4671 /* */
4672 /* Routine Name: ips_get_scb */
4673 /* */
4674 /* Routine Description: */
4675 /* */
4676 /* Initialize a CCB to default values */
4677 /* */
4678 /* ASSUMED to be callled from within a lock */
4679 /* */
4680 /****************************************************************************/
4681 static ips_scb_t *
4682 ips_getscb(ips_ha_t * ha)
4683 {
4684 ips_scb_t *scb;
4685
4686 METHOD_TRACE("ips_getscb", 1);
4687
4688 if ((scb = ha->scb_freelist) == NULL) {
4689
4690 return (NULL);
4691 }
4692
4693 ha->scb_freelist = scb->q_next;
4694 scb->flags = 0;
4695 scb->q_next = NULL;
4696
4697 ips_init_scb(ha, scb);
4698
4699 return (scb);
4700 }
4701
4702 /****************************************************************************/
4703 /* */
4704 /* Routine Name: ips_free_scb */
4705 /* */
4706 /* Routine Description: */
4707 /* */
4708 /* Return an unused CCB back to the free list */
4709 /* */
4710 /* ASSUMED to be called from within a lock */
4711 /* */
4712 /****************************************************************************/
4713 static void
4714 ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4715 {
4716
4717 METHOD_TRACE("ips_freescb", 1);
4718 if (scb->flags & IPS_SCB_MAP_SG)
4719 pci_unmap_sg(ha->pcidev, scb->scsi_cmd->request_buffer,
4720 scb->scsi_cmd->use_sg, IPS_DMA_DIR(scb));
4721 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4722 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4723 IPS_DMA_DIR(scb));
4724
4725 /* check to make sure this is not our "special" scb */
4726 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4727 scb->q_next = ha->scb_freelist;
4728 ha->scb_freelist = scb;
4729 }
4730 }
4731
4732 /****************************************************************************/
4733 /* */
4734 /* Routine Name: ips_isinit_copperhead */
4735 /* */
4736 /* Routine Description: */
4737 /* */
4738 /* Is controller initialized ? */
4739 /* */
4740 /****************************************************************************/
4741 static int
4742 ips_isinit_copperhead(ips_ha_t * ha)
4743 {
4744 uint8_t scpr;
4745 uint8_t isr;
4746
4747 METHOD_TRACE("ips_isinit_copperhead", 1);
4748
4749 isr = inb(ha->io_addr + IPS_REG_HISR);
4750 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4751
4752 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4753 return (0);
4754 else
4755 return (1);
4756 }
4757
4758 /****************************************************************************/
4759 /* */
4760 /* Routine Name: ips_isinit_copperhead_memio */
4761 /* */
4762 /* Routine Description: */
4763 /* */
4764 /* Is controller initialized ? */
4765 /* */
4766 /****************************************************************************/
4767 static int
4768 ips_isinit_copperhead_memio(ips_ha_t * ha)
4769 {
4770 uint8_t isr = 0;
4771 uint8_t scpr;
4772
4773 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4774
4775 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4776 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4777
4778 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4779 return (0);
4780 else
4781 return (1);
4782 }
4783
4784 /****************************************************************************/
4785 /* */
4786 /* Routine Name: ips_isinit_morpheus */
4787 /* */
4788 /* Routine Description: */
4789 /* */
4790 /* Is controller initialized ? */
4791 /* */
4792 /****************************************************************************/
4793 static int
4794 ips_isinit_morpheus(ips_ha_t * ha)
4795 {
4796 uint32_t post;
4797 uint32_t bits;
4798
4799 METHOD_TRACE("ips_is_init_morpheus", 1);
4800
4801 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4802 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4803
4804 if (post == 0)
4805 return (0);
4806 else if (bits & 0x3)
4807 return (0);
4808 else
4809 return (1);
4810 }
4811
4812 /****************************************************************************/
4813 /* */
4814 /* Routine Name: ips_enable_int_copperhead */
4815 /* */
4816 /* Routine Description: */
4817 /* Turn on interrupts */
4818 /* */
4819 /****************************************************************************/
4820 static void
4821 ips_enable_int_copperhead(ips_ha_t * ha)
4822 {
4823 METHOD_TRACE("ips_enable_int_copperhead", 1);
4824
4825 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4826 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4827 }
4828
4829 /****************************************************************************/
4830 /* */
4831 /* Routine Name: ips_enable_int_copperhead_memio */
4832 /* */
4833 /* Routine Description: */
4834 /* Turn on interrupts */
4835 /* */
4836 /****************************************************************************/
4837 static void
4838 ips_enable_int_copperhead_memio(ips_ha_t * ha)
4839 {
4840 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4841
4842 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4843 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4844 }
4845
4846 /****************************************************************************/
4847 /* */
4848 /* Routine Name: ips_enable_int_morpheus */
4849 /* */
4850 /* Routine Description: */
4851 /* Turn on interrupts */
4852 /* */
4853 /****************************************************************************/
4854 static void
4855 ips_enable_int_morpheus(ips_ha_t * ha)
4856 {
4857 uint32_t Oimr;
4858
4859 METHOD_TRACE("ips_enable_int_morpheus", 1);
4860
4861 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4862 Oimr &= ~0x08;
4863 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4864 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4865 }
4866
4867 /****************************************************************************/
4868 /* */
4869 /* Routine Name: ips_init_copperhead */
4870 /* */
4871 /* Routine Description: */
4872 /* */
4873 /* Initialize a copperhead controller */
4874 /* */
4875 /****************************************************************************/
4876 static int
4877 ips_init_copperhead(ips_ha_t * ha)
4878 {
4879 uint8_t Isr;
4880 uint8_t Cbsp;
4881 uint8_t PostByte[IPS_MAX_POST_BYTES];
4882 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4883 int i, j;
4884
4885 METHOD_TRACE("ips_init_copperhead", 1);
4886
4887 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4888 for (j = 0; j < 45; j++) {
4889 Isr = inb(ha->io_addr + IPS_REG_HISR);
4890 if (Isr & IPS_BIT_GHI)
4891 break;
4892
4893 /* Delay for 1 Second */
4894 MDELAY(IPS_ONE_SEC);
4895 }
4896
4897 if (j >= 45)
4898 /* error occurred */
4899 return (0);
4900
4901 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4902 outb(Isr, ha->io_addr + IPS_REG_HISR);
4903 }
4904
4905 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4906 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4907 "reset controller fails (post status %x %x).\n",
4908 PostByte[0], PostByte[1]);
4909
4910 return (0);
4911 }
4912
4913 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4914 for (j = 0; j < 240; j++) {
4915 Isr = inb(ha->io_addr + IPS_REG_HISR);
4916 if (Isr & IPS_BIT_GHI)
4917 break;
4918
4919 /* Delay for 1 Second */
4920 MDELAY(IPS_ONE_SEC);
4921 }
4922
4923 if (j >= 240)
4924 /* error occurred */
4925 return (0);
4926
4927 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4928 outb(Isr, ha->io_addr + IPS_REG_HISR);
4929 }
4930
4931 for (i = 0; i < 240; i++) {
4932 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4933
4934 if ((Cbsp & IPS_BIT_OP) == 0)
4935 break;
4936
4937 /* Delay for 1 Second */
4938 MDELAY(IPS_ONE_SEC);
4939 }
4940
4941 if (i >= 240)
4942 /* reset failed */
4943 return (0);
4944
4945 /* setup CCCR */
4946 outl(cpu_to_le32(0x1010), ha->io_addr + IPS_REG_CCCR);
4947
4948 /* Enable busmastering */
4949 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4950
4951 if (ha->revision_id == IPS_REVID_TROMBONE64)
4952 /* fix for anaconda64 */
4953 outl(0, ha->io_addr + IPS_REG_NDAE);
4954
4955 /* Enable interrupts */
4956 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4957
4958 return (1);
4959 }
4960
4961 /****************************************************************************/
4962 /* */
4963 /* Routine Name: ips_init_copperhead_memio */
4964 /* */
4965 /* Routine Description: */
4966 /* */
4967 /* Initialize a copperhead controller with memory mapped I/O */
4968 /* */
4969 /****************************************************************************/
4970 static int
4971 ips_init_copperhead_memio(ips_ha_t * ha)
4972 {
4973 uint8_t Isr = 0;
4974 uint8_t Cbsp;
4975 uint8_t PostByte[IPS_MAX_POST_BYTES];
4976 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4977 int i, j;
4978
4979 METHOD_TRACE("ips_init_copperhead_memio", 1);
4980
4981 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4982 for (j = 0; j < 45; j++) {
4983 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4984 if (Isr & IPS_BIT_GHI)
4985 break;
4986
4987 /* Delay for 1 Second */
4988 MDELAY(IPS_ONE_SEC);
4989 }
4990
4991 if (j >= 45)
4992 /* error occurred */
4993 return (0);
4994
4995 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4996 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4997 }
4998
4999 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
5000 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5001 "reset controller fails (post status %x %x).\n",
5002 PostByte[0], PostByte[1]);
5003
5004 return (0);
5005 }
5006
5007 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
5008 for (j = 0; j < 240; j++) {
5009 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5010 if (Isr & IPS_BIT_GHI)
5011 break;
5012
5013 /* Delay for 1 Second */
5014 MDELAY(IPS_ONE_SEC);
5015 }
5016
5017 if (j >= 240)
5018 /* error occurred */
5019 return (0);
5020
5021 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
5022 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5023 }
5024
5025 for (i = 0; i < 240; i++) {
5026 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
5027
5028 if ((Cbsp & IPS_BIT_OP) == 0)
5029 break;
5030
5031 /* Delay for 1 Second */
5032 MDELAY(IPS_ONE_SEC);
5033 }
5034
5035 if (i >= 240)
5036 /* error occurred */
5037 return (0);
5038
5039 /* setup CCCR */
5040 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
5041
5042 /* Enable busmastering */
5043 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
5044
5045 if (ha->revision_id == IPS_REVID_TROMBONE64)
5046 /* fix for anaconda64 */
5047 writel(0, ha->mem_ptr + IPS_REG_NDAE);
5048
5049 /* Enable interrupts */
5050 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
5051
5052 /* if we get here then everything went OK */
5053 return (1);
5054 }
5055
5056 /****************************************************************************/
5057 /* */
5058 /* Routine Name: ips_init_morpheus */
5059 /* */
5060 /* Routine Description: */
5061 /* */
5062 /* Initialize a morpheus controller */
5063 /* */
5064 /****************************************************************************/
5065 static int
5066 ips_init_morpheus(ips_ha_t * ha)
5067 {
5068 uint32_t Post;
5069 uint32_t Config;
5070 uint32_t Isr;
5071 uint32_t Oimr;
5072 int i;
5073
5074 METHOD_TRACE("ips_init_morpheus", 1);
5075
5076 /* Wait up to 45 secs for Post */
5077 for (i = 0; i < 45; i++) {
5078 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5079
5080 if (Isr & IPS_BIT_I960_MSG0I)
5081 break;
5082
5083 /* Delay for 1 Second */
5084 MDELAY(IPS_ONE_SEC);
5085 }
5086
5087 if (i >= 45) {
5088 /* error occurred */
5089 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5090 "timeout waiting for post.\n");
5091
5092 return (0);
5093 }
5094
5095 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5096
5097 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
5098 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5099 "Flashing Battery PIC, Please wait ...\n");
5100
5101 /* Clear the interrupt bit */
5102 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5103 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5104
5105 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
5106 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5107 if (Post != 0x4F00)
5108 break;
5109 /* Delay for 1 Second */
5110 MDELAY(IPS_ONE_SEC);
5111 }
5112
5113 if (i >= 120) {
5114 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5115 "timeout waiting for Battery PIC Flash\n");
5116 return (0);
5117 }
5118
5119 }
5120
5121 /* Clear the interrupt bit */
5122 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5123 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5124
5125 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
5126 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5127 "reset controller fails (post status %x).\n", Post);
5128
5129 return (0);
5130 }
5131
5132 /* Wait up to 240 secs for config bytes */
5133 for (i = 0; i < 240; i++) {
5134 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5135
5136 if (Isr & IPS_BIT_I960_MSG1I)
5137 break;
5138
5139 /* Delay for 1 Second */
5140 MDELAY(IPS_ONE_SEC);
5141 }
5142
5143 if (i >= 240) {
5144 /* error occurred */
5145 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5146 "timeout waiting for config.\n");
5147
5148 return (0);
5149 }
5150
5151 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
5152
5153 /* Clear interrupt bit */
5154 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
5155 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5156
5157 /* Turn on the interrupts */
5158 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
5159 Oimr &= ~0x8;
5160 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
5161
5162 /* if we get here then everything went OK */
5163
5164 /* Since we did a RESET, an EraseStripeLock may be needed */
5165 if (Post == 0xEF10) {
5166 if ((Config == 0x000F) || (Config == 0x0009))
5167 ha->requires_esl = 1;
5168 }
5169
5170 return (1);
5171 }
5172
5173 /****************************************************************************/
5174 /* */
5175 /* Routine Name: ips_reset_copperhead */
5176 /* */
5177 /* Routine Description: */
5178 /* */
5179 /* Reset the controller */
5180 /* */
5181 /****************************************************************************/
5182 static int
5183 ips_reset_copperhead(ips_ha_t * ha)
5184 {
5185 int reset_counter;
5186
5187 METHOD_TRACE("ips_reset_copperhead", 1);
5188
5189 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5190 ips_name, ha->host_num, ha->io_addr, ha->irq);
5191
5192 reset_counter = 0;
5193
5194 while (reset_counter < 2) {
5195 reset_counter++;
5196
5197 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5198
5199 /* Delay for 1 Second */
5200 MDELAY(IPS_ONE_SEC);
5201
5202 outb(0, ha->io_addr + IPS_REG_SCPR);
5203
5204 /* Delay for 1 Second */
5205 MDELAY(IPS_ONE_SEC);
5206
5207 if ((*ha->func.init) (ha))
5208 break;
5209 else if (reset_counter >= 2) {
5210
5211 return (0);
5212 }
5213 }
5214
5215 return (1);
5216 }
5217
5218 /****************************************************************************/
5219 /* */
5220 /* Routine Name: ips_reset_copperhead_memio */
5221 /* */
5222 /* Routine Description: */
5223 /* */
5224 /* Reset the controller */
5225 /* */
5226 /****************************************************************************/
5227 static int
5228 ips_reset_copperhead_memio(ips_ha_t * ha)
5229 {
5230 int reset_counter;
5231
5232 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5233
5234 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5235 ips_name, ha->host_num, ha->mem_addr, ha->irq);
5236
5237 reset_counter = 0;
5238
5239 while (reset_counter < 2) {
5240 reset_counter++;
5241
5242 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5243
5244 /* Delay for 1 Second */
5245 MDELAY(IPS_ONE_SEC);
5246
5247 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5248
5249 /* Delay for 1 Second */
5250 MDELAY(IPS_ONE_SEC);
5251
5252 if ((*ha->func.init) (ha))
5253 break;
5254 else if (reset_counter >= 2) {
5255
5256 return (0);
5257 }
5258 }
5259
5260 return (1);
5261 }
5262
5263 /****************************************************************************/
5264 /* */
5265 /* Routine Name: ips_reset_morpheus */
5266 /* */
5267 /* Routine Description: */
5268 /* */
5269 /* Reset the controller */
5270 /* */
5271 /****************************************************************************/
5272 static int
5273 ips_reset_morpheus(ips_ha_t * ha)
5274 {
5275 int reset_counter;
5276 uint8_t junk;
5277
5278 METHOD_TRACE("ips_reset_morpheus", 1);
5279
5280 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5281 ips_name, ha->host_num, ha->mem_addr, ha->irq);
5282
5283 reset_counter = 0;
5284
5285 while (reset_counter < 2) {
5286 reset_counter++;
5287
5288 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5289
5290 /* Delay for 5 Seconds */
5291 MDELAY(5 * IPS_ONE_SEC);
5292
5293 /* Do a PCI config read to wait for adapter */
5294 pci_read_config_byte(ha->pcidev, 4, &junk);
5295
5296 if ((*ha->func.init) (ha))
5297 break;
5298 else if (reset_counter >= 2) {
5299
5300 return (0);
5301 }
5302 }
5303
5304 return (1);
5305 }
5306
5307 /****************************************************************************/
5308 /* */
5309 /* Routine Name: ips_statinit */
5310 /* */
5311 /* Routine Description: */
5312 /* */
5313 /* Initialize the status queues on the controller */
5314 /* */
5315 /****************************************************************************/
5316 static void
5317 ips_statinit(ips_ha_t * ha)
5318 {
5319 uint32_t phys_status_start;
5320
5321 METHOD_TRACE("ips_statinit", 1);
5322
5323 ha->adapt->p_status_start = ha->adapt->status;
5324 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5325 ha->adapt->p_status_tail = ha->adapt->status;
5326
5327 phys_status_start = ha->adapt->hw_status_start;
5328 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQSR);
5329 outl(cpu_to_le32(phys_status_start + IPS_STATUS_Q_SIZE),
5330 ha->io_addr + IPS_REG_SQER);
5331 outl(cpu_to_le32(phys_status_start + IPS_STATUS_SIZE),
5332 ha->io_addr + IPS_REG_SQHR);
5333 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQTR);
5334
5335 ha->adapt->hw_status_tail = phys_status_start;
5336 }
5337
5338 /****************************************************************************/
5339 /* */
5340 /* Routine Name: ips_statinit_memio */
5341 /* */
5342 /* Routine Description: */
5343 /* */
5344 /* Initialize the status queues on the controller */
5345 /* */
5346 /****************************************************************************/
5347 static void
5348 ips_statinit_memio(ips_ha_t * ha)
5349 {
5350 uint32_t phys_status_start;
5351
5352 METHOD_TRACE("ips_statinit_memio", 1);
5353
5354 ha->adapt->p_status_start = ha->adapt->status;
5355 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5356 ha->adapt->p_status_tail = ha->adapt->status;
5357
5358 phys_status_start = ha->adapt->hw_status_start;
5359 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5360 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5361 ha->mem_ptr + IPS_REG_SQER);
5362 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5363 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5364
5365 ha->adapt->hw_status_tail = phys_status_start;
5366 }
5367
5368 /****************************************************************************/
5369 /* */
5370 /* Routine Name: ips_statupd_copperhead */
5371 /* */
5372 /* Routine Description: */
5373 /* */
5374 /* Remove an element from the status queue */
5375 /* */
5376 /****************************************************************************/
5377 static uint32_t
5378 ips_statupd_copperhead(ips_ha_t * ha)
5379 {
5380 METHOD_TRACE("ips_statupd_copperhead", 1);
5381
5382 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5383 ha->adapt->p_status_tail++;
5384 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5385 } else {
5386 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5387 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5388 }
5389
5390 outl(cpu_to_le32(ha->adapt->hw_status_tail),
5391 ha->io_addr + IPS_REG_SQTR);
5392
5393 return (ha->adapt->p_status_tail->value);
5394 }
5395
5396 /****************************************************************************/
5397 /* */
5398 /* Routine Name: ips_statupd_copperhead_memio */
5399 /* */
5400 /* Routine Description: */
5401 /* */
5402 /* Remove an element from the status queue */
5403 /* */
5404 /****************************************************************************/
5405 static uint32_t
5406 ips_statupd_copperhead_memio(ips_ha_t * ha)
5407 {
5408 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5409
5410 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5411 ha->adapt->p_status_tail++;
5412 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5413 } else {
5414 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5415 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5416 }
5417
5418 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5419
5420 return (ha->adapt->p_status_tail->value);
5421 }
5422
5423 /****************************************************************************/
5424 /* */
5425 /* Routine Name: ips_statupd_morpheus */
5426 /* */
5427 /* Routine Description: */
5428 /* */
5429 /* Remove an element from the status queue */
5430 /* */
5431 /****************************************************************************/
5432 static uint32_t
5433 ips_statupd_morpheus(ips_ha_t * ha)
5434 {
5435 uint32_t val;
5436
5437 METHOD_TRACE("ips_statupd_morpheus", 1);
5438
5439 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5440
5441 return (val);
5442 }
5443
5444 /****************************************************************************/
5445 /* */
5446 /* Routine Name: ips_issue_copperhead */
5447 /* */
5448 /* Routine Description: */
5449 /* */
5450 /* Send a command down to the controller */
5451 /* */
5452 /****************************************************************************/
5453 static int
5454 ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5455 {
5456 uint32_t TimeOut;
5457 uint32_t val;
5458
5459 METHOD_TRACE("ips_issue_copperhead", 1);
5460
5461 if (scb->scsi_cmd) {
5462 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5463 ips_name,
5464 ha->host_num,
5465 scb->cdb[0],
5466 scb->cmd.basic_io.command_id,
5467 scb->bus, scb->target_id, scb->lun);
5468 } else {
5469 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5470 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5471 }
5472
5473 TimeOut = 0;
5474
5475 while ((val =
5476 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5477 udelay(1000);
5478
5479 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5480 if (!(val & IPS_BIT_START_STOP))
5481 break;
5482
5483 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5484 "ips_issue val [0x%x].\n", val);
5485 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5486 "ips_issue semaphore chk timeout.\n");
5487
5488 return (IPS_FAILURE);
5489 } /* end if */
5490 } /* end while */
5491
5492 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_CCSAR);
5493 outw(cpu_to_le32(IPS_BIT_START_CMD), ha->io_addr + IPS_REG_CCCR);
5494
5495 return (IPS_SUCCESS);
5496 }
5497
5498 /****************************************************************************/
5499 /* */
5500 /* Routine Name: ips_issue_copperhead_memio */
5501 /* */
5502 /* Routine Description: */
5503 /* */
5504 /* Send a command down to the controller */
5505 /* */
5506 /****************************************************************************/
5507 static int
5508 ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5509 {
5510 uint32_t TimeOut;
5511 uint32_t val;
5512
5513 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5514
5515 if (scb->scsi_cmd) {
5516 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5517 ips_name,
5518 ha->host_num,
5519 scb->cdb[0],
5520 scb->cmd.basic_io.command_id,
5521 scb->bus, scb->target_id, scb->lun);
5522 } else {
5523 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5524 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5525 }
5526
5527 TimeOut = 0;
5528
5529 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5530 udelay(1000);
5531
5532 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5533 if (!(val & IPS_BIT_START_STOP))
5534 break;
5535
5536 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5537 "ips_issue val [0x%x].\n", val);
5538 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5539 "ips_issue semaphore chk timeout.\n");
5540
5541 return (IPS_FAILURE);
5542 } /* end if */
5543 } /* end while */
5544
5545 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5546 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5547
5548 return (IPS_SUCCESS);
5549 }
5550
5551 /****************************************************************************/
5552 /* */
5553 /* Routine Name: ips_issue_i2o */
5554 /* */
5555 /* Routine Description: */
5556 /* */
5557 /* Send a command down to the controller */
5558 /* */
5559 /****************************************************************************/
5560 static int
5561 ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5562 {
5563
5564 METHOD_TRACE("ips_issue_i2o", 1);
5565
5566 if (scb->scsi_cmd) {
5567 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5568 ips_name,
5569 ha->host_num,
5570 scb->cdb[0],
5571 scb->cmd.basic_io.command_id,
5572 scb->bus, scb->target_id, scb->lun);
5573 } else {
5574 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5575 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5576 }
5577
5578 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_I2O_INMSGQ);
5579
5580 return (IPS_SUCCESS);
5581 }
5582
5583 /****************************************************************************/
5584 /* */
5585 /* Routine Name: ips_issue_i2o_memio */
5586 /* */
5587 /* Routine Description: */
5588 /* */
5589 /* Send a command down to the controller */
5590 /* */
5591 /****************************************************************************/
5592 static int
5593 ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5594 {
5595
5596 METHOD_TRACE("ips_issue_i2o_memio", 1);
5597
5598 if (scb->scsi_cmd) {
5599 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5600 ips_name,
5601 ha->host_num,
5602 scb->cdb[0],
5603 scb->cmd.basic_io.command_id,
5604 scb->bus, scb->target_id, scb->lun);
5605 } else {
5606 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5607 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5608 }
5609
5610 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5611
5612 return (IPS_SUCCESS);
5613 }
5614
5615 /****************************************************************************/
5616 /* */
5617 /* Routine Name: ips_isintr_copperhead */
5618 /* */
5619 /* Routine Description: */
5620 /* */
5621 /* Test to see if an interrupt is for us */
5622 /* */
5623 /****************************************************************************/
5624 static int
5625 ips_isintr_copperhead(ips_ha_t * ha)
5626 {
5627 uint8_t Isr;
5628
5629 METHOD_TRACE("ips_isintr_copperhead", 2);
5630
5631 Isr = inb(ha->io_addr + IPS_REG_HISR);
5632
5633 if (Isr == 0xFF)
5634 /* ?!?! Nothing really there */
5635 return (0);
5636
5637 if (Isr & IPS_BIT_SCE)
5638 return (1);
5639 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5640 /* status queue overflow or GHI */
5641 /* just clear the interrupt */
5642 outb(Isr, ha->io_addr + IPS_REG_HISR);
5643 }
5644
5645 return (0);
5646 }
5647
5648 /****************************************************************************/
5649 /* */
5650 /* Routine Name: ips_isintr_copperhead_memio */
5651 /* */
5652 /* Routine Description: */
5653 /* */
5654 /* Test to see if an interrupt is for us */
5655 /* */
5656 /****************************************************************************/
5657 static int
5658 ips_isintr_copperhead_memio(ips_ha_t * ha)
5659 {
5660 uint8_t Isr;
5661
5662 METHOD_TRACE("ips_isintr_memio", 2);
5663
5664 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5665
5666 if (Isr == 0xFF)
5667 /* ?!?! Nothing really there */
5668 return (0);
5669
5670 if (Isr & IPS_BIT_SCE)
5671 return (1);
5672 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5673 /* status queue overflow or GHI */
5674 /* just clear the interrupt */
5675 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5676 }
5677
5678 return (0);
5679 }
5680
5681 /****************************************************************************/
5682 /* */
5683 /* Routine Name: ips_isintr_morpheus */
5684 /* */
5685 /* Routine Description: */
5686 /* */
5687 /* Test to see if an interrupt is for us */
5688 /* */
5689 /****************************************************************************/
5690 static int
5691 ips_isintr_morpheus(ips_ha_t * ha)
5692 {
5693 uint32_t Isr;
5694
5695 METHOD_TRACE("ips_isintr_morpheus", 2);
5696
5697 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5698
5699 if (Isr & IPS_BIT_I2O_OPQI)
5700 return (1);
5701 else
5702 return (0);
5703 }
5704
5705 /****************************************************************************/
5706 /* */
5707 /* Routine Name: ips_wait */
5708 /* */
5709 /* Routine Description: */
5710 /* */
5711 /* Wait for a command to complete */
5712 /* */
5713 /****************************************************************************/
5714 static int
5715 ips_wait(ips_ha_t * ha, int time, int intr)
5716 {
5717 int ret;
5718 int done;
5719
5720 METHOD_TRACE("ips_wait", 1);
5721
5722 ret = IPS_FAILURE;
5723 done = FALSE;
5724
5725 time *= IPS_ONE_SEC; /* convert seconds */
5726
5727 while ((time > 0) && (!done)) {
5728 if (intr == IPS_INTR_ON) {
5729 if (ha->waitflag == FALSE) {
5730 ret = IPS_SUCCESS;
5731 done = TRUE;
5732 break;
5733 }
5734 } else if (intr == IPS_INTR_IORL) {
5735 if (ha->waitflag == FALSE) {
5736 /*
5737 * controller generated an interrupt to
5738 * acknowledge completion of the command
5739 * and ips_intr() has serviced the interrupt.
5740 */
5741 ret = IPS_SUCCESS;
5742 done = TRUE;
5743 break;
5744 }
5745
5746 /*
5747 * NOTE: we already have the io_request_lock so
5748 * even if we get an interrupt it won't get serviced
5749 * until after we finish.
5750 */
5751
5752 (*ha->func.intr) (ha);
5753 }
5754
5755 /* This looks like a very evil loop, but it only does this during start-up */
5756 udelay(1000);
5757 time--;
5758 }
5759
5760 return (ret);
5761 }
5762
5763 /****************************************************************************/
5764 /* */
5765 /* Routine Name: ips_write_driver_status */
5766 /* */
5767 /* Routine Description: */
5768 /* */
5769 /* Write OS/Driver version to Page 5 of the nvram on the controller */
5770 /* */
5771 /****************************************************************************/
5772 static int
5773 ips_write_driver_status(ips_ha_t * ha, int intr)
5774 {
5775 METHOD_TRACE("ips_write_driver_status", 1);
5776
5777 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5778 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5779 "unable to read NVRAM page 5.\n");
5780
5781 return (0);
5782 }
5783
5784 /* check to make sure the page has a valid */
5785 /* signature */
5786 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5787 DEBUG_VAR(1,
5788 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5789 ips_name, ha->host_num, ha->nvram->signature);
5790 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5791 }
5792
5793 DEBUG_VAR(2,
5794 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5795 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5796 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5797 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5798 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5799 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5800 ha->nvram->bios_low[3]);
5801
5802 ips_get_bios_version(ha, intr);
5803
5804 /* change values (as needed) */
5805 ha->nvram->operating_system = IPS_OS_LINUX;
5806 ha->nvram->adapter_type = ha->ad_type;
5807 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5808 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5809 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5810 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5811
5812 ips_version_check(ha, intr); /* Check BIOS/FW/Driver Versions */
5813
5814 /* now update the page */
5815 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5816 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5817 "unable to write NVRAM page 5.\n");
5818
5819 return (0);
5820 }
5821
5822 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5823 ha->slot_num = ha->nvram->adapter_slot;
5824
5825 return (1);
5826 }
5827
5828 /****************************************************************************/
5829 /* */
5830 /* Routine Name: ips_read_adapter_status */
5831 /* */
5832 /* Routine Description: */
5833 /* */
5834 /* Do an Inquiry command to the adapter */
5835 /* */
5836 /****************************************************************************/
5837 static int
5838 ips_read_adapter_status(ips_ha_t * ha, int intr)
5839 {
5840 ips_scb_t *scb;
5841 int ret;
5842
5843 METHOD_TRACE("ips_read_adapter_status", 1);
5844
5845 scb = &ha->scbs[ha->max_cmds - 1];
5846
5847 ips_init_scb(ha, scb);
5848
5849 scb->timeout = ips_cmd_timeout;
5850 scb->cdb[0] = IPS_CMD_ENQUIRY;
5851
5852 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5853 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5854 scb->cmd.basic_io.sg_count = 0;
5855 scb->cmd.basic_io.lba = 0;
5856 scb->cmd.basic_io.sector_count = 0;
5857 scb->cmd.basic_io.log_drv = 0;
5858 scb->data_len = sizeof (*ha->enq);
5859 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5860
5861 /* send command */
5862 if (((ret =
5863 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5864 || (ret == IPS_SUCCESS_IMM)
5865 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5866 return (0);
5867
5868 return (1);
5869 }
5870
5871 /****************************************************************************/
5872 /* */
5873 /* Routine Name: ips_read_subsystem_parameters */
5874 /* */
5875 /* Routine Description: */
5876 /* */
5877 /* Read subsystem parameters from the adapter */
5878 /* */
5879 /****************************************************************************/
5880 static int
5881 ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5882 {
5883 ips_scb_t *scb;
5884 int ret;
5885
5886 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5887
5888 scb = &ha->scbs[ha->max_cmds - 1];
5889
5890 ips_init_scb(ha, scb);
5891
5892 scb->timeout = ips_cmd_timeout;
5893 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5894
5895 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5896 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5897 scb->cmd.basic_io.sg_count = 0;
5898 scb->cmd.basic_io.lba = 0;
5899 scb->cmd.basic_io.sector_count = 0;
5900 scb->cmd.basic_io.log_drv = 0;
5901 scb->data_len = sizeof (*ha->subsys);
5902 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5903
5904 /* send command */
5905 if (((ret =
5906 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5907 || (ret == IPS_SUCCESS_IMM)
5908 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5909 return (0);
5910
5911 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5912 return (1);
5913 }
5914
5915 /****************************************************************************/
5916 /* */
5917 /* Routine Name: ips_read_config */
5918 /* */
5919 /* Routine Description: */
5920 /* */
5921 /* Read the configuration on the adapter */
5922 /* */
5923 /****************************************************************************/
5924 static int
5925 ips_read_config(ips_ha_t * ha, int intr)
5926 {
5927 ips_scb_t *scb;
5928 int i;
5929 int ret;
5930
5931 METHOD_TRACE("ips_read_config", 1);
5932
5933 /* set defaults for initiator IDs */
5934 for (i = 0; i < 4; i++)
5935 ha->conf->init_id[i] = 7;
5936
5937 scb = &ha->scbs[ha->max_cmds - 1];
5938
5939 ips_init_scb(ha, scb);
5940
5941 scb->timeout = ips_cmd_timeout;
5942 scb->cdb[0] = IPS_CMD_READ_CONF;
5943
5944 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5945 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5946 scb->data_len = sizeof (*ha->conf);
5947 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5948
5949 /* send command */
5950 if (((ret =
5951 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5952 || (ret == IPS_SUCCESS_IMM)
5953 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5954
5955 memset(ha->conf, 0, sizeof (IPS_CONF));
5956
5957 /* reset initiator IDs */
5958 for (i = 0; i < 4; i++)
5959 ha->conf->init_id[i] = 7;
5960
5961 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5962 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5963 IPS_CMD_CMPLT_WERROR)
5964 return (1);
5965
5966 return (0);
5967 }
5968
5969 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5970 return (1);
5971 }
5972
5973 /****************************************************************************/
5974 /* */
5975 /* Routine Name: ips_readwrite_page5 */
5976 /* */
5977 /* Routine Description: */
5978 /* */
5979 /* Read nvram page 5 from the adapter */
5980 /* */
5981 /****************************************************************************/
5982 static int
5983 ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5984 {
5985 ips_scb_t *scb;
5986 int ret;
5987
5988 METHOD_TRACE("ips_readwrite_page5", 1);
5989
5990 scb = &ha->scbs[ha->max_cmds - 1];
5991
5992 ips_init_scb(ha, scb);
5993
5994 scb->timeout = ips_cmd_timeout;
5995 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5996
5997 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5998 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5999 scb->cmd.nvram.page = 5;
6000 scb->cmd.nvram.write = write;
6001 scb->cmd.nvram.reserved = 0;
6002 scb->cmd.nvram.reserved2 = 0;
6003 scb->data_len = sizeof (*ha->nvram);
6004 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
6005 if (write)
6006 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
6007
6008 /* issue the command */
6009 if (((ret =
6010 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6011 || (ret == IPS_SUCCESS_IMM)
6012 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
6013
6014 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
6015
6016 return (0);
6017 }
6018 if (!write)
6019 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
6020 return (1);
6021 }
6022
6023 /****************************************************************************/
6024 /* */
6025 /* Routine Name: ips_clear_adapter */
6026 /* */
6027 /* Routine Description: */
6028 /* */
6029 /* Clear the stripe lock tables */
6030 /* */
6031 /****************************************************************************/
6032 static int
6033 ips_clear_adapter(ips_ha_t * ha, int intr)
6034 {
6035 ips_scb_t *scb;
6036 int ret;
6037
6038 METHOD_TRACE("ips_clear_adapter", 1);
6039
6040 scb = &ha->scbs[ha->max_cmds - 1];
6041
6042 ips_init_scb(ha, scb);
6043
6044 scb->timeout = ips_reset_timeout;
6045 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
6046
6047 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
6048 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
6049 scb->cmd.config_sync.channel = 0;
6050 scb->cmd.config_sync.source_target = IPS_POCL;
6051 scb->cmd.config_sync.reserved = 0;
6052 scb->cmd.config_sync.reserved2 = 0;
6053 scb->cmd.config_sync.reserved3 = 0;
6054
6055 /* issue command */
6056 if (((ret =
6057 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
6058 || (ret == IPS_SUCCESS_IMM)
6059 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
6060 return (0);
6061
6062 /* send unlock stripe command */
6063 ips_init_scb(ha, scb);
6064
6065 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
6066 scb->timeout = ips_reset_timeout;
6067
6068 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
6069 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
6070 scb->cmd.unlock_stripe.log_drv = 0;
6071 scb->cmd.unlock_stripe.control = IPS_CSL;
6072 scb->cmd.unlock_stripe.reserved = 0;
6073 scb->cmd.unlock_stripe.reserved2 = 0;
6074 scb->cmd.unlock_stripe.reserved3 = 0;
6075
6076 /* issue command */
6077 if (((ret =
6078 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6079 || (ret == IPS_SUCCESS_IMM)
6080 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
6081 return (0);
6082
6083 return (1);
6084 }
6085
6086 /****************************************************************************/
6087 /* */
6088 /* Routine Name: ips_ffdc_reset */
6089 /* */
6090 /* Routine Description: */
6091 /* */
6092 /* FFDC: write reset info */
6093 /* */
6094 /****************************************************************************/
6095 static void
6096 ips_ffdc_reset(ips_ha_t * ha, int intr)
6097 {
6098 ips_scb_t *scb;
6099
6100 METHOD_TRACE("ips_ffdc_reset", 1);
6101
6102 scb = &ha->scbs[ha->max_cmds - 1];
6103
6104 ips_init_scb(ha, scb);
6105
6106 scb->timeout = ips_cmd_timeout;
6107 scb->cdb[0] = IPS_CMD_FFDC;
6108 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6109 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6110 scb->cmd.ffdc.reset_count = ha->reset_count;
6111 scb->cmd.ffdc.reset_type = 0x80;
6112
6113 /* convert time to what the card wants */
6114 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6115
6116 /* issue command */
6117 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6118 }
6119
6120 /****************************************************************************/
6121 /* */
6122 /* Routine Name: ips_ffdc_time */
6123 /* */
6124 /* Routine Description: */
6125 /* */
6126 /* FFDC: write time info */
6127 /* */
6128 /****************************************************************************/
6129 static void
6130 ips_ffdc_time(ips_ha_t * ha)
6131 {
6132 ips_scb_t *scb;
6133
6134 METHOD_TRACE("ips_ffdc_time", 1);
6135
6136 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
6137
6138 scb = &ha->scbs[ha->max_cmds - 1];
6139
6140 ips_init_scb(ha, scb);
6141
6142 scb->timeout = ips_cmd_timeout;
6143 scb->cdb[0] = IPS_CMD_FFDC;
6144 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6145 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6146 scb->cmd.ffdc.reset_count = 0;
6147 scb->cmd.ffdc.reset_type = 0;
6148
6149 /* convert time to what the card wants */
6150 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6151
6152 /* issue command */
6153 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
6154 }
6155
6156 /****************************************************************************/
6157 /* */
6158 /* Routine Name: ips_fix_ffdc_time */
6159 /* */
6160 /* Routine Description: */
6161 /* Adjust time_t to what the card wants */
6162 /* */
6163 /****************************************************************************/
6164 static void
6165 ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
6166 {
6167 long days;
6168 long rem;
6169 int i;
6170 int year;
6171 int yleap;
6172 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
6173 int month_lengths[12][2] = { {31, 31},
6174 {28, 29},
6175 {31, 31},
6176 {30, 30},
6177 {31, 31},
6178 {30, 30},
6179 {31, 31},
6180 {31, 31},
6181 {30, 30},
6182 {31, 31},
6183 {30, 30},
6184 {31, 31}
6185 };
6186
6187 METHOD_TRACE("ips_fix_ffdc_time", 1);
6188
6189 days = current_time / IPS_SECS_DAY;
6190 rem = current_time % IPS_SECS_DAY;
6191
6192 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
6193 rem = rem % IPS_SECS_HOUR;
6194 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
6195 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
6196
6197 year = IPS_EPOCH_YEAR;
6198 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
6199 int newy;
6200
6201 newy = year + (days / IPS_DAYS_NORMAL_YEAR);
6202 if (days < 0)
6203 --newy;
6204 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
6205 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
6206 IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
6207 year = newy;
6208 }
6209
6210 scb->cmd.ffdc.yearH = year / 100;
6211 scb->cmd.ffdc.yearL = year % 100;
6212
6213 for (i = 0; days >= month_lengths[i][yleap]; ++i)
6214 days -= month_lengths[i][yleap];
6215
6216 scb->cmd.ffdc.month = i + 1;
6217 scb->cmd.ffdc.day = days + 1;
6218 }
6219
6220 /****************************************************************************
6221 * BIOS Flash Routines *
6222 ****************************************************************************/
6223
6224 /****************************************************************************/
6225 /* */
6226 /* Routine Name: ips_erase_bios */
6227 /* */
6228 /* Routine Description: */
6229 /* Erase the BIOS on the adapter */
6230 /* */
6231 /****************************************************************************/
6232 static int
6233 ips_erase_bios(ips_ha_t * ha)
6234 {
6235 int timeout;
6236 uint8_t status = 0;
6237
6238 METHOD_TRACE("ips_erase_bios", 1);
6239
6240 status = 0;
6241
6242 /* Clear the status register */
6243 outl(0, ha->io_addr + IPS_REG_FLAP);
6244 if (ha->revision_id == IPS_REVID_TROMBONE64)
6245 udelay(25); /* 25 us */
6246
6247 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6248 if (ha->revision_id == IPS_REVID_TROMBONE64)
6249 udelay(25); /* 25 us */
6250
6251 /* Erase Setup */
6252 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6253 if (ha->revision_id == IPS_REVID_TROMBONE64)
6254 udelay(25); /* 25 us */
6255
6256 /* Erase Confirm */
6257 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6258 if (ha->revision_id == IPS_REVID_TROMBONE64)
6259 udelay(25); /* 25 us */
6260
6261 /* Erase Status */
6262 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6263 if (ha->revision_id == IPS_REVID_TROMBONE64)
6264 udelay(25); /* 25 us */
6265
6266 timeout = 80000; /* 80 seconds */
6267
6268 while (timeout > 0) {
6269 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6270 outl(0, ha->io_addr + IPS_REG_FLAP);
6271 udelay(25); /* 25 us */
6272 }
6273
6274 status = inb(ha->io_addr + IPS_REG_FLDP);
6275
6276 if (status & 0x80)
6277 break;
6278
6279 MDELAY(1);
6280 timeout--;
6281 }
6282
6283 /* check for timeout */
6284 if (timeout <= 0) {
6285 /* timeout */
6286
6287 /* try to suspend the erase */
6288 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6289 if (ha->revision_id == IPS_REVID_TROMBONE64)
6290 udelay(25); /* 25 us */
6291
6292 /* wait for 10 seconds */
6293 timeout = 10000;
6294 while (timeout > 0) {
6295 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6296 outl(0, ha->io_addr + IPS_REG_FLAP);
6297 udelay(25); /* 25 us */
6298 }
6299
6300 status = inb(ha->io_addr + IPS_REG_FLDP);
6301
6302 if (status & 0xC0)
6303 break;
6304
6305 MDELAY(1);
6306 timeout--;
6307 }
6308
6309 return (1);
6310 }
6311
6312 /* check for valid VPP */
6313 if (status & 0x08)
6314 /* VPP failure */
6315 return (1);
6316
6317 /* check for succesful flash */
6318 if (status & 0x30)
6319 /* sequence error */
6320 return (1);
6321
6322 /* Otherwise, we were successful */
6323 /* clear status */
6324 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6325 if (ha->revision_id == IPS_REVID_TROMBONE64)
6326 udelay(25); /* 25 us */
6327
6328 /* enable reads */
6329 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6330 if (ha->revision_id == IPS_REVID_TROMBONE64)
6331 udelay(25); /* 25 us */
6332
6333 return (0);
6334 }
6335
6336 /****************************************************************************/
6337 /* */
6338 /* Routine Name: ips_erase_bios_memio */
6339 /* */
6340 /* Routine Description: */
6341 /* Erase the BIOS on the adapter */
6342 /* */
6343 /****************************************************************************/
6344 static int
6345 ips_erase_bios_memio(ips_ha_t * ha)
6346 {
6347 int timeout;
6348 uint8_t status;
6349
6350 METHOD_TRACE("ips_erase_bios_memio", 1);
6351
6352 status = 0;
6353
6354 /* Clear the status register */
6355 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6356 if (ha->revision_id == IPS_REVID_TROMBONE64)
6357 udelay(25); /* 25 us */
6358
6359 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6360 if (ha->revision_id == IPS_REVID_TROMBONE64)
6361 udelay(25); /* 25 us */
6362
6363 /* Erase Setup */
6364 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6365 if (ha->revision_id == IPS_REVID_TROMBONE64)
6366 udelay(25); /* 25 us */
6367
6368 /* Erase Confirm */
6369 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6370 if (ha->revision_id == IPS_REVID_TROMBONE64)
6371 udelay(25); /* 25 us */
6372
6373 /* Erase Status */
6374 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6375 if (ha->revision_id == IPS_REVID_TROMBONE64)
6376 udelay(25); /* 25 us */
6377
6378 timeout = 80000; /* 80 seconds */
6379
6380 while (timeout > 0) {
6381 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6382 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6383 udelay(25); /* 25 us */
6384 }
6385
6386 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6387
6388 if (status & 0x80)
6389 break;
6390
6391 MDELAY(1);
6392 timeout--;
6393 }
6394
6395 /* check for timeout */
6396 if (timeout <= 0) {
6397 /* timeout */
6398
6399 /* try to suspend the erase */
6400 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6401 if (ha->revision_id == IPS_REVID_TROMBONE64)
6402 udelay(25); /* 25 us */
6403
6404 /* wait for 10 seconds */
6405 timeout = 10000;
6406 while (timeout > 0) {
6407 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6408 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6409 udelay(25); /* 25 us */
6410 }
6411
6412 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6413
6414 if (status & 0xC0)
6415 break;
6416
6417 MDELAY(1);
6418 timeout--;
6419 }
6420
6421 return (1);
6422 }
6423
6424 /* check for valid VPP */
6425 if (status & 0x08)
6426 /* VPP failure */
6427 return (1);
6428
6429 /* check for succesful flash */
6430 if (status & 0x30)
6431 /* sequence error */
6432 return (1);
6433
6434 /* Otherwise, we were successful */
6435 /* clear status */
6436 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6437 if (ha->revision_id == IPS_REVID_TROMBONE64)
6438 udelay(25); /* 25 us */
6439
6440 /* enable reads */
6441 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6442 if (ha->revision_id == IPS_REVID_TROMBONE64)
6443 udelay(25); /* 25 us */
6444
6445 return (0);
6446 }
6447
6448 /****************************************************************************/
6449 /* */
6450 /* Routine Name: ips_program_bios */
6451 /* */
6452 /* Routine Description: */
6453 /* Program the BIOS on the adapter */
6454 /* */
6455 /****************************************************************************/
6456 static int
6457 ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6458 uint32_t offset)
6459 {
6460 int i;
6461 int timeout;
6462 uint8_t status = 0;
6463
6464 METHOD_TRACE("ips_program_bios", 1);
6465
6466 status = 0;
6467
6468 for (i = 0; i < buffersize; i++) {
6469 /* write a byte */
6470 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6471 if (ha->revision_id == IPS_REVID_TROMBONE64)
6472 udelay(25); /* 25 us */
6473
6474 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6475 if (ha->revision_id == IPS_REVID_TROMBONE64)
6476 udelay(25); /* 25 us */
6477
6478 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6479 if (ha->revision_id == IPS_REVID_TROMBONE64)
6480 udelay(25); /* 25 us */
6481
6482 /* wait up to one second */
6483 timeout = 1000;
6484 while (timeout > 0) {
6485 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6486 outl(0, ha->io_addr + IPS_REG_FLAP);
6487 udelay(25); /* 25 us */
6488 }
6489
6490 status = inb(ha->io_addr + IPS_REG_FLDP);
6491
6492 if (status & 0x80)
6493 break;
6494
6495 MDELAY(1);
6496 timeout--;
6497 }
6498
6499 if (timeout == 0) {
6500 /* timeout error */
6501 outl(0, ha->io_addr + IPS_REG_FLAP);
6502 if (ha->revision_id == IPS_REVID_TROMBONE64)
6503 udelay(25); /* 25 us */
6504
6505 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6506 if (ha->revision_id == IPS_REVID_TROMBONE64)
6507 udelay(25); /* 25 us */
6508
6509 return (1);
6510 }
6511
6512 /* check the status */
6513 if (status & 0x18) {
6514 /* programming error */
6515 outl(0, ha->io_addr + IPS_REG_FLAP);
6516 if (ha->revision_id == IPS_REVID_TROMBONE64)
6517 udelay(25); /* 25 us */
6518
6519 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6520 if (ha->revision_id == IPS_REVID_TROMBONE64)
6521 udelay(25); /* 25 us */
6522
6523 return (1);
6524 }
6525 } /* end for */
6526
6527 /* Enable reading */
6528 outl(0, ha->io_addr + IPS_REG_FLAP);
6529 if (ha->revision_id == IPS_REVID_TROMBONE64)
6530 udelay(25); /* 25 us */
6531
6532 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6533 if (ha->revision_id == IPS_REVID_TROMBONE64)
6534 udelay(25); /* 25 us */
6535
6536 return (0);
6537 }
6538
6539 /****************************************************************************/
6540 /* */
6541 /* Routine Name: ips_program_bios_memio */
6542 /* */
6543 /* Routine Description: */
6544 /* Program the BIOS on the adapter */
6545 /* */
6546 /****************************************************************************/
6547 static int
6548 ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6549 uint32_t offset)
6550 {
6551 int i;
6552 int timeout;
6553 uint8_t status = 0;
6554
6555 METHOD_TRACE("ips_program_bios_memio", 1);
6556
6557 status = 0;
6558
6559 for (i = 0; i < buffersize; i++) {
6560 /* write a byte */
6561 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6562 if (ha->revision_id == IPS_REVID_TROMBONE64)
6563 udelay(25); /* 25 us */
6564
6565 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6566 if (ha->revision_id == IPS_REVID_TROMBONE64)
6567 udelay(25); /* 25 us */
6568
6569 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6570 if (ha->revision_id == IPS_REVID_TROMBONE64)
6571 udelay(25); /* 25 us */
6572
6573 /* wait up to one second */
6574 timeout = 1000;
6575 while (timeout > 0) {
6576 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6577 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6578 udelay(25); /* 25 us */
6579 }
6580
6581 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6582
6583 if (status & 0x80)
6584 break;
6585
6586 MDELAY(1);
6587 timeout--;
6588 }
6589
6590 if (timeout == 0) {
6591 /* timeout error */
6592 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6593 if (ha->revision_id == IPS_REVID_TROMBONE64)
6594 udelay(25); /* 25 us */
6595
6596 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6597 if (ha->revision_id == IPS_REVID_TROMBONE64)
6598 udelay(25); /* 25 us */
6599
6600 return (1);
6601 }
6602
6603 /* check the status */
6604 if (status & 0x18) {
6605 /* programming error */
6606 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6607 if (ha->revision_id == IPS_REVID_TROMBONE64)
6608 udelay(25); /* 25 us */
6609
6610 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6611 if (ha->revision_id == IPS_REVID_TROMBONE64)
6612 udelay(25); /* 25 us */
6613
6614 return (1);
6615 }
6616 } /* end for */
6617
6618 /* Enable reading */
6619 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6620 if (ha->revision_id == IPS_REVID_TROMBONE64)
6621 udelay(25); /* 25 us */
6622
6623 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6624 if (ha->revision_id == IPS_REVID_TROMBONE64)
6625 udelay(25); /* 25 us */
6626
6627 return (0);
6628 }
6629
6630 /****************************************************************************/
6631 /* */
6632 /* Routine Name: ips_verify_bios */
6633 /* */
6634 /* Routine Description: */
6635 /* Verify the BIOS on the adapter */
6636 /* */
6637 /****************************************************************************/
6638 static int
6639 ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6640 uint32_t offset)
6641 {
6642 uint8_t checksum;
6643 int i;
6644
6645 METHOD_TRACE("ips_verify_bios", 1);
6646
6647 /* test 1st byte */
6648 outl(0, ha->io_addr + IPS_REG_FLAP);
6649 if (ha->revision_id == IPS_REVID_TROMBONE64)
6650 udelay(25); /* 25 us */
6651
6652 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6653 return (1);
6654
6655 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
6656 if (ha->revision_id == IPS_REVID_TROMBONE64)
6657 udelay(25); /* 25 us */
6658 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6659 return (1);
6660
6661 checksum = 0xff;
6662 for (i = 2; i < buffersize; i++) {
6663
6664 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6665 if (ha->revision_id == IPS_REVID_TROMBONE64)
6666 udelay(25); /* 25 us */
6667
6668 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6669 }
6670
6671 if (checksum != 0)
6672 /* failure */
6673 return (1);
6674 else
6675 /* success */
6676 return (0);
6677 }
6678
6679 /****************************************************************************/
6680 /* */
6681 /* Routine Name: ips_verify_bios_memio */
6682 /* */
6683 /* Routine Description: */
6684 /* Verify the BIOS on the adapter */
6685 /* */
6686 /****************************************************************************/
6687 static int
6688 ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6689 uint32_t offset)
6690 {
6691 uint8_t checksum;
6692 int i;
6693
6694 METHOD_TRACE("ips_verify_bios_memio", 1);
6695
6696 /* test 1st byte */
6697 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6698 if (ha->revision_id == IPS_REVID_TROMBONE64)
6699 udelay(25); /* 25 us */
6700
6701 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6702 return (1);
6703
6704 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6705 if (ha->revision_id == IPS_REVID_TROMBONE64)
6706 udelay(25); /* 25 us */
6707 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6708 return (1);
6709
6710 checksum = 0xff;
6711 for (i = 2; i < buffersize; i++) {
6712
6713 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6714 if (ha->revision_id == IPS_REVID_TROMBONE64)
6715 udelay(25); /* 25 us */
6716
6717 checksum =
6718 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6719 }
6720
6721 if (checksum != 0)
6722 /* failure */
6723 return (1);
6724 else
6725 /* success */
6726 return (0);
6727 }
6728
6729 /*---------------------------------------------------------------------------*/
6730 /* Routine Name: ips_version_check */
6731 /* */
6732 /* Dependencies: */
6733 /* Assumes that ips_read_adapter_status() is called first filling in */
6734 /* the data for SubSystem Parameters. */
6735 /* Called from ips_write_driver_status() so it also assumes NVRAM Page 5 */
6736 /* Data is available. */
6737 /* */
6738 /*---------------------------------------------------------------------------*/
6739 static void
6740 ips_version_check(ips_ha_t * ha, int intr)
6741 {
6742 IPS_VERSION_DATA *VersionInfo;
6743 uint8_t FirmwareVersion[IPS_COMPAT_ID_LENGTH + 1];
6744 uint8_t BiosVersion[IPS_COMPAT_ID_LENGTH + 1];
6745 int MatchError;
6746 int rc;
6747 char BiosString[10];
6748 char FirmwareString[10];
6749
6750 METHOD_TRACE("ips_version_check", 1);
6751
6752 VersionInfo = ( IPS_VERSION_DATA * ) ha->ioctl_data;
6753
6754 memset(FirmwareVersion, 0, IPS_COMPAT_ID_LENGTH + 1);
6755 memset(BiosVersion, 0, IPS_COMPAT_ID_LENGTH + 1);
6756
6757 /* Get the Compatible BIOS Version from NVRAM Page 5 */
6758 memcpy(BiosVersion, ha->nvram->BiosCompatibilityID,
6759 IPS_COMPAT_ID_LENGTH);
6760
6761 rc = IPS_FAILURE;
6762 if (ha->subsys->param[4] & IPS_GET_VERSION_SUPPORT) { /* If Versioning is Supported */
6763 /* Get the Version Info with a Get Version Command */
6764 memset( VersionInfo, 0, sizeof (IPS_VERSION_DATA));
6765 rc = ips_get_version_info(ha, ha->ioctl_busaddr, intr);
6766 if (rc == IPS_SUCCESS)
6767 memcpy(FirmwareVersion, VersionInfo->compatibilityId,
6768 IPS_COMPAT_ID_LENGTH);
6769 }
6770
6771 if (rc != IPS_SUCCESS) { /* If Data Not Obtainable from a GetVersion Command */
6772 /* Get the Firmware Version from Enquiry Data */
6773 memcpy(FirmwareVersion, ha->enq->CodeBlkVersion,
6774 IPS_COMPAT_ID_LENGTH);
6775 }
6776
6777 /* printk(KERN_WARNING "Adapter's BIOS Version = %s\n", BiosVersion); */
6778 /* printk(KERN_WARNING "BIOS Compatible Version = %s\n", IPS_COMPAT_BIOS); */
6779 /* printk(KERN_WARNING "Adapter's Firmware Version = %s\n", FirmwareVersion); */
6780 /* printk(KERN_WARNING "Firmware Compatible Version = %s \n", Compatable[ ha->nvram->adapter_type ]); */
6781
6782 MatchError = 0;
6783
6784 if (strncmp
6785 (FirmwareVersion, Compatable[ha->nvram->adapter_type],
6786 IPS_COMPAT_ID_LENGTH) != 0)
6787 MatchError = 1;
6788
6789 if (strncmp(BiosVersion, IPS_COMPAT_BIOS, IPS_COMPAT_ID_LENGTH) != 0)
6790 MatchError = 1;
6791
6792 ha->nvram->versioning = 1; /* Indicate the Driver Supports Versioning */
6793
6794 if (MatchError) {
6795 ha->nvram->version_mismatch = 1;
6796 if (ips_cd_boot == 0) {
6797 strncpy(&BiosString[0], ha->nvram->bios_high, 4);
6798 strncpy(&BiosString[4], ha->nvram->bios_low, 4);
6799 BiosString[8] = 0;
6800
6801 strncpy(&FirmwareString[0], ha->enq->CodeBlkVersion, 8);
6802 FirmwareString[8] = 0;
6803
6804 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6805 "Warning ! ! ! ServeRAID Version Mismatch\n");
6806 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6807 "Bios = %s, Firmware = %s, Device Driver = %s%s\n",
6808 BiosString, FirmwareString, IPS_VERSION_HIGH,
6809 IPS_VERSION_LOW);
6810 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6811 "These levels should match to avoid possible compatibility problems.\n");
6812 }
6813 } else {
6814 ha->nvram->version_mismatch = 0;
6815 }
6816
6817 return;
6818 }
6819
6820 /*---------------------------------------------------------------------------*/
6821 /* Routine Name: ips_get_version_info */
6822 /* */
6823 /* Routine Description: */
6824 /* Issue an internal GETVERSION Command */
6825 /* */
6826 /* Return Value: */
6827 /* 0 if Successful, else non-zero */
6828 /*---------------------------------------------------------------------------*/
6829 static int
6830 ips_get_version_info(ips_ha_t * ha, dma_addr_t Buffer, int intr)
6831 {
6832 ips_scb_t *scb;
6833 int rc;
6834
6835 METHOD_TRACE("ips_get_version_info", 1);
6836
6837 scb = &ha->scbs[ha->max_cmds - 1];
6838
6839 ips_init_scb(ha, scb);
6840
6841 scb->timeout = ips_cmd_timeout;
6842 scb->cdb[0] = IPS_CMD_GET_VERSION_INFO;
6843 scb->cmd.version_info.op_code = IPS_CMD_GET_VERSION_INFO;
6844 scb->cmd.version_info.command_id = IPS_COMMAND_ID(ha, scb);
6845 scb->cmd.version_info.reserved = 0;
6846 scb->cmd.version_info.count = sizeof (IPS_VERSION_DATA);
6847 scb->cmd.version_info.reserved2 = 0;
6848 scb->data_len = sizeof (IPS_VERSION_DATA);
6849 scb->data_busaddr = Buffer;
6850 scb->cmd.version_info.buffer_addr = Buffer;
6851 scb->flags = 0;
6852
6853 /* issue command */
6854 rc = ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6855 return (rc);
6856 }
6857
6858 /****************************************************************************/
6859 /* */
6860 /* Routine Name: ips_abort_init */
6861 /* */
6862 /* Routine Description: */
6863 /* cleanup routine for a failed adapter initialization */
6864 /****************************************************************************/
6865 static int
6866 ips_abort_init(ips_ha_t * ha, int index)
6867 {
6868 ha->active = 0;
6869 ips_free(ha);
6870 ips_ha[index] = 0;
6871 ips_sh[index] = 0;
6872 return -1;
6873 }
6874
6875 /****************************************************************************/
6876 /* */
6877 /* Routine Name: ips_shift_controllers */
6878 /* */
6879 /* Routine Description: */
6880 /* helper function for ordering adapters */
6881 /****************************************************************************/
6882 static void
6883 ips_shift_controllers(int lowindex, int highindex)
6884 {
6885 ips_ha_t *ha_sav = ips_ha[highindex];
6886 struct Scsi_Host *sh_sav = ips_sh[highindex];
6887 int i;
6888
6889 for (i = highindex; i > lowindex; i--) {
6890 ips_ha[i] = ips_ha[i - 1];
6891 ips_sh[i] = ips_sh[i - 1];
6892 ips_ha[i]->host_num = i;
6893 }
6894 ha_sav->host_num = lowindex;
6895 ips_ha[lowindex] = ha_sav;
6896 ips_sh[lowindex] = sh_sav;
6897 }
6898
6899 /****************************************************************************/
6900 /* */
6901 /* Routine Name: ips_order_controllers */
6902 /* */
6903 /* Routine Description: */
6904 /* place controllers is the "proper" boot order */
6905 /****************************************************************************/
6906 static void
6907 ips_order_controllers(void)
6908 {
6909 int i, j, tmp, position = 0;
6910 IPS_NVRAM_P5 *nvram;
6911 if (!ips_ha[0])
6912 return;
6913 nvram = ips_ha[0]->nvram;
6914
6915 if (nvram->adapter_order[0]) {
6916 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6917 for (j = position; j < ips_num_controllers; j++) {
6918 switch (ips_ha[j]->ad_type) {
6919 case IPS_ADTYPE_SERVERAID6M:
6920 case IPS_ADTYPE_SERVERAID7M:
6921 if (nvram->adapter_order[i] == 'M') {
6922 ips_shift_controllers(position,
6923 j);
6924 position++;
6925 }
6926 break;
6927 case IPS_ADTYPE_SERVERAID4L:
6928 case IPS_ADTYPE_SERVERAID4M:
6929 case IPS_ADTYPE_SERVERAID4MX:
6930 case IPS_ADTYPE_SERVERAID4LX:
6931 if (nvram->adapter_order[i] == 'N') {
6932 ips_shift_controllers(position,
6933 j);
6934 position++;
6935 }
6936 break;
6937 case IPS_ADTYPE_SERVERAID6I:
6938 case IPS_ADTYPE_SERVERAID5I2:
6939 case IPS_ADTYPE_SERVERAID5I1:
6940 case IPS_ADTYPE_SERVERAID7k:
6941 if (nvram->adapter_order[i] == 'S') {
6942 ips_shift_controllers(position,
6943 j);
6944 position++;
6945 }
6946 break;
6947 case IPS_ADTYPE_SERVERAID:
6948 case IPS_ADTYPE_SERVERAID2:
6949 case IPS_ADTYPE_NAVAJO:
6950 case IPS_ADTYPE_KIOWA:
6951 case IPS_ADTYPE_SERVERAID3L:
6952 case IPS_ADTYPE_SERVERAID3:
6953 case IPS_ADTYPE_SERVERAID4H:
6954 if (nvram->adapter_order[i] == 'A') {
6955 ips_shift_controllers(position,
6956 j);
6957 position++;
6958 }
6959 break;
6960 default:
6961 break;
6962 }
6963 }
6964 }
6965 /* if adapter_order[0], then ordering is complete */
6966 return;
6967 }
6968 /* old bios, use older ordering */
6969 tmp = 0;
6970 for (i = position; i < ips_num_controllers; i++) {
6971 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6972 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6973 ips_shift_controllers(position, i);
6974 position++;
6975 tmp = 1;
6976 }
6977 }
6978 /* if there were no 5I cards, then don't do any extra ordering */
6979 if (!tmp)
6980 return;
6981 for (i = position; i < ips_num_controllers; i++) {
6982 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6983 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6984 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6985 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6986 ips_shift_controllers(position, i);
6987 position++;
6988 }
6989 }
6990
6991 return;
6992 }
6993
6994 /****************************************************************************/
6995 /* */
6996 /* Routine Name: ips_register_scsi */
6997 /* */
6998 /* Routine Description: */
6999 /* perform any registration and setup with the scsi layer */
7000 /****************************************************************************/
7001 static int
7002 ips_register_scsi(int index)
7003 {
7004 struct Scsi_Host *sh;
7005 ips_ha_t *ha, *oldha = ips_ha[index];
7006 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
7007 if (!sh) {
7008 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
7009 "Unable to register controller with SCSI subsystem\n");
7010 return -1;
7011 }
7012 ha = IPS_HA(sh);
7013 memcpy(ha, oldha, sizeof (ips_ha_t));
7014 free_irq(oldha->irq, oldha);
7015 /* Install the interrupt handler with the new ha */
7016 if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) {
7017 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7018 "Unable to install interrupt handler\n");
7019 scsi_host_put(sh);
7020 return -1;
7021 }
7022
7023 kfree(oldha);
7024 ips_sh[index] = sh;
7025 ips_ha[index] = ha;
7026 IPS_SCSI_SET_DEVICE(sh, ha);
7027
7028 /* Store away needed values for later use */
7029 sh->io_port = ha->io_addr;
7030 sh->n_io_port = ha->io_addr ? 255 : 0;
7031 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
7032 sh->irq = ha->irq;
7033 sh->sg_tablesize = sh->hostt->sg_tablesize;
7034 sh->can_queue = sh->hostt->can_queue;
7035 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
7036 sh->unchecked_isa_dma = sh->hostt->unchecked_isa_dma;
7037 sh->use_clustering = sh->hostt->use_clustering;
7038
7039 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,7)
7040 sh->max_sectors = 128;
7041 #endif
7042
7043 sh->max_id = ha->ntargets;
7044 sh->max_lun = ha->nlun;
7045 sh->max_channel = ha->nbus - 1;
7046 sh->can_queue = ha->max_cmds - 1;
7047
7048 IPS_ADD_HOST(sh, NULL);
7049 return 0;
7050 }
7051
7052 /*---------------------------------------------------------------------------*/
7053 /* Routine Name: ips_remove_device */
7054 /* */
7055 /* Routine Description: */
7056 /* Remove one Adapter ( Hot Plugging ) */
7057 /*---------------------------------------------------------------------------*/
7058 static void __devexit
7059 ips_remove_device(struct pci_dev *pci_dev)
7060 {
7061 int i;
7062 struct Scsi_Host *sh;
7063 ips_ha_t *ha;
7064
7065 for (i = 0; i < IPS_MAX_ADAPTERS; i++) {
7066 ha = ips_ha[i];
7067 if (ha) {
7068 if ((pci_dev->bus->number == ha->pcidev->bus->number) &&
7069 (pci_dev->devfn == ha->pcidev->devfn)) {
7070 sh = ips_sh[i];
7071 ips_release(sh);
7072 }
7073 }
7074 }
7075 }
7076
7077 /****************************************************************************/
7078 /* */
7079 /* Routine Name: ips_module_init */
7080 /* */
7081 /* Routine Description: */
7082 /* function called on module load */
7083 /****************************************************************************/
7084 static int __init
7085 ips_module_init(void)
7086 {
7087 if (pci_module_init(&ips_pci_driver) < 0)
7088 return -ENODEV;
7089 ips_driver_template.module = THIS_MODULE;
7090 ips_order_controllers();
7091 if (IPS_REGISTER_HOSTS(&ips_driver_template)) {
7092 pci_unregister_driver(&ips_pci_driver);
7093 return -ENODEV;
7094 }
7095 register_reboot_notifier(&ips_notifier);
7096 return 0;
7097 }
7098
7099 /****************************************************************************/
7100 /* */
7101 /* Routine Name: ips_module_exit */
7102 /* */
7103 /* Routine Description: */
7104 /* function called on module unload */
7105 /****************************************************************************/
7106 static void __exit
7107 ips_module_exit(void)
7108 {
7109 IPS_UNREGISTER_HOSTS(&ips_driver_template);
7110 pci_unregister_driver(&ips_pci_driver);
7111 unregister_reboot_notifier(&ips_notifier);
7112 }
7113
7114 module_init(ips_module_init);
7115 module_exit(ips_module_exit);
7116
7117 /*---------------------------------------------------------------------------*/
7118 /* Routine Name: ips_insert_device */
7119 /* */
7120 /* Routine Description: */
7121 /* Add One Adapter ( Hot Plug ) */
7122 /* */
7123 /* Return Value: */
7124 /* 0 if Successful, else non-zero */
7125 /*---------------------------------------------------------------------------*/
7126 static int __devinit
7127 ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
7128 {
7129 int index;
7130 int rc;
7131
7132 METHOD_TRACE("ips_insert_device", 1);
7133 if (pci_enable_device(pci_dev))
7134 return -1;
7135
7136 rc = ips_init_phase1(pci_dev, &index);
7137 if (rc == SUCCESS)
7138 rc = ips_init_phase2(index);
7139
7140 if (ips_hotplug)
7141 if (ips_register_scsi(index)) {
7142 ips_free(ips_ha[index]);
7143 rc = -1;
7144 }
7145
7146 if (rc == SUCCESS)
7147 ips_num_controllers++;
7148
7149 ips_next_controller = ips_num_controllers;
7150 return rc;
7151 }
7152
7153 /*---------------------------------------------------------------------------*/
7154 /* Routine Name: ips_init_phase1 */
7155 /* */
7156 /* Routine Description: */
7157 /* Adapter Initialization */
7158 /* */
7159 /* Return Value: */
7160 /* 0 if Successful, else non-zero */
7161 /*---------------------------------------------------------------------------*/
7162 static int
7163 ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
7164 {
7165 ips_ha_t *ha;
7166 uint32_t io_addr;
7167 uint32_t mem_addr;
7168 uint32_t io_len;
7169 uint32_t mem_len;
7170 uint8_t revision_id;
7171 uint8_t bus;
7172 uint8_t func;
7173 uint8_t irq;
7174 uint16_t subdevice_id;
7175 int j;
7176 int index;
7177 dma_addr_t dma_address;
7178 char *ioremap_ptr;
7179 char *mem_ptr;
7180 uint32_t IsDead;
7181
7182 METHOD_TRACE("ips_init_phase1", 1);
7183 index = IPS_MAX_ADAPTERS;
7184 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
7185 if (ips_ha[j] == 0) {
7186 index = j;
7187 break;
7188 }
7189 }
7190
7191 if (index >= IPS_MAX_ADAPTERS)
7192 return -1;
7193
7194 /* stuff that we get in dev */
7195 irq = pci_dev->irq;
7196 bus = pci_dev->bus->number;
7197 func = pci_dev->devfn;
7198
7199 /* Init MEM/IO addresses to 0 */
7200 mem_addr = 0;
7201 io_addr = 0;
7202 mem_len = 0;
7203 io_len = 0;
7204
7205 for (j = 0; j < 2; j++) {
7206 if (!pci_resource_start(pci_dev, j))
7207 break;
7208
7209 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
7210 io_addr = pci_resource_start(pci_dev, j);
7211 io_len = pci_resource_len(pci_dev, j);
7212 } else {
7213 mem_addr = pci_resource_start(pci_dev, j);
7214 mem_len = pci_resource_len(pci_dev, j);
7215 }
7216 }
7217
7218 /* setup memory mapped area (if applicable) */
7219 if (mem_addr) {
7220 uint32_t base;
7221 uint32_t offs;
7222
7223 if (!request_mem_region(mem_addr, mem_len, "ips")) {
7224 IPS_PRINTK(KERN_WARNING, pci_dev,
7225 "Couldn't allocate IO Memory space %x len %d.\n",
7226 mem_addr, mem_len);
7227 return -1;
7228 }
7229
7230 base = mem_addr & PAGE_MASK;
7231 offs = mem_addr - base;
7232 ioremap_ptr = ioremap(base, PAGE_SIZE);
7233 mem_ptr = ioremap_ptr + offs;
7234 } else {
7235 ioremap_ptr = NULL;
7236 mem_ptr = NULL;
7237 }
7238
7239 /* setup I/O mapped area (if applicable) */
7240 if (io_addr) {
7241 if (!request_region(io_addr, io_len, "ips")) {
7242 IPS_PRINTK(KERN_WARNING, pci_dev,
7243 "Couldn't allocate IO space %x len %d.\n",
7244 io_addr, io_len);
7245 return -1;
7246 }
7247 }
7248
7249 /* get the revision ID */
7250 if (pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id)) {
7251 IPS_PRINTK(KERN_WARNING, pci_dev, "Can't get revision id.\n");
7252 return -1;
7253 }
7254
7255 subdevice_id = pci_dev->subsystem_device;
7256
7257 /* found a controller */
7258 ha = kmalloc(sizeof (ips_ha_t), GFP_KERNEL);
7259 if (ha == NULL) {
7260 IPS_PRINTK(KERN_WARNING, pci_dev,
7261 "Unable to allocate temporary ha struct\n");
7262 return -1;
7263 }
7264
7265 memset(ha, 0, sizeof (ips_ha_t));
7266
7267 ips_sh[index] = NULL;
7268 ips_ha[index] = ha;
7269 ha->active = 1;
7270
7271 /* Store info in HA structure */
7272 ha->irq = irq;
7273 ha->io_addr = io_addr;
7274 ha->io_len = io_len;
7275 ha->mem_addr = mem_addr;
7276 ha->mem_len = mem_len;
7277 ha->mem_ptr = mem_ptr;
7278 ha->ioremap_ptr = ioremap_ptr;
7279 ha->host_num = (uint32_t) index;
7280 ha->revision_id = revision_id;
7281 ha->slot_num = PCI_SLOT(pci_dev->devfn);
7282 ha->device_id = pci_dev->device;
7283 ha->subdevice_id = subdevice_id;
7284 ha->pcidev = pci_dev;
7285
7286 /*
7287 * Set the pci_dev's dma_mask. Not all adapters support 64bit
7288 * addressing so don't enable it if the adapter can't support
7289 * it! Also, don't use 64bit addressing if dma addresses
7290 * are guaranteed to be < 4G.
7291 */
7292 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
7293 !pci_set_dma_mask(ha->pcidev, 0xffffffffffffffffULL)) {
7294 (ha)->flags |= IPS_HA_ENH_SG;
7295 } else {
7296 if (pci_set_dma_mask(ha->pcidev, 0xffffffffULL) != 0) {
7297 printk(KERN_WARNING "Unable to set DMA Mask\n");
7298 return ips_abort_init(ha, index);
7299 }
7300 }
7301 if(ips_cd_boot && !ips_FlashData){
7302 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
7303 &ips_flashbusaddr);
7304 }
7305
7306 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
7307 &ha->enq_busaddr);
7308 if (!ha->enq) {
7309 IPS_PRINTK(KERN_WARNING, pci_dev,
7310 "Unable to allocate host inquiry structure\n");
7311 return ips_abort_init(ha, index);
7312 }
7313
7314 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
7315 sizeof (IPS_IO_CMD), &dma_address);
7316 if (!ha->adapt) {
7317 IPS_PRINTK(KERN_WARNING, pci_dev,
7318 "Unable to allocate host adapt & dummy structures\n");
7319 return ips_abort_init(ha, index);
7320 }
7321 ha->adapt->hw_status_start = dma_address;
7322 ha->dummy = (void *) (ha->adapt + 1);
7323
7324
7325
7326 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7327 if (!ha->logical_drive_info) {
7328 IPS_PRINTK(KERN_WARNING, pci_dev,
7329 "Unable to allocate logical drive info structure\n");
7330 return ips_abort_init(ha, index);
7331 }
7332 ha->logical_drive_info_dma_addr = dma_address;
7333
7334
7335 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7336
7337 if (!ha->conf) {
7338 IPS_PRINTK(KERN_WARNING, pci_dev,
7339 "Unable to allocate host conf structure\n");
7340 return ips_abort_init(ha, index);
7341 }
7342
7343 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7344
7345 if (!ha->nvram) {
7346 IPS_PRINTK(KERN_WARNING, pci_dev,
7347 "Unable to allocate host NVRAM structure\n");
7348 return ips_abort_init(ha, index);
7349 }
7350
7351 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7352
7353 if (!ha->subsys) {
7354 IPS_PRINTK(KERN_WARNING, pci_dev,
7355 "Unable to allocate host subsystem structure\n");
7356 return ips_abort_init(ha, index);
7357 }
7358
7359 /* the ioctl buffer is now used during adapter initialization, so its
7360 * successful allocation is now required */
7361 if (ips_ioctlsize < PAGE_SIZE)
7362 ips_ioctlsize = PAGE_SIZE;
7363
7364 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7365 &ha->ioctl_busaddr);
7366 ha->ioctl_len = ips_ioctlsize;
7367 if (!ha->ioctl_data) {
7368 IPS_PRINTK(KERN_WARNING, pci_dev,
7369 "Unable to allocate IOCTL data\n");
7370 return ips_abort_init(ha, index);
7371 }
7372
7373 /*
7374 * Setup Functions
7375 */
7376 ips_setup_funclist(ha);
7377
7378 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7379 /* If Morpheus appears dead, reset it */
7380 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7381 if (IsDead == 0xDEADBEEF) {
7382 ips_reset_morpheus(ha);
7383 }
7384 }
7385
7386 /*
7387 * Initialize the card if it isn't already
7388 */
7389
7390 if (!(*ha->func.isinit) (ha)) {
7391 if (!(*ha->func.init) (ha)) {
7392 /*
7393 * Initialization failed
7394 */
7395 IPS_PRINTK(KERN_WARNING, pci_dev,
7396 "Unable to initialize controller\n");
7397 return ips_abort_init(ha, index);
7398 }
7399 }
7400
7401 *indexPtr = index;
7402 return SUCCESS;
7403 }
7404
7405 /*---------------------------------------------------------------------------*/
7406 /* Routine Name: ips_init_phase2 */
7407 /* */
7408 /* Routine Description: */
7409 /* Adapter Initialization Phase 2 */
7410 /* */
7411 /* Return Value: */
7412 /* 0 if Successful, else non-zero */
7413 /*---------------------------------------------------------------------------*/
7414 static int
7415 ips_init_phase2(int index)
7416 {
7417 ips_ha_t *ha;
7418
7419 ha = ips_ha[index];
7420
7421 METHOD_TRACE("ips_init_phase2", 1);
7422 if (!ha->active) {
7423 ips_ha[index] = NULL;
7424 return -1;
7425 }
7426
7427 /* Install the interrupt handler */
7428 if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) {
7429 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7430 "Unable to install interrupt handler\n");
7431 return ips_abort_init(ha, index);
7432 }
7433
7434 /*
7435 * Allocate a temporary SCB for initialization
7436 */
7437 ha->max_cmds = 1;
7438 if (!ips_allocatescbs(ha)) {
7439 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7440 "Unable to allocate a CCB\n");
7441 free_irq(ha->irq, ha);
7442 return ips_abort_init(ha, index);
7443 }
7444
7445 if (!ips_hainit(ha)) {
7446 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7447 "Unable to initialize controller\n");
7448 free_irq(ha->irq, ha);
7449 return ips_abort_init(ha, index);
7450 }
7451 /* Free the temporary SCB */
7452 ips_deallocatescbs(ha, 1);
7453
7454 /* allocate CCBs */
7455 if (!ips_allocatescbs(ha)) {
7456 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7457 "Unable to allocate CCBs\n");
7458 free_irq(ha->irq, ha);
7459 return ips_abort_init(ha, index);
7460 }
7461
7462 return SUCCESS;
7463 }
7464
7465 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,9)
7466 MODULE_LICENSE("GPL");
7467 #endif
7468
7469 #ifdef MODULE_DESCRIPTION
7470 MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7471 #endif
7472
7473 #ifdef MODULE_VERSION
7474 MODULE_VERSION(IPS_VER_STRING);
7475 #endif
7476
7477
7478 /*
7479 * Overrides for Emacs so that we almost follow Linus's tabbing style.
7480 * Emacs will notice this stuff at the end of the file and automatically
7481 * adjust the settings for this buffer only. This must remain at the end
7482 * of the file.
7483 * ---------------------------------------------------------------------------
7484 * Local variables:
7485 * c-indent-level: 2
7486 * c-brace-imaginary-offset: 0
7487 * c-brace-offset: -2
7488 * c-argdecl-indent: 2
7489 * c-label-offset: -2
7490 * c-continued-statement-offset: 2
7491 * c-continued-brace-offset: 0
7492 * indent-tabs-mode: nil
7493 * tab-width: 8
7494 * End:
7495 */
7496