1 /* $Id: esp.h,v 1.28 2000/03/30 01:33:17 davem Exp $ 2 * esp.h: Defines and structures for the Sparc ESP (Enhanced SCSI 3 * Processor) driver under Linux. 4 * 5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 6 */ 7 8 #ifndef _SPARC_ESP_H 9 #define _SPARC_ESP_H 10 11 #include <linux/config.h> 12 13 /* For dvma controller register definitions. */ 14 #include <asm/dma.h> 15 16 /* The ESP SCSI controllers have their register sets in three 17 * "classes": 18 * 19 * 1) Registers which are both read and write. 20 * 2) Registers which are read only. 21 * 3) Registers which are write only. 22 * 23 * Yet, they all live within the same IO space. 24 */ 25 26 /* All the ESP registers are one byte each and are accessed longwords 27 * apart with a big-endian ordering to the bytes. 28 */ 29 /* Access Description Offset */ 30 #define ESP_TCLOW 0x00UL /* rw Low bits of the transfer count 0x00 */ 31 #define ESP_TCMED 0x04UL /* rw Mid bits of the transfer count 0x04 */ 32 #define ESP_FDATA 0x08UL /* rw FIFO data bits 0x08 */ 33 #define ESP_CMD 0x0cUL /* rw SCSI command bits 0x0c */ 34 #define ESP_STATUS 0x10UL /* ro ESP status register 0x10 */ 35 #define ESP_BUSID ESP_STATUS /* wo Bus ID for select/reselect 0x10 */ 36 #define ESP_INTRPT 0x14UL /* ro Kind of interrupt 0x14 */ 37 #define ESP_TIMEO ESP_INTRPT /* wo Timeout value for select/resel 0x14 */ 38 #define ESP_SSTEP 0x18UL /* ro Sequence step register 0x18 */ 39 #define ESP_STP ESP_SSTEP /* wo Transfer period per sync 0x18 */ 40 #define ESP_FFLAGS 0x1cUL /* ro Bits of current FIFO info 0x1c */ 41 #define ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */ 42 #define ESP_CFG1 0x20UL /* rw First configuration register 0x20 */ 43 #define ESP_CFACT 0x24UL /* wo Clock conversion factor 0x24 */ 44 #define ESP_STATUS2 ESP_CFACT /* ro HME status2 register 0x24 */ 45 #define ESP_CTEST 0x28UL /* wo Chip test register 0x28 */ 46 #define ESP_CFG2 0x2cUL /* rw Second configuration register 0x2c */ 47 #define ESP_CFG3 0x30UL /* rw Third configuration register 0x30 */ 48 #define ESP_TCHI 0x38UL /* rw High bits of transfer count 0x38 */ 49 #define ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */ 50 #define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */ 51 #define ESP_FGRND 0x3cUL /* rw Data base for fifo 0x3c */ 52 #define FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */ 53 #define ESP_REG_SIZE 0x40UL 54 55 /* Various revisions of the ESP board. */ 56 enum esp_rev { 57 esp100 = 0x00, /* NCR53C90 - very broken */ 58 esp100a = 0x01, /* NCR53C90A */ 59 esp236 = 0x02, 60 fas236 = 0x03, 61 fas100a = 0x04, 62 fast = 0x05, 63 fashme = 0x06, 64 espunknown = 0x07 65 }; 66 67 /* We get one of these for each ESP probed. */ 68 struct esp { 69 spinlock_t lock; 70 unsigned long eregs; /* ESP controller registers */ 71 unsigned long dregs; /* DMA controller registers */ 72 struct sbus_dma *dma; /* DMA controller sw state */ 73 struct Scsi_Host *ehost; /* Backpointer to SCSI Host */ 74 struct sbus_dev *sdev; /* Pointer to SBus entry */ 75 76 /* ESP Configuration Registers */ 77 u8 config1; /* Copy of the 1st config register */ 78 u8 config2; /* Copy of the 2nd config register */ 79 u8 config3[16]; /* Copy of the 3rd config register */ 80 81 /* The current command we are sending to the ESP chip. This esp_command 82 * ptr needs to be mapped in DVMA area so we can send commands and read 83 * from the ESP fifo without burning precious CPU cycles. Programmed I/O 84 * sucks when we have the DVMA to do it for us. The ESP is stupid and will 85 * only send out 6, 10, and 12 byte SCSI commands, others we need to send 86 * one byte at a time. esp_slowcmd being set says that we are doing one 87 * of the command types ESP doesn't understand, esp_scmdp keeps track of 88 * which byte we are sending, esp_scmdleft says how many bytes to go. 89 */ 90 volatile u8 *esp_command; /* Location of command (CPU view) */ 91 __u32 esp_command_dvma;/* Location of command (DVMA view) */ 92 unsigned char esp_clen; /* Length of this command */ 93 unsigned char esp_slowcmd; 94 unsigned char *esp_scmdp; 95 unsigned char esp_scmdleft; 96 97 /* The following are used to determine the cause of an IRQ. Upon every 98 * IRQ entry we synchronize these with the hardware registers. 99 */ 100 u8 ireg; /* Copy of ESP interrupt register */ 101 u8 sreg; /* Copy of ESP status register */ 102 u8 seqreg; /* Copy of ESP sequence step register */ 103 u8 sreg2; /* Copy of HME status2 register */ 104 105 /* To save register writes to the ESP, which can be expensive, we 106 * keep track of the previous value that various registers had for 107 * the last target we connected to. If they are the same for the 108 * current target, we skip the register writes as they are not needed. 109 */ 110 u8 prev_soff, prev_stp; 111 u8 prev_cfg3, __cache_pad; 112 113 /* We also keep a cache of the previous FAS/HME DMA CSR register value. */ 114 u32 prev_hme_dmacsr; 115 116 /* The HME is the biggest piece of shit I have ever seen. */ 117 u8 hme_fifo_workaround_buffer[16 * 2]; 118 u8 hme_fifo_workaround_count; 119 120 /* For each target we keep track of save/restore data 121 * pointer information. This needs to be updated majorly 122 * when we add support for tagged queueing. -DaveM 123 */ 124 struct esp_pointers { 125 char *saved_ptr; 126 struct scatterlist *saved_buffer; 127 int saved_this_residual; 128 int saved_buffers_residual; 129 } data_pointers[16] /*XXX [MAX_TAGS_PER_TARGET]*/; 130 131 /* Clock periods, frequencies, synchronization, etc. */ 132 unsigned int cfreq; /* Clock frequency in HZ */ 133 unsigned int cfact; /* Clock conversion factor */ 134 unsigned int raw_cfact; /* Raw copy from probing */ 135 unsigned int ccycle; /* One ESP clock cycle */ 136 unsigned int ctick; /* One ESP clock time */ 137 unsigned int radelay; /* FAST chip req/ack delay */ 138 unsigned int neg_defp; /* Default negotiation period */ 139 unsigned int sync_defp; /* Default sync transfer period */ 140 unsigned int max_period; /* longest our period can be */ 141 unsigned int min_period; /* shortest period we can withstand */ 142 143 struct esp *next; /* Next ESP we probed or NULL */ 144 char prom_name[64]; /* Name of ESP device from prom */ 145 int prom_node; /* Prom node where ESP found */ 146 int esp_id; /* Unique per-ESP ID number */ 147 148 /* For slow to medium speed input clock rates we shoot for 5mb/s, 149 * but for high input clock rates we try to do 10mb/s although I 150 * don't think a transfer can even run that fast with an ESP even 151 * with DMA2 scatter gather pipelining. 152 */ 153 #define SYNC_DEFP_SLOW 0x32 /* 5mb/s */ 154 #define SYNC_DEFP_FAST 0x19 /* 10mb/s */ 155 156 unsigned int snip; /* Sync. negotiation in progress */ 157 unsigned int wnip; /* WIDE negotiation in progress */ 158 unsigned int targets_present;/* targets spoken to before */ 159 160 int current_transfer_size; /* Set at beginning of data dma */ 161 162 u8 espcmdlog[32]; /* Log of current esp cmds sent. */ 163 u8 espcmdent; /* Current entry in esp cmd log. */ 164 165 /* Misc. info about this ESP */ 166 enum esp_rev erev; /* ESP revision */ 167 int irq; /* SBus IRQ for this ESP */ 168 int scsi_id; /* Who am I as initiator? */ 169 int scsi_id_mask; /* Bitmask of 'me'. */ 170 int diff; /* Differential SCSI bus? */ 171 int bursts; /* Burst sizes our DVMA supports */ 172 173 /* Our command queues, only one cmd lives in the current_SC queue. */ 174 Scsi_Cmnd *issue_SC; /* Commands to be issued */ 175 Scsi_Cmnd *current_SC; /* Who is currently working the bus */ 176 Scsi_Cmnd *disconnected_SC;/* Commands disconnected from the bus */ 177 178 /* Message goo */ 179 u8 cur_msgout[16]; 180 u8 cur_msgin[16]; 181 u8 prevmsgout, prevmsgin; 182 u8 msgout_len, msgin_len; 183 u8 msgout_ctr, msgin_ctr; 184 185 /* States that we cannot keep in the per cmd structure because they 186 * cannot be assosciated with any specific command. 187 */ 188 u8 resetting_bus; 189 }; 190 191 /* Bitfield meanings for the above registers. */ 192 193 /* ESP config reg 1, read-write, found on all ESP chips */ 194 #define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */ 195 #define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */ 196 #define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */ 197 #define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */ 198 #define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */ 199 #define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */ 200 201 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */ 202 #define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */ 203 #define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */ 204 #define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */ 205 #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tmode only) */ 206 #define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */ 207 #define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */ 208 #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */ 209 #define ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */ 210 #define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,esp216) */ 211 #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (esp236) */ 212 #define ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */ 213 #define ESP_CONFIG2_HME32 0x80 /* HME 32 extended */ 214 #define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */ 215 216 /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */ 217 #define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */ 218 #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */ 219 #define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */ 220 #define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */ 221 #define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */ 222 #define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */ 223 #define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */ 224 #define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */ 225 #define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */ 226 #define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */ 227 #define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */ 228 #define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */ 229 #define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */ 230 #define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */ 231 #define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */ 232 #define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */ 233 234 /* ESP command register read-write */ 235 /* Group 1 commands: These may be sent at any point in time to the ESP 236 * chip. None of them can generate interrupts 'cept 237 * the "SCSI bus reset" command if you have not disabled 238 * SCSI reset interrupts in the config1 ESP register. 239 */ 240 #define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */ 241 #define ESP_CMD_FLUSH 0x01 /* FIFO Flush */ 242 #define ESP_CMD_RC 0x02 /* Chip reset */ 243 #define ESP_CMD_RS 0x03 /* SCSI bus reset */ 244 245 /* Group 2 commands: ESP must be an initiator and connected to a target 246 * for these commands to work. 247 */ 248 #define ESP_CMD_TI 0x10 /* Transfer Information */ 249 #define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */ 250 #define ESP_CMD_MOK 0x12 /* Message okie-dokie */ 251 #define ESP_CMD_TPAD 0x18 /* Transfer Pad */ 252 #define ESP_CMD_SATN 0x1a /* Set ATN */ 253 #define ESP_CMD_RATN 0x1b /* De-assert ATN */ 254 255 /* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected 256 * to a target as the initiator for these commands to work. 257 */ 258 #define ESP_CMD_SMSG 0x20 /* Send message */ 259 #define ESP_CMD_SSTAT 0x21 /* Send status */ 260 #define ESP_CMD_SDATA 0x22 /* Send data */ 261 #define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */ 262 #define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */ 263 #define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */ 264 #define ESP_CMD_DCNCT 0x27 /* Disconnect */ 265 #define ESP_CMD_RMSG 0x28 /* Receive Message */ 266 #define ESP_CMD_RCMD 0x29 /* Receive Command */ 267 #define ESP_CMD_RDATA 0x2a /* Receive Data */ 268 #define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */ 269 270 /* Group 4 commands: The ESP must be in the disconnected state and must 271 * not be connected to any targets as initiator for 272 * these commands to work. 273 */ 274 #define ESP_CMD_RSEL 0x40 /* Reselect */ 275 #define ESP_CMD_SEL 0x41 /* Select w/o ATN */ 276 #define ESP_CMD_SELA 0x42 /* Select w/ATN */ 277 #define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */ 278 #define ESP_CMD_ESEL 0x44 /* Enable selection */ 279 #define ESP_CMD_DSEL 0x45 /* Disable selections */ 280 #define ESP_CMD_SA3 0x46 /* Select w/ATN3 */ 281 #define ESP_CMD_RSEL3 0x47 /* Reselect3 */ 282 283 /* This bit enables the ESP's DMA on the SBus */ 284 #define ESP_CMD_DMA 0x80 /* Do DMA? */ 285 286 287 /* ESP status register read-only */ 288 #define ESP_STAT_PIO 0x01 /* IO phase bit */ 289 #define ESP_STAT_PCD 0x02 /* CD phase bit */ 290 #define ESP_STAT_PMSG 0x04 /* MSG phase bit */ 291 #define ESP_STAT_PMASK 0x07 /* Mask of phase bits */ 292 #define ESP_STAT_TDONE 0x08 /* Transfer Completed */ 293 #define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */ 294 #define ESP_STAT_PERR 0x20 /* Parity error */ 295 #define ESP_STAT_SPAM 0x40 /* Real bad error */ 296 /* This indicates the 'interrupt pending' condition on esp236, it is a reserved 297 * bit on other revs of the ESP. 298 */ 299 #define ESP_STAT_INTR 0x80 /* Interrupt */ 300 301 /* HME only: status 2 register */ 302 #define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */ 303 #define ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */ 304 #define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */ 305 #define ESP_STAT2_CREGA 0x08 /* The command reg is active now */ 306 #define ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */ 307 #define ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */ 308 #define ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */ 309 #define ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */ 310 311 /* The status register can be masked with ESP_STAT_PMASK and compared 312 * with the following values to determine the current phase the ESP 313 * (at least thinks it) is in. For our purposes we also add our own 314 * software 'done' bit for our phase management engine. 315 */ 316 #define ESP_DOP (0) /* Data Out */ 317 #define ESP_DIP (ESP_STAT_PIO) /* Data In */ 318 #define ESP_CMDP (ESP_STAT_PCD) /* Command */ 319 #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */ 320 #define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */ 321 #define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */ 322 323 /* ESP interrupt register read-only */ 324 #define ESP_INTR_S 0x01 /* Select w/o ATN */ 325 #define ESP_INTR_SATN 0x02 /* Select w/ATN */ 326 #define ESP_INTR_RSEL 0x04 /* Reselected */ 327 #define ESP_INTR_FDONE 0x08 /* Function done */ 328 #define ESP_INTR_BSERV 0x10 /* Bus service */ 329 #define ESP_INTR_DC 0x20 /* Disconnect */ 330 #define ESP_INTR_IC 0x40 /* Illegal command given */ 331 #define ESP_INTR_SR 0x80 /* SCSI bus reset detected */ 332 333 /* Interrupt status macros */ 334 #define ESP_SRESET_IRQ(esp) ((esp)->intreg & (ESP_INTR_SR)) 335 #define ESP_ILLCMD_IRQ(esp) ((esp)->intreg & (ESP_INTR_IC)) 336 #define ESP_SELECT_WITH_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_SATN)) 337 #define ESP_SELECT_WITHOUT_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_S)) 338 #define ESP_SELECTION_IRQ(esp) ((ESP_SELECT_WITH_ATN_IRQ(esp)) || \ 339 (ESP_SELECT_WITHOUT_ATN_IRQ(esp))) 340 #define ESP_RESELECTION_IRQ(esp) ((esp)->intreg & (ESP_INTR_RSEL)) 341 342 /* ESP sequence step register read-only */ 343 #define ESP_STEP_VBITS 0x07 /* Valid bits */ 344 #define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */ 345 #define ESP_STEP_SID 0x01 /* One msg byte sent */ 346 #define ESP_STEP_NCMD 0x02 /* Was not in command phase */ 347 #define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd 348 * bytes to be lost 349 */ 350 #define ESP_STEP_FINI4 0x04 /* Command was sent ok */ 351 352 /* Ho hum, some ESP's set the step register to this as well... */ 353 #define ESP_STEP_FINI5 0x05 354 #define ESP_STEP_FINI6 0x06 355 #define ESP_STEP_FINI7 0x07 356 357 /* ESP chip-test register read-write */ 358 #define ESP_TEST_TARG 0x01 /* Target test mode */ 359 #define ESP_TEST_INI 0x02 /* Initiator test mode */ 360 #define ESP_TEST_TS 0x04 /* Tristate test mode */ 361 362 /* ESP unique ID register read-only, found on fas236+fas100a only */ 363 #define ESP_UID_F100A 0x00 /* ESP FAS100A */ 364 #define ESP_UID_F236 0x02 /* ESP FAS236 */ 365 #define ESP_UID_REV 0x07 /* ESP revision */ 366 #define ESP_UID_FAM 0xf8 /* ESP family */ 367 368 /* ESP fifo flags register read-only */ 369 /* Note that the following implies a 16 byte FIFO on the ESP. */ 370 #define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */ 371 #define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */ 372 #define ESP_FF_SSTEP 0xe0 /* Sequence step */ 373 374 /* ESP clock conversion factor register write-only */ 375 #define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */ 376 #define ESP_CCF_NEVER 0x01 /* Set it to this and die */ 377 #define ESP_CCF_F2 0x02 /* 10MHz */ 378 #define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */ 379 #define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */ 380 #define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */ 381 #define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */ 382 #define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */ 383 384 /* HME only... */ 385 #define ESP_BUSID_RESELID 0x10 386 #define ESP_BUSID_CTR32BIT 0x40 387 388 #define ESP_BUS_TIMEOUT 275 /* In milli-seconds */ 389 #define ESP_TIMEO_CONST 8192 390 #define ESP_NEG_DEFP(mhz, cfact) \ 391 ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact))) 392 #define ESP_MHZ_TO_CYCLE(mhertz) ((1000000000) / ((mhertz) / 1000)) 393 #define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000)) 394 395 extern int esp_detect(struct SHT *); 396 extern const char *esp_info(struct Scsi_Host *); 397 extern int esp_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *)); 398 extern int esp_command(Scsi_Cmnd *); 399 extern int esp_abort(Scsi_Cmnd *); 400 extern int esp_reset(Scsi_Cmnd *, unsigned int); 401 extern int esp_proc_info(char *buffer, char **start, off_t offset, int length, 402 int hostno, int inout); 403 extern int esp_revoke(Scsi_Device* SDptr); 404 405 #ifdef CONFIG_SPARC64 406 #define SCSI_SPARC_ESP { \ 407 proc_name: "esp", \ 408 proc_info: &esp_proc_info, \ 409 name: "Sun ESP 100/100a/200", \ 410 detect: esp_detect, \ 411 revoke: esp_revoke, \ 412 info: esp_info, \ 413 command: esp_command, \ 414 queuecommand: esp_queue, \ 415 abort: esp_abort, \ 416 reset: esp_reset, \ 417 can_queue: 7, \ 418 this_id: 7, \ 419 sg_tablesize: SG_ALL, \ 420 cmd_per_lun: 1, \ 421 use_clustering: ENABLE_CLUSTERING, \ 422 use_new_eh_code: 0, \ 423 highmem_io: 1 \ 424 } 425 #else 426 /* Sparc32's iommu code cannot handle highmem pages yet. */ 427 #define SCSI_SPARC_ESP { \ 428 proc_name: "esp", \ 429 proc_info: &esp_proc_info, \ 430 name: "Sun ESP 100/100a/200", \ 431 detect: esp_detect, \ 432 revoke: esp_revoke, \ 433 info: esp_info, \ 434 command: esp_command, \ 435 queuecommand: esp_queue, \ 436 abort: esp_abort, \ 437 reset: esp_reset, \ 438 can_queue: 7, \ 439 this_id: 7, \ 440 sg_tablesize: SG_ALL, \ 441 cmd_per_lun: 1, \ 442 use_clustering: ENABLE_CLUSTERING, \ 443 } 444 #endif 445 446 /* For our interrupt engine. */ 447 #define for_each_esp(esp) \ 448 for((esp) = espchain; (esp); (esp) = (esp)->next) 449 450 #endif /* !(_SPARC_ESP_H) */ 451