1 /* blz1230.c: Driver for Blizzard 1230 SCSI IV Controller.
2 *
3 * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
4 *
5 * This driver is based on the CyberStorm driver, hence the occasional
6 * reference to CyberStorm.
7 */
8
9 /* TODO:
10 *
11 * 1) Figure out how to make a cleaner merge with the sparc driver with regard
12 * to the caches and the Sparc MMU mapping.
13 * 2) Make as few routines required outside the generic driver. A lot of the
14 * routines in this file used to be inline!
15 */
16
17 #include <linux/module.h>
18
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/types.h>
23 #include <linux/string.h>
24 #include <linux/slab.h>
25 #include <linux/blk.h>
26 #include <linux/proc_fs.h>
27 #include <linux/stat.h>
28
29 #include "scsi.h"
30 #include "hosts.h"
31 #include "NCR53C9x.h"
32 #include "blz1230.h"
33
34 #include <linux/zorro.h>
35 #include <asm/irq.h>
36 #include <asm/amigaints.h>
37 #include <asm/amigahw.h>
38
39 #include <asm/pgtable.h>
40
41 #define MKIV 1
42
43 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
44 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
45 static void dma_dump_state(struct NCR_ESP *esp);
46 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
47 static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
48 static void dma_ints_off(struct NCR_ESP *esp);
49 static void dma_ints_on(struct NCR_ESP *esp);
50 static int dma_irq_p(struct NCR_ESP *esp);
51 static int dma_ports_p(struct NCR_ESP *esp);
52 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
53
54 static volatile unsigned char cmd_buffer[16];
55 /* This is where all commands are put
56 * before they are transferred to the ESP chip
57 * via PIO.
58 */
59
60 /***************************************************************** Detection */
blz1230_esp_detect(Scsi_Host_Template * tpnt)61 int __init blz1230_esp_detect(Scsi_Host_Template *tpnt)
62 {
63 struct NCR_ESP *esp;
64 struct zorro_dev *z = NULL;
65 unsigned long address;
66 struct ESP_regs *eregs;
67 unsigned long board;
68
69 #if MKIV
70 #define REAL_BLZ1230_ID ZORRO_PROD_PHASE5_BLIZZARD_1230_IV_1260
71 #define REAL_BLZ1230_ESP_ADDR BLZ1230_ESP_ADDR
72 #define REAL_BLZ1230_DMA_ADDR BLZ1230_DMA_ADDR
73 #else
74 #define REAL_BLZ1230_ID ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060
75 #define REAL_BLZ1230_ESP_ADDR BLZ1230II_ESP_ADDR
76 #define REAL_BLZ1230_DMA_ADDR BLZ1230II_DMA_ADDR
77 #endif
78
79 if ((z = zorro_find_device(REAL_BLZ1230_ID, z))) {
80 board = z->resource.start;
81 if (request_mem_region(board+REAL_BLZ1230_ESP_ADDR,
82 sizeof(struct ESP_regs), "NCR53C9x")) {
83 /* Do some magic to figure out if the blizzard is
84 * equipped with a SCSI controller
85 */
86 address = ZTWO_VADDR(board);
87 eregs = (struct ESP_regs *)(address + REAL_BLZ1230_ESP_ADDR);
88 esp = esp_allocate(tpnt, (void *)board+REAL_BLZ1230_ESP_ADDR);
89
90 esp_write(eregs->esp_cfg1, (ESP_CONFIG1_PENABLE | 7));
91 udelay(5);
92 if(esp_read(eregs->esp_cfg1) != (ESP_CONFIG1_PENABLE | 7))
93 goto err_out;
94
95 /* Do command transfer with programmed I/O */
96 esp->do_pio_cmds = 1;
97
98 /* Required functions */
99 esp->dma_bytes_sent = &dma_bytes_sent;
100 esp->dma_can_transfer = &dma_can_transfer;
101 esp->dma_dump_state = &dma_dump_state;
102 esp->dma_init_read = &dma_init_read;
103 esp->dma_init_write = &dma_init_write;
104 esp->dma_ints_off = &dma_ints_off;
105 esp->dma_ints_on = &dma_ints_on;
106 esp->dma_irq_p = &dma_irq_p;
107 esp->dma_ports_p = &dma_ports_p;
108 esp->dma_setup = &dma_setup;
109
110 /* Optional functions */
111 esp->dma_barrier = 0;
112 esp->dma_drain = 0;
113 esp->dma_invalidate = 0;
114 esp->dma_irq_entry = 0;
115 esp->dma_irq_exit = 0;
116 esp->dma_led_on = 0;
117 esp->dma_led_off = 0;
118 esp->dma_poll = 0;
119 esp->dma_reset = 0;
120
121 /* SCSI chip speed */
122 esp->cfreq = 40000000;
123
124 /* The DMA registers on the Blizzard are mapped
125 * relative to the device (i.e. in the same Zorro
126 * I/O block).
127 */
128 esp->dregs = (void *)(address + REAL_BLZ1230_DMA_ADDR);
129
130 /* ESP register base */
131 esp->eregs = eregs;
132
133 /* Set the command buffer */
134 esp->esp_command = cmd_buffer;
135 esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer);
136
137 esp->irq = IRQ_AMIGA_PORTS;
138 esp->slot = board+REAL_BLZ1230_ESP_ADDR;
139 if (request_irq(IRQ_AMIGA_PORTS, esp_intr, SA_SHIRQ,
140 "Blizzard 1230 SCSI IV", esp_intr))
141 goto err_out;
142
143 /* Figure out our scsi ID on the bus */
144 esp->scsi_id = 7;
145
146 /* We don't have a differential SCSI-bus. */
147 esp->diff = 0;
148
149 esp_initialize(esp);
150
151 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
152 esps_running = esps_in_use;
153 return esps_in_use;
154 }
155 }
156 return 0;
157
158 err_out:
159 scsi_unregister(esp->ehost);
160 esp_deallocate(esp);
161 release_mem_region(board+REAL_BLZ1230_ESP_ADDR,
162 sizeof(struct ESP_regs));
163 return 0;
164 }
165
166 /************************************************************* DMA Functions */
dma_bytes_sent(struct NCR_ESP * esp,int fifo_count)167 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
168 {
169 /* Since the Blizzard DMA is fully dedicated to the ESP chip,
170 * the number of bytes sent (to the ESP chip) equals the number
171 * of bytes in the FIFO - there is no buffering in the DMA controller.
172 * XXXX Do I read this right? It is from host to ESP, right?
173 */
174 return fifo_count;
175 }
176
dma_can_transfer(struct NCR_ESP * esp,Scsi_Cmnd * sp)177 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
178 {
179 /* I don't think there's any limit on the Blizzard DMA. So we use what
180 * the ESP chip can handle (24 bit).
181 */
182 unsigned long sz = sp->SCp.this_residual;
183 if(sz > 0x1000000)
184 sz = 0x1000000;
185 return sz;
186 }
187
dma_dump_state(struct NCR_ESP * esp)188 static void dma_dump_state(struct NCR_ESP *esp)
189 {
190 ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
191 custom.intreqr, custom.intenar));
192 }
193
dma_init_read(struct NCR_ESP * esp,__u32 addr,int length)194 void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
195 {
196 #if MKIV
197 struct blz1230_dma_registers *dregs =
198 (struct blz1230_dma_registers *) (esp->dregs);
199 #else
200 struct blz1230II_dma_registers *dregs =
201 (struct blz1230II_dma_registers *) (esp->dregs);
202 #endif
203
204 cache_clear(addr, length);
205
206 addr >>= 1;
207 addr &= ~(BLZ1230_DMA_WRITE);
208
209 /* First set latch */
210 dregs->dma_latch = (addr >> 24) & 0xff;
211
212 /* Then pump the address to the DMA address register */
213 #if MKIV
214 dregs->dma_addr = (addr >> 24) & 0xff;
215 #endif
216 dregs->dma_addr = (addr >> 16) & 0xff;
217 dregs->dma_addr = (addr >> 8) & 0xff;
218 dregs->dma_addr = (addr ) & 0xff;
219 }
220
dma_init_write(struct NCR_ESP * esp,__u32 addr,int length)221 void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
222 {
223 #if MKIV
224 struct blz1230_dma_registers *dregs =
225 (struct blz1230_dma_registers *) (esp->dregs);
226 #else
227 struct blz1230II_dma_registers *dregs =
228 (struct blz1230II_dma_registers *) (esp->dregs);
229 #endif
230
231 cache_push(addr, length);
232
233 addr >>= 1;
234 addr |= BLZ1230_DMA_WRITE;
235
236 /* First set latch */
237 dregs->dma_latch = (addr >> 24) & 0xff;
238
239 /* Then pump the address to the DMA address register */
240 #if MKIV
241 dregs->dma_addr = (addr >> 24) & 0xff;
242 #endif
243 dregs->dma_addr = (addr >> 16) & 0xff;
244 dregs->dma_addr = (addr >> 8) & 0xff;
245 dregs->dma_addr = (addr ) & 0xff;
246 }
247
dma_ints_off(struct NCR_ESP * esp)248 static void dma_ints_off(struct NCR_ESP *esp)
249 {
250 disable_irq(esp->irq);
251 }
252
dma_ints_on(struct NCR_ESP * esp)253 static void dma_ints_on(struct NCR_ESP *esp)
254 {
255 enable_irq(esp->irq);
256 }
257
dma_irq_p(struct NCR_ESP * esp)258 static int dma_irq_p(struct NCR_ESP *esp)
259 {
260 return (esp_read(esp->eregs->esp_status) & ESP_STAT_INTR);
261 }
262
dma_ports_p(struct NCR_ESP * esp)263 static int dma_ports_p(struct NCR_ESP *esp)
264 {
265 return ((custom.intenar) & IF_PORTS);
266 }
267
dma_setup(struct NCR_ESP * esp,__u32 addr,int count,int write)268 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
269 {
270 /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
271 * so when (write) is true, it actually means READ!
272 */
273 if(write){
274 dma_init_read(esp, addr, count);
275 } else {
276 dma_init_write(esp, addr, count);
277 }
278 }
279
280 #define HOSTS_C
281
282 #include "blz1230.h"
283
284 static Scsi_Host_Template driver_template = SCSI_BLZ1230;
285
286 #include "scsi_module.c"
287
blz1230_esp_release(struct Scsi_Host * instance)288 int blz1230_esp_release(struct Scsi_Host *instance)
289 {
290 #ifdef MODULE
291 unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
292 esp_deallocate((struct NCR_ESP *)instance->hostdata);
293 esp_release();
294 release_mem_region(address, sizeof(struct ESP_regs));
295 free_irq(IRQ_AMIGA_PORTS, esp_intr);
296 #endif
297 return 1;
298 }
299
300 MODULE_LICENSE("GPL");
301