1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 */
41
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/pci.h>
45 #include <linux/init.h>
46 #include <linux/blkdev.h>
47 #include <linux/delay.h>
48 #include "scsi.h"
49 #include <scsi/scsi_host.h>
50 #include <linux/libata.h>
51
52 #define DRV_NAME "ata_piix"
53 #define DRV_VERSION "1.05"
54
55 enum {
56 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
57 ICH5_PMR = 0x90, /* port mapping register */
58 ICH5_PCS = 0x92, /* port control and status */
59 PIIX_SCC = 0x0A, /* sub-class code register */
60
61 PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */
62 PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
63 PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
64
65 /* combined mode. if set, PATA is channel 0.
66 * if clear, PATA is channel 1.
67 */
68 PIIX_COMB_PATA_P0 = (1 << 1),
69 PIIX_COMB = (1 << 2), /* combined mode enabled? */
70
71 PIIX_PORT_ENABLED = (1 << 0),
72 PIIX_PORT_PRESENT = (1 << 4),
73
74 PIIX_80C_PRI = (1 << 5) | (1 << 4),
75 PIIX_80C_SEC = (1 << 7) | (1 << 6),
76
77 ich5_pata = 0,
78 ich5_sata = 1,
79 piix4_pata = 2,
80 ich6_sata = 3,
81 ich6_sata_rm = 4,
82 ich7_sata = 5,
83 esb2_sata = 6,
84
85 PIIX_AHCI_DEVICE = 6,
86 };
87
88 static int piix_init_one (struct pci_dev *pdev,
89 const struct pci_device_id *ent);
90
91 static void piix_pata_phy_reset(struct ata_port *ap);
92 static void piix_sata_phy_reset(struct ata_port *ap);
93 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
94 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
95
96 static unsigned int in_module_init = 1;
97
98 static const struct pci_device_id piix_pci_tbl[] = {
99 #ifdef ATA_ENABLE_PATA
100 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
101 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
102 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
103 #endif
104
105 /* NOTE: The following PCI ids must be kept in sync with the
106 * list in drivers/pci/quirks.c.
107 */
108
109 /* 82801EB (ICH5) */
110 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
111 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
112 /* 6300ESB (ICH5 variant with broken PCS present bits) */
113 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
114 /* 6300ESB pretending RAID */
115 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
116 /* 82801FB/FW (ICH6/ICH6W) */
117 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
118 /* 82801FR/FRW (ICH6R/ICH6RW) */
119 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
120 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
121 * Attach iff the controller is in IDE mode. */
122 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
123 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6_sata_rm },
124 /* Enterprise Southbridge 2 (631xESB/632xESB) */
125 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb2_sata },
126 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
127 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
128 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
129 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
130 /* SATA Controller 1 IDE (ICH8) */
131 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
132 /* SATA Controller 2 IDE (ICH8) */
133 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
134 /* Mobile SATA Controller IDE (ICH8M) */
135 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
136 { 0x8086, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
137 /* SATA Controller IDE (ICH9) */
138 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
139 /* SATA Controller IDE (ICH9) */
140 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
141 /* SATA Controller IDE (ICH9) */
142 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
143 /* SATA Controller IDE (ICH9M) */
144 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
145 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
146 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
147 /* SATA Controller IDE (Tolopai) */
148 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
149 /* SATA Controller IDE (ICH10) */
150 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
151 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
152 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
153 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
154 /* SATA Controller IDE (PCH) */
155 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
156 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
157 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
158 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
159
160 { } /* terminate list */
161 };
162
163 static struct pci_driver piix_pci_driver = {
164 .name = DRV_NAME,
165 .id_table = piix_pci_tbl,
166 .probe = piix_init_one,
167 .remove = ata_pci_remove_one,
168 };
169
170 static Scsi_Host_Template piix_sht = {
171 .module = THIS_MODULE,
172 .name = DRV_NAME,
173 .detect = ata_scsi_detect,
174 .release = ata_scsi_release,
175 .ioctl = ata_scsi_ioctl,
176 .queuecommand = ata_scsi_queuecmd,
177 .eh_strategy_handler = ata_scsi_error,
178 .can_queue = ATA_DEF_QUEUE,
179 .this_id = ATA_SHT_THIS_ID,
180 .sg_tablesize = LIBATA_MAX_PRD,
181 .max_sectors = ATA_MAX_SECTORS,
182 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
183 .use_new_eh_code = ATA_SHT_NEW_EH_CODE,
184 .emulated = ATA_SHT_EMULATED,
185 .use_clustering = ATA_SHT_USE_CLUSTERING,
186 .proc_name = DRV_NAME,
187 .bios_param = ata_std_bios_param,
188 };
189
190 static const struct ata_port_operations piix_pata_ops = {
191 .port_disable = ata_port_disable,
192 .set_piomode = piix_set_piomode,
193 .set_dmamode = piix_set_dmamode,
194
195 .tf_load = ata_tf_load,
196 .tf_read = ata_tf_read,
197 .check_status = ata_check_status,
198 .exec_command = ata_exec_command,
199 .dev_select = ata_std_dev_select,
200
201 .phy_reset = piix_pata_phy_reset,
202
203 .bmdma_setup = ata_bmdma_setup,
204 .bmdma_start = ata_bmdma_start,
205 .bmdma_stop = ata_bmdma_stop,
206 .bmdma_status = ata_bmdma_status,
207 .qc_prep = ata_qc_prep,
208 .qc_issue = ata_qc_issue_prot,
209
210 .eng_timeout = ata_eng_timeout,
211
212 .irq_handler = ata_interrupt,
213 .irq_clear = ata_bmdma_irq_clear,
214
215 .port_start = ata_port_start,
216 .port_stop = ata_port_stop,
217 .host_stop = ata_host_stop,
218 };
219
220 static const struct ata_port_operations piix_sata_ops = {
221 .port_disable = ata_port_disable,
222
223 .tf_load = ata_tf_load,
224 .tf_read = ata_tf_read,
225 .check_status = ata_check_status,
226 .exec_command = ata_exec_command,
227 .dev_select = ata_std_dev_select,
228
229 .phy_reset = piix_sata_phy_reset,
230
231 .bmdma_setup = ata_bmdma_setup,
232 .bmdma_start = ata_bmdma_start,
233 .bmdma_stop = ata_bmdma_stop,
234 .bmdma_status = ata_bmdma_status,
235 .qc_prep = ata_qc_prep,
236 .qc_issue = ata_qc_issue_prot,
237
238 .eng_timeout = ata_eng_timeout,
239
240 .irq_handler = ata_interrupt,
241 .irq_clear = ata_bmdma_irq_clear,
242
243 .port_start = ata_port_start,
244 .port_stop = ata_port_stop,
245 .host_stop = ata_host_stop,
246 };
247
248 static struct ata_port_info piix_port_info[] = {
249 /* ich5_pata */
250 {
251 .sht = &piix_sht,
252 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
253 PIIX_FLAG_CHECKINTR,
254 .pio_mask = 0x1f, /* pio0-4 */
255 #if 0
256 .mwdma_mask = 0x06, /* mwdma1-2 */
257 #else
258 .mwdma_mask = 0x00, /* mwdma broken */
259 #endif
260 .udma_mask = 0x3f, /* udma0-5 */
261 .port_ops = &piix_pata_ops,
262 },
263
264 /* ich5_sata */
265 {
266 .sht = &piix_sht,
267 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
268 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
269 .pio_mask = 0x1f, /* pio0-4 */
270 .mwdma_mask = 0x07, /* mwdma0-2 */
271 .udma_mask = 0x7f, /* udma0-6 */
272 .port_ops = &piix_sata_ops,
273 },
274
275 /* piix4_pata */
276 {
277 .sht = &piix_sht,
278 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
279 .pio_mask = 0x1f, /* pio0-4 */
280 #if 0
281 .mwdma_mask = 0x06, /* mwdma1-2 */
282 #else
283 .mwdma_mask = 0x00, /* mwdma broken */
284 #endif
285 .udma_mask = ATA_UDMA_MASK_40C,
286 .port_ops = &piix_pata_ops,
287 },
288
289 /* ich6_sata */
290 {
291 .sht = &piix_sht,
292 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
293 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
294 ATA_FLAG_SLAVE_POSS,
295 .pio_mask = 0x1f, /* pio0-4 */
296 .mwdma_mask = 0x07, /* mwdma0-2 */
297 .udma_mask = 0x7f, /* udma0-6 */
298 .port_ops = &piix_sata_ops,
299 },
300
301 /* ich6_sata_rm */
302 {
303 .sht = &piix_sht,
304 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
305 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
306 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
307 .pio_mask = 0x1f, /* pio0-4 */
308 .mwdma_mask = 0x07, /* mwdma0-2 */
309 .udma_mask = 0x7f, /* udma0-6 */
310 .port_ops = &piix_sata_ops,
311 },
312
313 /* ich7_sata */
314 {
315 .sht = &piix_sht,
316 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
317 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
318 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
319 .pio_mask = 0x1f, /* pio0-4 */
320 .mwdma_mask = 0x07, /* mwdma0-2 */
321 .udma_mask = 0x7f, /* udma0-6 */
322 .port_ops = &piix_sata_ops,
323 },
324
325 /* esb2_sata */
326 {
327 .sht = &piix_sht,
328 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
329 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
330 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
331 .pio_mask = 0x1f, /* pio0-4 */
332 .mwdma_mask = 0x07, /* mwdma0-2 */
333 .udma_mask = 0x7f, /* udma0-6 */
334 .port_ops = &piix_sata_ops,
335 },
336 };
337
338 static struct pci_bits piix_enable_bits[] = {
339 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
340 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
341 };
342
343 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
344 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
345 MODULE_LICENSE("GPL");
346 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
347 MODULE_VERSION(DRV_VERSION);
348
349 /**
350 * piix_pata_cbl_detect - Probe host controller cable detect info
351 * @ap: Port for which cable detect info is desired
352 *
353 * Read 80c cable indicator from ATA PCI device's PCI config
354 * register. This register is normally set by firmware (BIOS).
355 *
356 * LOCKING:
357 * None (inherited from caller).
358 */
piix_pata_cbl_detect(struct ata_port * ap)359 static void piix_pata_cbl_detect(struct ata_port *ap)
360 {
361 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
362 u8 tmp, mask;
363
364 /* no 80c support in host controller? */
365 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
366 goto cbl40;
367
368 /* check BIOS cable detect results */
369 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
370 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
371 if ((tmp & mask) == 0)
372 goto cbl40;
373
374 ap->cbl = ATA_CBL_PATA80;
375 return;
376
377 cbl40:
378 ap->cbl = ATA_CBL_PATA40;
379 ap->udma_mask &= ATA_UDMA_MASK_40C;
380 }
381
382 /**
383 * piix_pata_phy_reset - Probe specified port on PATA host controller
384 * @ap: Port to probe
385 *
386 * Probe PATA phy.
387 *
388 * LOCKING:
389 * None (inherited from caller).
390 */
391
piix_pata_phy_reset(struct ata_port * ap)392 static void piix_pata_phy_reset(struct ata_port *ap)
393 {
394 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
395
396 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
397 ata_port_disable(ap);
398 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
399 return;
400 }
401
402 piix_pata_cbl_detect(ap);
403
404 ata_port_probe(ap);
405
406 ata_bus_reset(ap);
407 }
408
409 /**
410 * piix_sata_probe - Probe PCI device for present SATA devices
411 * @ap: Port associated with the PCI device we wish to probe
412 *
413 * Reads SATA PCI device's PCI config register Port Configuration
414 * and Status (PCS) to determine port and device availability.
415 *
416 * LOCKING:
417 * None (inherited from caller).
418 *
419 * RETURNS:
420 * Non-zero if port is enabled, it may or may not have a device
421 * attached in that case (PRESENT bit would only be set if BIOS probe
422 * was done). Zero is returned if port is disabled.
423 */
piix_sata_probe(struct ata_port * ap)424 static int piix_sata_probe (struct ata_port *ap)
425 {
426 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
427 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
428 int orig_mask, mask, i;
429 u8 pcs;
430
431 mask = (PIIX_PORT_PRESENT << ap->hard_port_no) |
432 (PIIX_PORT_ENABLED << ap->hard_port_no);
433
434 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
435 orig_mask = (int) pcs & 0xff;
436
437 /* TODO: this is vaguely wrong for ICH6 combined mode,
438 * where only two of the four SATA ports are mapped
439 * onto a single ATA channel. It is also vaguely inaccurate
440 * for ICH5, which has only two ports. However, this is ok,
441 * as further device presence detection code will handle
442 * any false positives produced here.
443 */
444
445 for (i = 0; i < 4; i++) {
446 mask = (PIIX_PORT_ENABLED << i);
447
448 if ((orig_mask & mask) == mask)
449 if (combined || (i == ap->hard_port_no))
450 return 1;
451 }
452
453 return 0;
454 }
455
456 /**
457 * piix_sata_phy_reset - Probe specified port on SATA host controller
458 * @ap: Port to probe
459 *
460 * Probe SATA phy.
461 *
462 * LOCKING:
463 * None (inherited from caller).
464 */
465
piix_sata_phy_reset(struct ata_port * ap)466 static void piix_sata_phy_reset(struct ata_port *ap)
467 {
468 if (!piix_sata_probe(ap)) {
469 ata_port_disable(ap);
470 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
471 return;
472 }
473
474 ap->cbl = ATA_CBL_SATA;
475
476 ata_port_probe(ap);
477
478 ata_bus_reset(ap);
479 }
480
481 /**
482 * piix_set_piomode - Initialize host controller PATA PIO timings
483 * @ap: Port whose timings we are configuring
484 * @adev: um
485 *
486 * Set PIO mode for device, in host controller PCI config space.
487 *
488 * LOCKING:
489 * None (inherited from caller).
490 */
491
piix_set_piomode(struct ata_port * ap,struct ata_device * adev)492 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
493 {
494 unsigned int pio = adev->pio_mode - XFER_PIO_0;
495 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
496 unsigned int is_slave = (adev->devno != 0);
497 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
498 unsigned int slave_port = 0x44;
499 u16 master_data;
500 u8 slave_data;
501
502 static const /* ISP RTC */
503 u8 timings[][2] = { { 0, 0 },
504 { 0, 0 },
505 { 1, 0 },
506 { 2, 1 },
507 { 2, 3 }, };
508
509 pci_read_config_word(dev, master_port, &master_data);
510 if (is_slave) {
511 master_data |= 0x4000;
512 /* enable PPE, IE and TIME */
513 master_data |= 0x0070;
514 pci_read_config_byte(dev, slave_port, &slave_data);
515 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
516 slave_data |=
517 (timings[pio][0] << 2) |
518 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
519 } else {
520 master_data &= 0xccf8;
521 /* enable PPE, IE and TIME */
522 master_data |= 0x0007;
523 master_data |=
524 (timings[pio][0] << 12) |
525 (timings[pio][1] << 8);
526 }
527 pci_write_config_word(dev, master_port, master_data);
528 if (is_slave)
529 pci_write_config_byte(dev, slave_port, slave_data);
530 }
531
532 /**
533 * piix_set_dmamode - Initialize host controller PATA PIO timings
534 * @ap: Port whose timings we are configuring
535 * @adev: um
536 * @udma: udma mode, 0 - 6
537 *
538 * Set UDMA mode for device, in host controller PCI config space.
539 *
540 * LOCKING:
541 * None (inherited from caller).
542 */
543
piix_set_dmamode(struct ata_port * ap,struct ata_device * adev)544 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
545 {
546 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
547 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
548 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
549 u8 speed = udma;
550 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
551 int a_speed = 3 << (drive_dn * 4);
552 int u_flag = 1 << drive_dn;
553 int v_flag = 0x01 << drive_dn;
554 int w_flag = 0x10 << drive_dn;
555 int u_speed = 0;
556 int sitre;
557 u16 reg4042, reg4a;
558 u8 reg48, reg54, reg55;
559
560 pci_read_config_word(dev, maslave, ®4042);
561 DPRINTK("reg4042 = 0x%04x\n", reg4042);
562 sitre = (reg4042 & 0x4000) ? 1 : 0;
563 pci_read_config_byte(dev, 0x48, ®48);
564 pci_read_config_word(dev, 0x4a, ®4a);
565 pci_read_config_byte(dev, 0x54, ®54);
566 pci_read_config_byte(dev, 0x55, ®55);
567
568 switch(speed) {
569 case XFER_UDMA_4:
570 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
571 case XFER_UDMA_6:
572 case XFER_UDMA_5:
573 case XFER_UDMA_3:
574 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
575 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
576 case XFER_MW_DMA_2:
577 case XFER_MW_DMA_1: break;
578 default:
579 BUG();
580 return;
581 }
582
583 if (speed >= XFER_UDMA_0) {
584 if (!(reg48 & u_flag))
585 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
586 if (speed == XFER_UDMA_5) {
587 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
588 } else {
589 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
590 }
591 if ((reg4a & a_speed) != u_speed)
592 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
593 if (speed > XFER_UDMA_2) {
594 if (!(reg54 & v_flag))
595 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
596 } else
597 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
598 } else {
599 if (reg48 & u_flag)
600 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
601 if (reg4a & a_speed)
602 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
603 if (reg54 & v_flag)
604 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
605 if (reg55 & w_flag)
606 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
607 }
608 }
609
610 #define AHCI_PCI_BAR 5
611 #define AHCI_GLOBAL_CTL 0x04
612 #define AHCI_ENABLE (1 << 31)
piix_disable_ahci(struct pci_dev * pdev)613 static int piix_disable_ahci(struct pci_dev *pdev)
614 {
615 void __iomem *mmio;
616 u32 tmp;
617 int rc = 0;
618
619 /* BUG: pci_enable_device has not yet been called. This
620 * works because this device is usually set up by BIOS.
621 */
622
623 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
624 !pci_resource_len(pdev, AHCI_PCI_BAR))
625 return 0;
626
627 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
628 if (!mmio)
629 return -ENOMEM;
630
631 tmp = readl(mmio + AHCI_GLOBAL_CTL);
632 if (tmp & AHCI_ENABLE) {
633 tmp &= ~AHCI_ENABLE;
634 writel(tmp, mmio + AHCI_GLOBAL_CTL);
635
636 tmp = readl(mmio + AHCI_GLOBAL_CTL);
637 if (tmp & AHCI_ENABLE)
638 rc = -EIO;
639 }
640
641 pci_iounmap(pdev, mmio);
642 return rc;
643 }
644
645 /**
646 * piix_init_one - Register PIIX ATA PCI device with kernel services
647 * @pdev: PCI device to register
648 * @ent: Entry in piix_pci_tbl matching with @pdev
649 *
650 * Called from kernel PCI layer. We probe for combined mode (sigh),
651 * and then hand over control to libata, for it to do the rest.
652 *
653 * LOCKING:
654 * Inherited from PCI layer (may sleep).
655 *
656 * RETURNS:
657 * Zero on success, or -ERRNO value.
658 */
659
piix_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)660 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
661 {
662 static int printed_version;
663 struct ata_port_info *port_info[2];
664 unsigned int combined = 0;
665 unsigned int pata_chan = 0, sata_chan = 0;
666
667 if (!printed_version++)
668 pdev_printk(KERN_DEBUG, pdev,
669 "version " DRV_VERSION "\n");
670
671 /* no hotplugging support (FIXME) */
672 if (!in_module_init)
673 return -ENODEV;
674
675 port_info[0] = &piix_port_info[ent->driver_data];
676 port_info[1] = &piix_port_info[ent->driver_data];
677
678 if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
679 u8 tmp;
680 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
681 if (tmp == PIIX_AHCI_DEVICE) {
682 int rc = piix_disable_ahci(pdev);
683 if (rc)
684 return rc;
685 }
686 }
687
688 if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
689 u8 tmp;
690 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
691
692 if (tmp & PIIX_COMB) {
693 combined = 1;
694 if (tmp & PIIX_COMB_PATA_P0)
695 sata_chan = 1;
696 else
697 pata_chan = 1;
698 }
699 }
700
701 /* On ICH5, some BIOSen disable the interrupt using the
702 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
703 * On ICH6, this bit has the same effect, but only when
704 * MSI is disabled (and it is disabled, as we don't use
705 * message-signalled interrupts currently).
706 */
707 if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
708 pci_intx(pdev, 1);
709
710 if (combined) {
711 port_info[sata_chan] = &piix_port_info[ent->driver_data];
712 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
713 port_info[pata_chan] = &piix_port_info[ich5_pata];
714
715 pdev_printk(KERN_WARNING, pdev,
716 "combined mode detected (p=%u, s=%u)\n",
717 pata_chan, sata_chan);
718 }
719
720 return ata_pci_init_one(pdev, port_info, 2);
721 }
722
piix_init(void)723 static int __init piix_init(void)
724 {
725 int rc;
726
727 DPRINTK("pci_module_init\n");
728 rc = pci_module_init(&piix_pci_driver);
729 if (rc)
730 return rc;
731
732 in_module_init = 0;
733
734 DPRINTK("scsi_register_host\n");
735 rc = scsi_register_module(MODULE_SCSI_HA, &piix_sht);
736 if (rc) {
737 rc = -ENODEV;
738 goto err_out;
739 }
740
741 DPRINTK("done\n");
742 return 0;
743
744 err_out:
745 pci_unregister_driver(&piix_pci_driver);
746 return rc;
747 }
748
piix_exit(void)749 static void __exit piix_exit(void)
750 {
751 scsi_unregister_module(MODULE_SCSI_HA, &piix_sht);
752 pci_unregister_driver(&piix_pci_driver);
753 }
754
755 module_init(piix_init);
756 module_exit(piix_exit);
757
758