1 /* $Id: dbri.h,v 1.13 2000/10/13 00:34:24 uzi Exp $ 2 * drivers/sbus/audio/cs4231.h 3 * 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de) 5 */ 6 7 #ifndef _DBRI_H_ 8 #define _DBRI_H_ 9 10 #include <linux/types.h> 11 12 /* DBRI main registers */ 13 #define REG0 0x00UL /* Status and Control */ 14 #define REG1 0x04UL /* Mode and Interrupt */ 15 #define REG2 0x08UL /* Parallel IO */ 16 #define REG3 0x0cUL /* Test */ 17 #define REG8 0x20UL /* Command Queue Pointer */ 18 #define REG9 0x24UL /* Interrupt Queue Pointer */ 19 20 #define DBRI_NO_CMDS 64 21 #define DBRI_NO_INTS 1 /* Note: the value of this define was 22 * originally 2. The ringbuffer to store 23 * interrupts in dma is currently broken. 24 * This is a temporary fix until the ringbuffer 25 * is fixed. 26 */ 27 #define DBRI_INT_BLK 64 28 #define DBRI_NO_DESCS 64 29 30 #define DBRI_MM_ONB 1 31 #define DBRI_MM_SB 2 32 33 struct dbri_mem { 34 volatile __u32 word1; 35 volatile __u32 ba; /* Transmit/Receive Buffer Address */ 36 volatile __u32 nda; /* Next Descriptor Address */ 37 volatile __u32 word4; 38 }; 39 40 #include "cs4215.h" 41 42 /* This structure is in a DMA region where it can accessed by both 43 * the CPU and the DBRI 44 */ 45 struct dbri_dma { 46 volatile s32 cmd[DBRI_NO_CMDS]; /* Place for commands */ 47 volatile s32 intr[DBRI_NO_INTS * DBRI_INT_BLK]; /* Interrupt field */ 48 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */ 49 }; 50 51 #define dbri_dma_off(member, elem) \ 52 ((u32)(unsigned long) \ 53 (&(((struct dbri_dma *)0)->member[elem]))) 54 55 enum in_or_out { PIPEinput, PIPEoutput }; 56 57 enum direction { in, out }; 58 59 struct dbri_pipe { 60 u32 sdp; /* SDP command word */ 61 enum direction direction; 62 int nextpipe; /* Next pipe in linked list */ 63 int prevpipe; 64 int cycle; /* Offset of timeslot (bits) */ 65 int length; /* Length of timeslot (bits) */ 66 int desc; /* Index of active descriptor*/ 67 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */ 68 }; 69 70 struct dbri_desc { 71 int inuse; /* Boolean flag */ 72 int next; /* Index of next desc, or -1 */ 73 void *buffer; /* CPU view of buffer */ 74 u32 buffer_dvma; /* Device view */ 75 unsigned int len; 76 void (*output_callback)(void *, int); 77 void *output_callback_arg; 78 void (*input_callback)(void *, int, unsigned int); 79 void *input_callback_arg; 80 }; 81 82 /* This structure holds the information for both chips (DBRI & CS4215) */ 83 84 struct dbri { 85 int regs_size, irq; /* Needed for unload */ 86 struct sbus_dev *sdev; /* SBUS device info */ 87 88 volatile struct dbri_dma *dma; /* Pointer to our DMA block */ 89 u32 dma_dvma; /* DBRI visible DMA address */ 90 91 unsigned long regs; /* dbri HW regs */ 92 int dbri_version; /* 'e' and up is OK */ 93 int dbri_irqp; /* intr queue pointer */ 94 int wait_seen; 95 96 struct dbri_pipe pipes[32]; /* DBRI's 32 data pipes */ 97 struct dbri_desc descs[DBRI_NO_DESCS]; 98 99 int chi_in_pipe; 100 int chi_out_pipe; 101 int chi_bpf; 102 103 struct cs4215 mm; /* mmcodec special info */ 104 105 #if 0 106 /* Where to sleep if busy */ 107 wait_queue_head_t wait, int_wait; 108 #endif 109 struct audio_info perchip_info; 110 111 /* Track ISDN LIU and notify changes */ 112 int liu_state; 113 void (*liu_callback)(void *); 114 void *liu_callback_arg; 115 }; 116 117 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */ 118 #define D_P (1<<15) /* Program command & queue pointer valid */ 119 #define D_G (1<<14) /* Allow 4-Word SBus Burst */ 120 #define D_S (1<<13) /* Allow 16-Word SBus Burst */ 121 #define D_E (1<<12) /* Allow 8-Word SBus Burst */ 122 #define D_X (1<<7) /* Sanity Timer Disable */ 123 #define D_T (1<<6) /* Permit activation of the TE interface */ 124 #define D_N (1<<5) /* Permit activation of the NT interface */ 125 #define D_C (1<<4) /* Permit activation of the CHI interface */ 126 #define D_F (1<<3) /* Force Sanity Timer Time-Out */ 127 #define D_D (1<<2) /* Disable Master Mode */ 128 #define D_H (1<<1) /* Halt for Analysis */ 129 #define D_R (1<<0) /* Soft Reset */ 130 131 132 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */ 133 #define D_LITTLE_END (1<<8) /* Byte Order */ 134 #define D_BIG_END (0<<8) /* Byte Order */ 135 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (readonly) */ 136 #define D_MLE (1<<3) /* Multiple Late Error on SBus (readonly) */ 137 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (readonly) */ 138 #define D_MBE (1<<1) /* Burst Error on SBus (readonly) */ 139 #define D_IR (1<<0) /* Interrupt Indicator (readonly) */ 140 141 142 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */ 143 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */ 144 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */ 145 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */ 146 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */ 147 #define D_ENPIO (0xf0) /* Enable all the pins */ 148 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */ 149 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */ 150 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */ 151 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */ 152 153 154 /* DBRI Commands (Page 20) */ 155 #define D_WAIT 0x0 /* Stop execution */ 156 #define D_PAUSE 0x1 /* Flush long pipes */ 157 #define D_JUMP 0x2 /* New command queue */ 158 #define D_IIQ 0x3 /* Initialize Interrupt Queue */ 159 #define D_REX 0x4 /* Report command execution via interrupt */ 160 #define D_SDP 0x5 /* Setup Data Pipe */ 161 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */ 162 #define D_DTS 0x7 /* Define Time Slot */ 163 #define D_SSP 0x8 /* Set short Data Pipe */ 164 #define D_CHI 0x9 /* Set CHI Global Mode */ 165 #define D_NT 0xa /* NT Command */ 166 #define D_TE 0xb /* TE Command */ 167 #define D_CDEC 0xc /* Codec setup */ 168 #define D_TEST 0xd /* No comment */ 169 #define D_CDM 0xe /* CHI Data mode command */ 170 171 172 173 /* Special bits for some commands */ 174 #define D_PIPE(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */ 175 176 /* Setup Data Pipe */ 177 /* IRM */ 178 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value rcvd*/ 179 #define D_SDP_CHANGE (2<<18) /* Report any changes */ 180 #define D_SDP_EVERY (3<<18) /* Report any changes */ 181 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */ 182 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */ 183 184 /* Pipe data MODE */ 185 #define D_SDP_MEM (0<<13) /* To/from memory */ 186 #define D_SDP_HDLC (2<<13) 187 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control)*/ 188 #define D_SDP_SER (4<<13) /* Serial to serial */ 189 #define D_SDP_FIXED (6<<13) /* Short only */ 190 #define D_SDP_MODE(v) ((v)&(7<<13)) 191 192 #define D_SDP_TO_SER (1<<12) /* Direction */ 193 #define D_SDP_FROM_SER (0<<12) /* Direction */ 194 #define D_SDP_MSB (1<<11) /* Bit order within Byte */ 195 #define D_SDP_LSB (0<<11) /* Bit order within Byte */ 196 #define D_SDP_P (1<<10) /* Pointer Valid */ 197 #define D_SDP_A (1<<8) /* Abort */ 198 #define D_SDP_C (1<<7) /* Clear */ 199 200 /* Define Time Slot */ 201 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */ 202 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */ 203 #define D_DTS_INS (1<<15) /* Insert Time Slot */ 204 #define D_DTS_DEL (0<<15) /* Delete Time Slot */ 205 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */ 206 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */ 207 208 /* Time Slot defines */ 209 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */ 210 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */ 211 #define D_TS_DI (1<<13) /* Data Invert */ 212 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */ 213 #define D_TS_MONITOR (2<<10) /* Monitor pipe */ 214 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */ 215 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */ 216 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */ 217 #define D_TS_NEXT(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */ 218 219 /* Concentration Highway Interface Modes */ 220 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */ 221 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */ 222 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */ 223 #define D_CHI_OD (1<<13) /* Open Drain Enable */ 224 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */ 225 #define D_CHI_FD (1<<11) /* Frame Drive */ 226 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */ 227 228 /* NT: These are here for completeness */ 229 #define D_NT_FBIT (1<<17) /* Frame Bit */ 230 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */ 231 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */ 232 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */ 233 #define D_NT_ISNT (1<<13) /* Configfure interface as NT */ 234 #define D_NT_FT (1<<12) /* Fixed Timing */ 235 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */ 236 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */ 237 #define D_NT_ACT (1<<9) /* Activate Interface */ 238 #define D_NT_MFE (1<<8) /* Multiframe Enable */ 239 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */ 240 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */ 241 #define D_NT_FACT (1<<1) /* Force Activation */ 242 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */ 243 244 /* Codec Setup */ 245 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */ 246 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */ 247 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */ 248 249 /* Test */ 250 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */ 251 #define D_TEST_SIZE(v) ((v)<<11) /* */ 252 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */ 253 #define D_TEST_PROC 0x6 /* MicroProcessor test */ 254 #define D_TEST_SER 0x7 /* Serial-Controller test */ 255 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */ 256 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */ 257 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */ 258 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */ 259 #define D_TEST_DUMP 0xe /* ROM Dump */ 260 261 /* CHI Data Mode */ 262 #define D_CDM_THI (1<<8) /* Transmit Data on CHIDR Pin */ 263 #define D_CDM_RHI (1<<7) /* Receive Data on CHIDX Pin */ 264 #define D_CDM_RCE (1<<6) /* Receive on Rising Edge of CHICK */ 265 #define D_CDM_XCE (1<<2) /* Transmit Data on Rising Edge of CHICK */ 266 #define D_CDM_XEN (1<<1) /* Transmit Highway Enable */ 267 #define D_CDM_REN (1<<0) /* Receive Highway Enable */ 268 269 /* The Interrupts */ 270 #define D_INTR_BRDY 1 /* Buffer Ready for processing */ 271 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */ 272 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */ 273 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */ 274 #define D_INTR_EOL 5 /* End of List */ 275 #define D_INTR_CMDI 6 /* Command has bean read */ 276 #define D_INTR_XCMP 8 /* Transmission of frame complete */ 277 #define D_INTR_SBRI 9 /* BRI status change info */ 278 #define D_INTR_FXDT 10 /* Fixed data change */ 279 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */ 280 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */ 281 #define D_INTR_DBYT 12 /* Dropped by frame slip */ 282 #define D_INTR_RBYT 13 /* Repeated by frame slip */ 283 #define D_INTR_LINT 14 /* Lost Interrupt */ 284 #define D_INTR_UNDR 15 /* DMA underrun */ 285 286 #define D_INTR_TE 32 287 #define D_INTR_NT 34 288 #define D_INTR_CHI 36 289 #define D_INTR_CMD 38 290 291 #define D_INTR_GETCHAN(v) (((v)>>24) & 0x3f) 292 #define D_INTR_GETCODE(v) (((v)>>20) & 0xf) 293 #define D_INTR_GETCMD(v) (((v)>>16) & 0xf) 294 #define D_INTR_GETVAL(v) ((v) & 0xffff) 295 #define D_INTR_GETRVAL(v) ((v) & 0xfffff) 296 297 #define D_P_0 0 /* TE receive anchor */ 298 #define D_P_1 1 /* TE transmit anchor */ 299 #define D_P_2 2 /* NT transmit anchor */ 300 #define D_P_3 3 /* NT receive anchor */ 301 #define D_P_4 4 /* CHI send data */ 302 #define D_P_5 5 /* CHI receive data */ 303 #define D_P_6 6 /* */ 304 #define D_P_7 7 /* */ 305 #define D_P_8 8 /* */ 306 #define D_P_9 9 /* */ 307 #define D_P_10 10 /* */ 308 #define D_P_11 11 /* */ 309 #define D_P_12 12 /* */ 310 #define D_P_13 13 /* */ 311 #define D_P_14 14 /* */ 312 #define D_P_15 15 /* */ 313 #define D_P_16 16 /* CHI anchor pipe */ 314 #define D_P_17 17 /* CHI send */ 315 #define D_P_18 18 /* CHI receive */ 316 #define D_P_19 19 /* CHI receive */ 317 #define D_P_20 20 /* CHI receive */ 318 #define D_P_21 21 /* */ 319 #define D_P_22 22 /* */ 320 #define D_P_23 23 /* */ 321 #define D_P_24 24 /* */ 322 #define D_P_25 25 /* */ 323 #define D_P_26 26 /* */ 324 #define D_P_27 27 /* */ 325 #define D_P_28 28 /* */ 326 #define D_P_29 29 /* */ 327 #define D_P_30 30 /* */ 328 #define D_P_31 31 /* */ 329 330 331 /* Transmit descriptor defines */ 332 #define DBRI_TD_F (1<<31) /* End of Frame */ 333 #define DBRI_TD_D (1<<30) /* Do not append CRC */ 334 #define DBRI_TD_CNT(v) ((v)<<16) /* Number of valid bytes in the buffer */ 335 #define DBRI_TD_B (1<<15) /* Final interrupt */ 336 #define DBRI_TD_M (1<<14) /* Marker interrupt */ 337 #define DBRI_TD_I (1<<13) /* Transmit Idle Characters */ 338 #define DBRI_TD_FCNT(v) (v) /* Flag Count */ 339 #define DBRI_TD_UNR (1<<3) /* Underrun: transmitter is out of data */ 340 #define DBRI_TD_ABT (1<<2) /* Abort: frame aborted */ 341 #define DBRI_TD_TBC (1<<0) /* Transmit buffer Complete */ 342 #define DBRI_TD_STATUS(v) ((v)&0xff) /* Transmit status */ 343 344 /* Receive descriptor defines */ 345 #define DBRI_RD_F (1<<31) /* End of Frame */ 346 #define DBRI_RD_C (1<<30) /* Completed buffer */ 347 #define DBRI_RD_B (1<<15) /* Final interrupt */ 348 #define DBRI_RD_M (1<<14) /* Marker interrupt */ 349 #define DBRI_RD_BCNT(v) (v) /* Buffer size */ 350 #define DBRI_RD_CRC (1<<7) /* 0: CRC is correct */ 351 #define DBRI_RD_BBC (1<<6) /* 1: Bad Byte received */ 352 #define DBRI_RD_ABT (1<<5) /* Abort: frame aborted */ 353 #define DBRI_RD_OVRN (1<<3) /* Overrun: data lost */ 354 #define DBRI_RD_STATUS(v) ((v)&0xff) /* Receive status */ 355 #define DBRI_RD_CNT(v) (((v)>>16)&0x1fff) /* Number of valid bytes in the buffer */ 356 357 #endif /* _DBRI_H_ */ 358