1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.30h"
26 #define DRV_RELDATE "06.24.2004"
27 #define PFX DRV_NAME ": "
28
29 static const char *version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
31
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49
50 #include <asm/bitops.h>
51 #include <asm/dma.h>
52 #include <asm/io.h>
53 #include <asm/uaccess.h>
54 #include <asm/irq.h>
55
56 /*
57 * PCI device identifiers for "new style" Linux PCI Device Drivers
58 */
59 static struct pci_device_id pcnet32_pci_tbl[] __devinitdata = {
60 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
61 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
62 /*
63 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
64 * the incorrect vendor id.
65 */
66 { PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID,
67 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, 0 },
68 { 0, }
69 };
70
71 MODULE_DEVICE_TABLE (pci, pcnet32_pci_tbl);
72
73 static int cards_found __devinitdata;
74
75 /*
76 * VLB I/O addresses
77 */
78 static unsigned int pcnet32_portlist[] __initdata =
79 { 0x300, 0x320, 0x340, 0x360, 0 };
80
81
82
83 static int pcnet32_debug = 0;
84 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
85 static int pcnet32vlb; /* check for VLB cards ? */
86
87 static struct net_device *pcnet32_dev;
88
89 static int max_interrupt_work = 2;
90 static int rx_copybreak = 200;
91
92 #define PCNET32_PORT_AUI 0x00
93 #define PCNET32_PORT_10BT 0x01
94 #define PCNET32_PORT_GPSI 0x02
95 #define PCNET32_PORT_MII 0x03
96
97 #define PCNET32_PORT_PORTSEL 0x03
98 #define PCNET32_PORT_ASEL 0x04
99 #define PCNET32_PORT_100 0x40
100 #define PCNET32_PORT_FD 0x80
101
102 #define PCNET32_DMA_MASK 0xffffffff
103
104 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
105 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
106
107 /*
108 * table to translate option values from tulip
109 * to internal options
110 */
111 static unsigned char options_mapping[] = {
112 PCNET32_PORT_ASEL, /* 0 Auto-select */
113 PCNET32_PORT_AUI, /* 1 BNC/AUI */
114 PCNET32_PORT_AUI, /* 2 AUI/BNC */
115 PCNET32_PORT_ASEL, /* 3 not supported */
116 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
117 PCNET32_PORT_ASEL, /* 5 not supported */
118 PCNET32_PORT_ASEL, /* 6 not supported */
119 PCNET32_PORT_ASEL, /* 7 not supported */
120 PCNET32_PORT_ASEL, /* 8 not supported */
121 PCNET32_PORT_MII, /* 9 MII 10baseT */
122 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
123 PCNET32_PORT_MII, /* 11 MII (autosel) */
124 PCNET32_PORT_10BT, /* 12 10BaseT */
125 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
126 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
127 PCNET32_PORT_ASEL /* 15 not supported */
128 };
129
130 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
131 "Loopback test (offline)"
132 };
133 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
134
135 #define PCNET32_NUM_REGS 168
136
137 #define MAX_UNITS 8 /* More are supported, limit only on options */
138 static int options[MAX_UNITS];
139 static int full_duplex[MAX_UNITS];
140 static int homepna[MAX_UNITS];
141
142 /*
143 * Theory of Operation
144 *
145 * This driver uses the same software structure as the normal lance
146 * driver. So look for a verbose description in lance.c. The differences
147 * to the normal lance driver is the use of the 32bit mode of PCnet32
148 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
149 * 16MB limitation and we don't need bounce buffers.
150 */
151
152 /*
153 * History:
154 * v0.01: Initial version
155 * only tested on Alpha Noname Board
156 * v0.02: changed IRQ handling for new interrupt scheme (dev_id)
157 * tested on a ASUS SP3G
158 * v0.10: fixed an odd problem with the 79C974 in a Compaq Deskpro XL
159 * looks like the 974 doesn't like stopping and restarting in a
160 * short period of time; now we do a reinit of the lance; the
161 * bug was triggered by doing ifconfig eth0 <ip> broadcast <addr>
162 * and hangs the machine (thanks to Klaus Liedl for debugging)
163 * v0.12: by suggestion from Donald Becker: Renamed driver to pcnet32,
164 * made it standalone (no need for lance.c)
165 * v0.13: added additional PCI detecting for special PCI devices (Compaq)
166 * v0.14: stripped down additional PCI probe (thanks to David C Niemi
167 * and sveneric@xs4all.nl for testing this on their Compaq boxes)
168 * v0.15: added 79C965 (VLB) probe
169 * added interrupt sharing for PCI chips
170 * v0.16: fixed set_multicast_list on Alpha machines
171 * v0.17: removed hack from dev.c; now pcnet32 uses ethif_probe in Space.c
172 * v0.19: changed setting of autoselect bit
173 * v0.20: removed additional Compaq PCI probe; there is now a working one
174 * in arch/i386/bios32.c
175 * v0.21: added endian conversion for ppc, from work by cort@cs.nmt.edu
176 * v0.22: added printing of status to ring dump
177 * v0.23: changed enet_statistics to net_devive_stats
178 * v0.90: added multicast filter
179 * added module support
180 * changed irq probe to new style
181 * added PCnetFast chip id
182 * added fix for receive stalls with Intel saturn chipsets
183 * added in-place rx skbs like in the tulip driver
184 * minor cleanups
185 * v0.91: added PCnetFast+ chip id
186 * back port to 2.0.x
187 * v1.00: added some stuff from Donald Becker's 2.0.34 version
188 * added support for byte counters in net_dev_stats
189 * v1.01: do ring dumps, only when debugging the driver
190 * increased the transmit timeout
191 * v1.02: fixed memory leak in pcnet32_init_ring()
192 * v1.10: workaround for stopped transmitter
193 * added port selection for modules
194 * detect special T1/E1 WAN card and setup port selection
195 * v1.11: fixed wrong checking of Tx errors
196 * v1.20: added check of return value kmalloc (cpeterso@cs.washington.edu)
197 * added save original kmalloc addr for freeing (mcr@solidum.com)
198 * added support for PCnetHome chip (joe@MIT.EDU)
199 * rewritten PCI card detection
200 * added dwio mode to get driver working on some PPC machines
201 * v1.21: added mii selection and mii ioctl
202 * v1.22: changed pci scanning code to make PPC people happy
203 * fixed switching to 32bit mode in pcnet32_open() (thanks
204 * to Michael Richard <mcr@solidum.com> for noticing this one)
205 * added sub vendor/device id matching (thanks again to
206 * Michael Richard <mcr@solidum.com>)
207 * added chip id for 79c973/975 (thanks to Zach Brown <zab@zabbo.net>)
208 * v1.23 fixed small bug, when manual selecting MII speed/duplex
209 * v1.24 Applied Thomas' patch to use TxStartPoint and thus decrease TxFIFO
210 * underflows. Added tx_start_pt module parameter. Increased
211 * TX_RING_SIZE from 16 to 32. Added #ifdef'd code to use DXSUFLO
212 * for FAST[+] chipsets. <kaf@fc.hp.com>
213 * v1.24ac Added SMP spinlocking - Alan Cox <alan@redhat.com>
214 * v1.25kf Added No Interrupt on successful Tx for some Tx's <kaf@fc.hp.com>
215 * v1.26 Converted to pci_alloc_consistent, Jamey Hicks / George France
216 * <jamey@crl.dec.com>
217 * - Fixed a few bugs, related to running the controller in 32bit mode.
218 * 23 Oct, 2000. Carsten Langgaard, carstenl@mips.com
219 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
220 * v1.26p Fix oops on rmmod+insmod; plug i/o resource leak - Paul Gortmaker
221 * v1.27 improved CSR/PROM address detection, lots of cleanups,
222 * new pcnet32vlb module option, HP-PARISC support,
223 * added module parameter descriptions,
224 * initial ethtool support - Helge Deller <deller@gmx.de>
225 * v1.27a Sun Feb 10 2002 Go Taniguchi <go@turbolinux.co.jp>
226 * use alloc_etherdev and register_netdev
227 * fix pci probe not increment cards_found
228 * FD auto negotiate error workaround for xSeries250
229 * clean up and using new mii module
230 * v1.27b Sep 30 2002 Kent Yoder <yoder1@us.ibm.com>
231 * Added timer for cable connection state changes.
232 * v1.28 20 Feb 2004 Don Fry <brazilnut@us.ibm.com>
233 * Jon Mason <jonmason@us.ibm.com>, Chinmay Albal <albal@in.ibm.com>
234 * Now uses ethtool_ops, netif_msg_* and generic_mii_ioctl.
235 * Fixes bogus 'Bus master arbitration failure', pci_[un]map_single
236 * length errors, and transmit hangs. Cleans up after errors in open.
237 * Jim Lewis <jklewis@us.ibm.com> added ethernet loopback test.
238 * Thomas Munck Steenholdt <tmus@tmus.dk> non-mii ioctl corrections.
239 * v1.29 6 Apr 2004 Jim Lewis <jklewis@us.ibm.com> added physical
240 * identification code (blink led's) and register dump.
241 * Don Fry added timer for 971/972 so skbufs don't remain on tx ring
242 * forever.
243 * v1.30 18 May 2004 Don Fry removed timer and Last Transmit Interrupt
244 * (ltint) as they added complexity and didn't give good throughput.
245 * v1.30a 22 May 2004 Don Fry limit frames received during interrupt.
246 * v1.30b 24 May 2004 Don Fry fix bogus tx carrier errors with 79c973,
247 * assisted by Bruce Penrod <bmpenrod@endruntechnologies.com>.
248 * v1.30c 25 May 2004 Don Fry added netif_wake_queue after pcnet32_restart.
249 * v1.30d 01 Jun 2004 Don Fry discard oversize rx packets.
250 * v1.30e 11 Jun 2004 Don Fry recover after fifo error and rx hang.
251 * v1.30f 16 Jun 2004 Don Fry cleanup IRQ to allow 0 and 1 for PCI,
252 * expanding on suggestions from Ralf Baechle <ralf@linux-mips.org>,
253 * and Brian Murphy <brian@murphy.dk>.
254 * v1.30g 22 Jun 2004 Patrick Simmons <psimmons@flash.net> added option
255 * homepna for selecting HomePNA mode for PCNet/Home 79C978.
256 * v1.30h 24 Jun 2004 Don Fry correctly select auto, speed, duplex in bcr32.
257 */
258
259
260 /*
261 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
262 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
263 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
264 */
265 #ifndef PCNET32_LOG_TX_BUFFERS
266 #define PCNET32_LOG_TX_BUFFERS 4
267 #define PCNET32_LOG_RX_BUFFERS 5
268 #endif
269
270 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
271 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
272 #define TX_RING_LEN_BITS ((PCNET32_LOG_TX_BUFFERS) << 12)
273
274 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
275 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
276 #define RX_RING_LEN_BITS ((PCNET32_LOG_RX_BUFFERS) << 4)
277
278 #define PKT_BUF_SZ 1544
279
280 /* Offsets from base I/O address. */
281 #define PCNET32_WIO_RDP 0x10
282 #define PCNET32_WIO_RAP 0x12
283 #define PCNET32_WIO_RESET 0x14
284 #define PCNET32_WIO_BDP 0x16
285
286 #define PCNET32_DWIO_RDP 0x10
287 #define PCNET32_DWIO_RAP 0x14
288 #define PCNET32_DWIO_RESET 0x18
289 #define PCNET32_DWIO_BDP 0x1C
290
291 #define PCNET32_TOTAL_SIZE 0x20
292
293 /* The PCNET32 Rx and Tx ring descriptors. */
294 struct pcnet32_rx_head {
295 u32 base;
296 s16 buf_length;
297 s16 status;
298 u32 msg_length;
299 u32 reserved;
300 };
301
302 struct pcnet32_tx_head {
303 u32 base;
304 s16 length;
305 s16 status;
306 u32 misc;
307 u32 reserved;
308 };
309
310 /* The PCNET32 32-Bit initialization block, described in databook. */
311 struct pcnet32_init_block {
312 u16 mode;
313 u16 tlen_rlen;
314 u8 phys_addr[6];
315 u16 reserved;
316 u32 filter[2];
317 /* Receive and transmit ring base, along with extra bits. */
318 u32 rx_ring;
319 u32 tx_ring;
320 };
321
322 /* PCnet32 access functions */
323 struct pcnet32_access {
324 u16 (*read_csr)(unsigned long, int);
325 void (*write_csr)(unsigned long, int, u16);
326 u16 (*read_bcr)(unsigned long, int);
327 void (*write_bcr)(unsigned long, int, u16);
328 u16 (*read_rap)(unsigned long);
329 void (*write_rap)(unsigned long, u16);
330 void (*reset)(unsigned long);
331 };
332
333 /*
334 * The first three fields of pcnet32_private are read by the ethernet device
335 * so we allocate the structure should be allocated by pci_alloc_consistent().
336 */
337 struct pcnet32_private {
338 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
339 struct pcnet32_rx_head rx_ring[RX_RING_SIZE];
340 struct pcnet32_tx_head tx_ring[TX_RING_SIZE];
341 struct pcnet32_init_block init_block;
342 dma_addr_t dma_addr; /* DMA address of beginning of this
343 object, returned by
344 pci_alloc_consistent */
345 struct pci_dev *pci_dev; /* Pointer to the associated pci device
346 structure */
347 const char *name;
348 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
349 struct sk_buff *tx_skbuff[TX_RING_SIZE];
350 struct sk_buff *rx_skbuff[RX_RING_SIZE];
351 dma_addr_t tx_dma_addr[TX_RING_SIZE];
352 dma_addr_t rx_dma_addr[RX_RING_SIZE];
353 struct pcnet32_access a;
354 spinlock_t lock; /* Guard lock */
355 unsigned int cur_rx, cur_tx; /* The next free ring entry */
356 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
357 struct net_device_stats stats;
358 char tx_full;
359 int options;
360 int shared_irq:1, /* shared irq possible */
361 dxsuflo:1, /* disable transmit stop on uflo */
362 mii:1; /* mii port available */
363 struct net_device *next;
364 struct mii_if_info mii_if;
365 struct timer_list watchdog_timer;
366 struct timer_list blink_timer;
367 u32 msg_enable; /* debug message level */
368 };
369
370 static void pcnet32_probe_vlbus(void);
371 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
372 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
373 static int pcnet32_open(struct net_device *);
374 static int pcnet32_init_ring(struct net_device *);
375 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
376 static int pcnet32_rx(struct net_device *);
377 static void pcnet32_tx_timeout (struct net_device *dev);
378 static void pcnet32_interrupt(int, void *, struct pt_regs *);
379 static int pcnet32_close(struct net_device *);
380 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
381 static void pcnet32_load_multicast(struct net_device *dev);
382 static void pcnet32_set_multicast_list(struct net_device *);
383 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
384 static void pcnet32_watchdog(struct net_device *);
385 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
386 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val);
387 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
388 static void pcnet32_ethtool_test(struct net_device *dev,
389 struct ethtool_test *eth_test, u64 *data);
390 static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1);
391 static int pcnet32_phys_id(struct net_device *dev, u32 data);
392 static void pcnet32_led_blink_callback(struct net_device *dev);
393 static int pcnet32_get_regs_len(struct net_device *dev);
394 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
395 void *ptr);
396
397 enum pci_flags_bit {
398 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
399 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
400 };
401
402
pcnet32_wio_read_csr(unsigned long addr,int index)403 static u16 pcnet32_wio_read_csr (unsigned long addr, int index)
404 {
405 outw (index, addr+PCNET32_WIO_RAP);
406 return inw (addr+PCNET32_WIO_RDP);
407 }
408
pcnet32_wio_write_csr(unsigned long addr,int index,u16 val)409 static void pcnet32_wio_write_csr (unsigned long addr, int index, u16 val)
410 {
411 outw (index, addr+PCNET32_WIO_RAP);
412 outw (val, addr+PCNET32_WIO_RDP);
413 }
414
pcnet32_wio_read_bcr(unsigned long addr,int index)415 static u16 pcnet32_wio_read_bcr (unsigned long addr, int index)
416 {
417 outw (index, addr+PCNET32_WIO_RAP);
418 return inw (addr+PCNET32_WIO_BDP);
419 }
420
pcnet32_wio_write_bcr(unsigned long addr,int index,u16 val)421 static void pcnet32_wio_write_bcr (unsigned long addr, int index, u16 val)
422 {
423 outw (index, addr+PCNET32_WIO_RAP);
424 outw (val, addr+PCNET32_WIO_BDP);
425 }
426
pcnet32_wio_read_rap(unsigned long addr)427 static u16 pcnet32_wio_read_rap (unsigned long addr)
428 {
429 return inw (addr+PCNET32_WIO_RAP);
430 }
431
pcnet32_wio_write_rap(unsigned long addr,u16 val)432 static void pcnet32_wio_write_rap (unsigned long addr, u16 val)
433 {
434 outw (val, addr+PCNET32_WIO_RAP);
435 }
436
pcnet32_wio_reset(unsigned long addr)437 static void pcnet32_wio_reset (unsigned long addr)
438 {
439 inw (addr+PCNET32_WIO_RESET);
440 }
441
pcnet32_wio_check(unsigned long addr)442 static int pcnet32_wio_check (unsigned long addr)
443 {
444 outw (88, addr+PCNET32_WIO_RAP);
445 return (inw (addr+PCNET32_WIO_RAP) == 88);
446 }
447
448 static struct pcnet32_access pcnet32_wio = {
449 .read_csr = pcnet32_wio_read_csr,
450 .write_csr = pcnet32_wio_write_csr,
451 .read_bcr = pcnet32_wio_read_bcr,
452 .write_bcr = pcnet32_wio_write_bcr,
453 .read_rap = pcnet32_wio_read_rap,
454 .write_rap = pcnet32_wio_write_rap,
455 .reset = pcnet32_wio_reset
456 };
457
pcnet32_dwio_read_csr(unsigned long addr,int index)458 static u16 pcnet32_dwio_read_csr (unsigned long addr, int index)
459 {
460 outl (index, addr+PCNET32_DWIO_RAP);
461 return (inl (addr+PCNET32_DWIO_RDP) & 0xffff);
462 }
463
pcnet32_dwio_write_csr(unsigned long addr,int index,u16 val)464 static void pcnet32_dwio_write_csr (unsigned long addr, int index, u16 val)
465 {
466 outl (index, addr+PCNET32_DWIO_RAP);
467 outl (val, addr+PCNET32_DWIO_RDP);
468 }
469
pcnet32_dwio_read_bcr(unsigned long addr,int index)470 static u16 pcnet32_dwio_read_bcr (unsigned long addr, int index)
471 {
472 outl (index, addr+PCNET32_DWIO_RAP);
473 return (inl (addr+PCNET32_DWIO_BDP) & 0xffff);
474 }
475
pcnet32_dwio_write_bcr(unsigned long addr,int index,u16 val)476 static void pcnet32_dwio_write_bcr (unsigned long addr, int index, u16 val)
477 {
478 outl (index, addr+PCNET32_DWIO_RAP);
479 outl (val, addr+PCNET32_DWIO_BDP);
480 }
481
pcnet32_dwio_read_rap(unsigned long addr)482 static u16 pcnet32_dwio_read_rap (unsigned long addr)
483 {
484 return (inl (addr+PCNET32_DWIO_RAP) & 0xffff);
485 }
486
pcnet32_dwio_write_rap(unsigned long addr,u16 val)487 static void pcnet32_dwio_write_rap (unsigned long addr, u16 val)
488 {
489 outl (val, addr+PCNET32_DWIO_RAP);
490 }
491
pcnet32_dwio_reset(unsigned long addr)492 static void pcnet32_dwio_reset (unsigned long addr)
493 {
494 inl (addr+PCNET32_DWIO_RESET);
495 }
496
pcnet32_dwio_check(unsigned long addr)497 static int pcnet32_dwio_check (unsigned long addr)
498 {
499 outl (88, addr+PCNET32_DWIO_RAP);
500 return ((inl (addr+PCNET32_DWIO_RAP) & 0xffff) == 88);
501 }
502
503 static struct pcnet32_access pcnet32_dwio = {
504 .read_csr = pcnet32_dwio_read_csr,
505 .write_csr = pcnet32_dwio_write_csr,
506 .read_bcr = pcnet32_dwio_read_bcr,
507 .write_bcr = pcnet32_dwio_write_bcr,
508 .read_rap = pcnet32_dwio_read_rap,
509 .write_rap = pcnet32_dwio_write_rap,
510 .reset = pcnet32_dwio_reset
511 };
512
513 #ifdef CONFIG_NET_POLL_CONTROLLER
pcnet32_poll_controller(struct net_device * dev)514 static void pcnet32_poll_controller(struct net_device *dev)
515 {
516 disable_irq(dev->irq);
517 pcnet32_interrupt(0, dev, NULL);
518 enable_irq(dev->irq);
519 }
520 #endif
521
522
pcnet32_get_settings(struct net_device * dev,struct ethtool_cmd * cmd)523 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
524 {
525 struct pcnet32_private *lp = dev->priv;
526 unsigned long flags;
527 int r = -EOPNOTSUPP;
528
529 if (lp->mii) {
530 spin_lock_irqsave(&lp->lock, flags);
531 mii_ethtool_gset(&lp->mii_if, cmd);
532 spin_unlock_irqrestore(&lp->lock, flags);
533 r = 0;
534 }
535 return r;
536 }
537
pcnet32_set_settings(struct net_device * dev,struct ethtool_cmd * cmd)538 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
539 {
540 struct pcnet32_private *lp = dev->priv;
541 unsigned long flags;
542 int r = -EOPNOTSUPP;
543
544 if (lp->mii) {
545 spin_lock_irqsave(&lp->lock, flags);
546 r = mii_ethtool_sset(&lp->mii_if, cmd);
547 spin_unlock_irqrestore(&lp->lock, flags);
548 }
549 return r;
550 }
551
pcnet32_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)552 static void pcnet32_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
553 {
554 struct pcnet32_private *lp = dev->priv;
555
556 strcpy (info->driver, DRV_NAME);
557 strcpy (info->version, DRV_VERSION);
558 if (lp->pci_dev)
559 strcpy (info->bus_info, pci_name(lp->pci_dev));
560 else
561 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
562 }
563
pcnet32_get_link(struct net_device * dev)564 static u32 pcnet32_get_link(struct net_device *dev)
565 {
566 struct pcnet32_private *lp = dev->priv;
567 unsigned long flags;
568 int r;
569
570 spin_lock_irqsave(&lp->lock, flags);
571 if (lp->mii) {
572 r = mii_link_ok(&lp->mii_if);
573 } else {
574 ulong ioaddr = dev->base_addr; /* card base I/O address */
575 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
576 }
577 spin_unlock_irqrestore(&lp->lock, flags);
578
579 return r;
580 }
581
pcnet32_get_msglevel(struct net_device * dev)582 static u32 pcnet32_get_msglevel(struct net_device *dev)
583 {
584 struct pcnet32_private *lp = dev->priv;
585 return lp->msg_enable;
586 }
587
pcnet32_set_msglevel(struct net_device * dev,u32 value)588 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
589 {
590 struct pcnet32_private *lp = dev->priv;
591 lp->msg_enable = value;
592 }
593
pcnet32_nway_reset(struct net_device * dev)594 static int pcnet32_nway_reset(struct net_device *dev)
595 {
596 struct pcnet32_private *lp = dev->priv;
597 unsigned long flags;
598 int r = -EOPNOTSUPP;
599
600 if (lp->mii) {
601 spin_lock_irqsave(&lp->lock, flags);
602 r = mii_nway_restart(&lp->mii_if);
603 spin_unlock_irqrestore(&lp->lock, flags);
604 }
605 return r;
606 }
607
pcnet32_get_ringparam(struct net_device * dev,struct ethtool_ringparam * ering)608 static void pcnet32_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
609 {
610 struct pcnet32_private *lp = dev->priv;
611
612 ering->tx_max_pending = TX_RING_SIZE - 1;
613 ering->tx_pending = lp->cur_tx - lp->dirty_tx;
614 ering->rx_max_pending = RX_RING_SIZE - 1;
615 ering->rx_pending = lp->cur_rx & RX_RING_MOD_MASK;
616 }
617
pcnet32_get_strings(struct net_device * dev,u32 stringset,u8 * data)618 static void pcnet32_get_strings(struct net_device *dev, u32 stringset, u8 *data)
619 {
620 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
621 }
622
pcnet32_self_test_count(struct net_device * dev)623 static int pcnet32_self_test_count(struct net_device *dev)
624 {
625 return PCNET32_TEST_LEN;
626 }
627
pcnet32_ethtool_test(struct net_device * dev,struct ethtool_test * test,u64 * data)628 static void pcnet32_ethtool_test(struct net_device *dev,
629 struct ethtool_test *test, u64 *data)
630 {
631 struct pcnet32_private *lp = dev->priv;
632 int rc;
633
634 if (test->flags == ETH_TEST_FL_OFFLINE) {
635 rc = pcnet32_loopback_test(dev, data);
636 if (rc) {
637 if (netif_msg_hw(lp))
638 printk(KERN_DEBUG "%s: Loopback test failed.\n", dev->name);
639 test->flags |= ETH_TEST_FL_FAILED;
640 } else if (netif_msg_hw(lp))
641 printk(KERN_DEBUG "%s: Loopback test passed.\n", dev->name);
642 } else if (netif_msg_hw(lp))
643 printk(KERN_DEBUG "%s: No tests to run (specify 'Offline' on ethtool).", dev->name);
644 } /* end pcnet32_ethtool_test */
645
pcnet32_loopback_test(struct net_device * dev,uint64_t * data1)646 static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1)
647 {
648 struct pcnet32_private *lp = dev->priv;
649 struct pcnet32_access *a = &lp->a; /* access to registers */
650 ulong ioaddr = dev->base_addr; /* card base I/O address */
651 struct sk_buff *skb; /* sk buff */
652 int x, i; /* counters */
653 int numbuffs = 4; /* number of TX/RX buffers and descs */
654 u16 status = 0x8300; /* TX ring status */
655 u16 teststatus; /* test of ring status */
656 int rc; /* return code */
657 int size; /* size of packets */
658 unsigned char *packet; /* source packet data */
659 static int data_len = 60; /* length of source packets */
660 unsigned long flags;
661 unsigned long ticks;
662
663 *data1 = 1; /* status of test, default to fail */
664 rc = 1; /* default to fail */
665
666 if (netif_running(dev))
667 pcnet32_close(dev);
668
669 spin_lock_irqsave(&lp->lock, flags);
670
671 /* Reset the PCNET32 */
672 lp->a.reset (ioaddr);
673
674 /* switch pcnet32 to 32bit mode */
675 lp->a.write_bcr (ioaddr, 20, 2);
676
677 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
678 lp->init_block.filter[0] = 0;
679 lp->init_block.filter[1] = 0;
680
681 /* purge & init rings but don't actually restart */
682 pcnet32_restart(dev, 0x0000);
683
684 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
685
686 /* Initialize Transmit buffers. */
687 size = data_len + 15;
688 for (x=0; x<numbuffs; x++) {
689 if (!(skb = dev_alloc_skb(size))) {
690 if (netif_msg_hw(lp))
691 printk(KERN_DEBUG "%s: Cannot allocate skb at line: %d!\n",
692 dev->name, __LINE__);
693 goto clean_up;
694 } else {
695 packet = skb->data;
696 skb_put(skb, size); /* create space for data */
697 lp->tx_skbuff[x] = skb;
698 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
699 lp->tx_ring[x].misc = 0;
700
701 /* put DA and SA into the skb */
702 for (i=0; i<6; i++)
703 *packet++ = dev->dev_addr[i];
704 for (i=0; i<6; i++)
705 *packet++ = dev->dev_addr[i];
706 /* type */
707 *packet++ = 0x08;
708 *packet++ = 0x06;
709 /* packet number */
710 *packet++ = x;
711 /* fill packet with data */
712 for (i=0; i<data_len; i++)
713 *packet++ = i;
714
715 lp->tx_dma_addr[x] = pci_map_single(lp->pci_dev, skb->data,
716 skb->len, PCI_DMA_TODEVICE);
717 lp->tx_ring[x].base = (u32)le32_to_cpu(lp->tx_dma_addr[x]);
718 wmb(); /* Make sure owner changes after all others are visible */
719 lp->tx_ring[x].status = le16_to_cpu(status);
720 }
721 }
722
723 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BSR32 */
724 x = x | 0x0002;
725 a->write_bcr(ioaddr, 32, x);
726
727 lp->a.write_csr (ioaddr, 15, 0x0044); /* set int loopback in CSR15 */
728
729 teststatus = le16_to_cpu(0x8000);
730 lp->a.write_csr(ioaddr, 0, 0x0002); /* Set STRT bit */
731
732 /* Check status of descriptors */
733 for (x=0; x<numbuffs; x++) {
734 ticks = 0;
735 rmb();
736 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
737 spin_unlock_irqrestore(&lp->lock, flags);
738 mdelay(1);
739 spin_lock_irqsave(&lp->lock, flags);
740 rmb();
741 ticks++;
742 }
743 if (ticks == 200) {
744 if (netif_msg_hw(lp))
745 printk("%s: Desc %d failed to reset!\n",dev->name,x);
746 break;
747 }
748 }
749
750 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
751 wmb();
752 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
753 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
754
755 for (x=0; x<numbuffs; x++) {
756 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
757 skb = lp->rx_skbuff[x];
758 for (i=0; i<size; i++) {
759 printk("%02x ", *(skb->data+i));
760 }
761 printk("\n");
762 }
763 }
764
765 x = 0;
766 rc = 0;
767 while (x<numbuffs && !rc) {
768 skb = lp->rx_skbuff[x];
769 packet = lp->tx_skbuff[x]->data;
770 for (i=0; i<size; i++) {
771 if (*(skb->data+i) != packet[i]) {
772 if (netif_msg_hw(lp))
773 printk(KERN_DEBUG "%s: Error in compare! %2x - %02x %02x\n",
774 dev->name, i, *(skb->data+i), packet[i]);
775 rc = 1;
776 break;
777 }
778 }
779 x++;
780 }
781 if (!rc) {
782 *data1 = 0;
783 }
784
785 clean_up:
786 x = a->read_csr(ioaddr, 15) & 0xFFFF;
787 a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */
788
789 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
790 x = x & ~0x0002;
791 a->write_bcr(ioaddr, 32, x);
792
793 spin_unlock_irqrestore(&lp->lock, flags);
794
795 if (netif_running(dev)) {
796 pcnet32_open(dev);
797 } else {
798 lp->a.write_bcr (ioaddr, 20, 4); /* return to 16bit mode */
799 }
800
801 return(rc);
802 } /* end pcnet32_loopback_test */
803
pcnet32_led_blink_callback(struct net_device * dev)804 static void pcnet32_led_blink_callback(struct net_device *dev)
805 {
806 struct pcnet32_private *lp = dev->priv;
807 struct pcnet32_access *a = &lp->a;
808 ulong ioaddr = dev->base_addr;
809 unsigned long flags;
810 int i;
811
812 spin_lock_irqsave(&lp->lock, flags);
813 for (i=4; i<8; i++) {
814 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
815 }
816 spin_unlock_irqrestore(&lp->lock, flags);
817
818 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
819 }
820
pcnet32_phys_id(struct net_device * dev,u32 data)821 static int pcnet32_phys_id(struct net_device *dev, u32 data)
822 {
823 struct pcnet32_private *lp = dev->priv;
824 struct pcnet32_access *a = &lp->a;
825 ulong ioaddr = dev->base_addr;
826 unsigned long flags;
827 int i, regs[4];
828
829 if (!lp->blink_timer.function) {
830 init_timer(&lp->blink_timer);
831 lp->blink_timer.function = (void *) pcnet32_led_blink_callback;
832 lp->blink_timer.data = (unsigned long) dev;
833 }
834
835 /* Save the current value of the bcrs */
836 spin_lock_irqsave(&lp->lock, flags);
837 for (i=4; i<8; i++) {
838 regs[i-4] = a->read_bcr(ioaddr, i);
839 }
840 spin_unlock_irqrestore(&lp->lock, flags);
841
842 mod_timer(&lp->blink_timer, jiffies);
843 set_current_state(TASK_INTERRUPTIBLE);
844
845 if ((!data) || (data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)))
846 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
847
848 schedule_timeout(data * HZ);
849 del_timer_sync(&lp->blink_timer);
850
851 /* Restore the original value of the bcrs */
852 spin_lock_irqsave(&lp->lock, flags);
853 for (i=4; i<8; i++) {
854 a->write_bcr(ioaddr, i, regs[i-4]);
855 }
856 spin_unlock_irqrestore(&lp->lock, flags);
857
858 return 0;
859 }
860
pcnet32_get_regs_len(struct net_device * dev)861 static int pcnet32_get_regs_len(struct net_device *dev)
862 {
863 return(PCNET32_NUM_REGS * sizeof(u16));
864 }
865
pcnet32_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * ptr)866 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
867 void *ptr)
868 {
869 int i, csr0;
870 u16 *buff = ptr;
871 struct pcnet32_private *lp = dev->priv;
872 struct pcnet32_access *a = &lp->a;
873 ulong ioaddr = dev->base_addr;
874 int ticks;
875 unsigned long flags;
876
877 spin_lock_irqsave(&lp->lock, flags);
878
879 csr0 = a->read_csr(ioaddr, 0);
880 if (!(csr0 & 0x0004)) { /* If not stopped */
881 /* set SUSPEND (SPND) - CSR5 bit 0 */
882 a->write_csr(ioaddr, 5, 0x0001);
883
884 /* poll waiting for bit to be set */
885 ticks = 0;
886 while (!(a->read_csr(ioaddr, 5) & 0x0001)) {
887 spin_unlock_irqrestore(&lp->lock, flags);
888 mdelay(1);
889 spin_lock_irqsave(&lp->lock, flags);
890 ticks++;
891 if (ticks > 200) {
892 if (netif_msg_hw(lp))
893 printk(KERN_DEBUG "%s: Error getting into suspend!\n",
894 dev->name);
895 break;
896 }
897 }
898 }
899
900 /* read address PROM */
901 for (i=0; i<16; i += 2)
902 *buff++ = inw(ioaddr + i);
903
904 /* read control and status registers */
905 for (i=0; i<90; i++) {
906 *buff++ = a->read_csr(ioaddr, i);
907 }
908
909 *buff++ = a->read_csr(ioaddr, 112);
910 *buff++ = a->read_csr(ioaddr, 114);
911
912 /* read bus configuration registers */
913 for (i=0; i<36; i++) {
914 *buff++ = a->read_bcr(ioaddr, i);
915 }
916
917 /* read mii phy registers */
918 if (lp->mii) {
919 for (i=0; i<32; i++) {
920 lp->a.write_bcr(ioaddr, 33, ((lp->mii_if.phy_id) << 5) | i);
921 *buff++ = lp->a.read_bcr(ioaddr, 34);
922 }
923 }
924
925 if (!(csr0 & 0x0004)) { /* If not stopped */
926 /* clear SUSPEND (SPND) - CSR5 bit 0 */
927 a->write_csr(ioaddr, 5, 0x0000);
928 }
929
930 i = buff - (u16 *)ptr;
931 for (; i < PCNET32_NUM_REGS; i++)
932 *buff++ = 0;
933
934 spin_unlock_irqrestore(&lp->lock, flags);
935 }
936
937 static struct ethtool_ops pcnet32_ethtool_ops = {
938 .get_settings = pcnet32_get_settings,
939 .set_settings = pcnet32_set_settings,
940 .get_drvinfo = pcnet32_get_drvinfo,
941 .get_msglevel = pcnet32_get_msglevel,
942 .set_msglevel = pcnet32_set_msglevel,
943 .nway_reset = pcnet32_nway_reset,
944 .get_link = pcnet32_get_link,
945 .get_ringparam = pcnet32_get_ringparam,
946 .get_tx_csum = ethtool_op_get_tx_csum,
947 .get_sg = ethtool_op_get_sg,
948 .get_strings = pcnet32_get_strings,
949 .self_test_count = pcnet32_self_test_count,
950 .self_test = pcnet32_ethtool_test,
951 .phys_id = pcnet32_phys_id,
952 .get_regs_len = pcnet32_get_regs_len,
953 .get_regs = pcnet32_get_regs,
954 };
955
956 /* only probes for non-PCI devices, the rest are handled by
957 * pci_register_driver via pcnet32_probe_pci */
958
959 static void __devinit
pcnet32_probe_vlbus(void)960 pcnet32_probe_vlbus(void)
961 {
962 unsigned int *port, ioaddr;
963
964 /* search for PCnet32 VLB cards at known addresses */
965 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
966 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
967 /* check if there is really a pcnet chip on that ioaddr */
968 if ((inb(ioaddr + 14) == 0x57) && (inb(ioaddr + 15) == 0x57)) {
969 pcnet32_probe1(ioaddr, 0, NULL);
970 } else {
971 release_region(ioaddr, PCNET32_TOTAL_SIZE);
972 }
973 }
974 }
975 }
976
977
978 static int __devinit
pcnet32_probe_pci(struct pci_dev * pdev,const struct pci_device_id * ent)979 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
980 {
981 unsigned long ioaddr;
982 int err;
983
984 err = pci_enable_device(pdev);
985 if (err < 0) {
986 if (pcnet32_debug & NETIF_MSG_PROBE)
987 printk(KERN_ERR PFX "failed to enable device -- err=%d\n", err);
988 return err;
989 }
990 pci_set_master(pdev);
991
992 ioaddr = pci_resource_start (pdev, 0);
993 if (!ioaddr) {
994 if (pcnet32_debug & NETIF_MSG_PROBE)
995 printk (KERN_ERR PFX "card has no PCI IO resources, aborting\n");
996 return -ENODEV;
997 }
998
999 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1000 if (pcnet32_debug & NETIF_MSG_PROBE)
1001 printk(KERN_ERR PFX "architecture does not support 32bit PCI busmaster DMA\n");
1002 return -ENODEV;
1003 }
1004 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") == NULL) {
1005 if (pcnet32_debug & NETIF_MSG_PROBE)
1006 printk(KERN_ERR PFX "io address range already allocated\n");
1007 return -EBUSY;
1008 }
1009
1010 err = pcnet32_probe1(ioaddr, 1, pdev);
1011 if (err < 0) {
1012 pci_disable_device(pdev);
1013 }
1014 return err;
1015 }
1016
1017
1018 /* pcnet32_probe1
1019 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1020 * pdev will be NULL when called from pcnet32_probe_vlbus.
1021 */
1022 static int __devinit
pcnet32_probe1(unsigned long ioaddr,int shared,struct pci_dev * pdev)1023 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1024 {
1025 struct pcnet32_private *lp;
1026 dma_addr_t lp_dma_addr;
1027 int i, media;
1028 int fdx, mii, fset, dxsuflo;
1029 int chip_version;
1030 char *chipname;
1031 struct net_device *dev;
1032 struct pcnet32_access *a = NULL;
1033 u8 promaddr[6];
1034 int ret = -ENODEV;
1035
1036 /* reset the chip */
1037 pcnet32_wio_reset(ioaddr);
1038
1039 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1040 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1041 a = &pcnet32_wio;
1042 } else {
1043 pcnet32_dwio_reset(ioaddr);
1044 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) {
1045 a = &pcnet32_dwio;
1046 } else
1047 goto err_release_region;
1048 }
1049
1050 chip_version = a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr,89) << 16);
1051 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1052 printk(KERN_INFO " PCnet chip version is %#x.\n", chip_version);
1053 if ((chip_version & 0xfff) != 0x003) {
1054 if (pcnet32_debug & NETIF_MSG_PROBE)
1055 printk(KERN_INFO PFX "Unsupported chip version.\n");
1056 goto err_release_region;
1057 }
1058
1059 /* initialize variables */
1060 fdx = mii = fset = dxsuflo = 0;
1061 chip_version = (chip_version >> 12) & 0xffff;
1062
1063 switch (chip_version) {
1064 case 0x2420:
1065 chipname = "PCnet/PCI 79C970"; /* PCI */
1066 break;
1067 case 0x2430:
1068 if (shared)
1069 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1070 else
1071 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1072 break;
1073 case 0x2621:
1074 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1075 fdx = 1;
1076 break;
1077 case 0x2623:
1078 chipname = "PCnet/FAST 79C971"; /* PCI */
1079 fdx = 1; mii = 1; fset = 1;
1080 break;
1081 case 0x2624:
1082 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1083 fdx = 1; mii = 1; fset = 1;
1084 break;
1085 case 0x2625:
1086 chipname = "PCnet/FAST III 79C973"; /* PCI */
1087 fdx = 1; mii = 1;
1088 break;
1089 case 0x2626:
1090 chipname = "PCnet/Home 79C978"; /* PCI */
1091 fdx = 1;
1092 /*
1093 * This is based on specs published at www.amd.com. This section
1094 * assumes that a card with a 79C978 wants to go into standard
1095 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1096 * and the module option homepna=1 can select this instead.
1097 */
1098 media = a->read_bcr(ioaddr, 49);
1099 media &= ~3; /* default to 10Mb ethernet */
1100 if (cards_found < MAX_UNITS && homepna[cards_found])
1101 media |= 1; /* switch to home wiring mode */
1102 if (pcnet32_debug & NETIF_MSG_PROBE)
1103 printk(KERN_DEBUG PFX "media set to %dMbit mode.\n",
1104 (media & 1) ? 1 : 10);
1105 a->write_bcr(ioaddr, 49, media);
1106 break;
1107 case 0x2627:
1108 chipname = "PCnet/FAST III 79C975"; /* PCI */
1109 fdx = 1; mii = 1;
1110 break;
1111 case 0x2628:
1112 chipname = "PCnet/PRO 79C976";
1113 fdx = 1; mii = 1;
1114 break;
1115 default:
1116 if (pcnet32_debug & NETIF_MSG_PROBE)
1117 printk(KERN_INFO PFX "PCnet version %#x, no PCnet32 chip.\n",
1118 chip_version);
1119 goto err_release_region;
1120 }
1121
1122 /*
1123 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1124 * starting until the packet is loaded. Strike one for reliability, lose
1125 * one for latency - although on PCI this isnt a big loss. Older chips
1126 * have FIFO's smaller than a packet, so you can't do this.
1127 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1128 */
1129
1130 if (fset) {
1131 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1132 a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1133 dxsuflo = 1;
1134 }
1135
1136 dev = alloc_etherdev(0);
1137 if (!dev) {
1138 if (pcnet32_debug & NETIF_MSG_PROBE)
1139 printk(KERN_ERR PFX "Memory allocation failed.\n");
1140 ret = -ENOMEM;
1141 goto err_release_region;
1142 }
1143 SET_NETDEV_DEV(dev, &pdev->dev);
1144
1145 if (pcnet32_debug & NETIF_MSG_PROBE)
1146 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1147
1148 /* In most chips, after a chip reset, the ethernet address is read from the
1149 * station address PROM at the base address and programmed into the
1150 * "Physical Address Registers" CSR12-14.
1151 * As a precautionary measure, we read the PROM values and complain if
1152 * they disagree with the CSRs. Either way, we use the CSR values, and
1153 * double check that they are valid.
1154 */
1155 for (i = 0; i < 3; i++) {
1156 unsigned int val;
1157 val = a->read_csr(ioaddr, i+12) & 0x0ffff;
1158 /* There may be endianness issues here. */
1159 dev->dev_addr[2*i] = val & 0x0ff;
1160 dev->dev_addr[2*i+1] = (val >> 8) & 0x0ff;
1161 }
1162
1163 /* read PROM address and compare with CSR address */
1164 for (i = 0; i < 6; i++)
1165 promaddr[i] = inb(ioaddr + i);
1166
1167 if (memcmp(promaddr, dev->dev_addr, 6)
1168 || !is_valid_ether_addr(dev->dev_addr)) {
1169 #ifndef __powerpc__
1170 if (is_valid_ether_addr(promaddr)) {
1171 #else
1172 if (!is_valid_ether_addr(dev->dev_addr)
1173 && is_valid_ether_addr(promaddr)) {
1174 #endif
1175 if (pcnet32_debug & NETIF_MSG_PROBE) {
1176 printk(" warning: CSR address invalid,\n");
1177 printk(KERN_INFO " using instead PROM address of");
1178 }
1179 memcpy(dev->dev_addr, promaddr, 6);
1180 }
1181 }
1182
1183 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1184 if (!is_valid_ether_addr(dev->dev_addr))
1185 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1186
1187 if (pcnet32_debug & NETIF_MSG_PROBE) {
1188 for (i = 0; i < 6; i++)
1189 printk(" %2.2x", dev->dev_addr[i]);
1190
1191 /* Version 0x2623 - 0x2624 */
1192 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1193 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1194 printk("\n" KERN_INFO " tx_start_pt(0x%04x):",i);
1195 switch(i>>10) {
1196 case 0: printk(" 20 bytes,"); break;
1197 case 1: printk(" 64 bytes,"); break;
1198 case 2: printk(" 128 bytes,"); break;
1199 case 3: printk("~220 bytes,"); break;
1200 }
1201 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1202 printk(" BCR18(%x):",i&0xffff);
1203 if (i & (1<<5)) printk("BurstWrEn ");
1204 if (i & (1<<6)) printk("BurstRdEn ");
1205 if (i & (1<<7)) printk("DWordIO ");
1206 if (i & (1<<11)) printk("NoUFlow ");
1207 i = a->read_bcr(ioaddr, 25);
1208 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,",i<<8);
1209 i = a->read_bcr(ioaddr, 26);
1210 printk(" SRAM_BND=0x%04x,",i<<8);
1211 i = a->read_bcr(ioaddr, 27);
1212 if (i & (1<<14)) printk("LowLatRx");
1213 }
1214 }
1215
1216 dev->base_addr = ioaddr;
1217 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1218 if ((lp = pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1219 if (pcnet32_debug & NETIF_MSG_PROBE)
1220 printk(KERN_ERR PFX "Consistent memory allocation failed.\n");
1221 ret = -ENOMEM;
1222 goto err_free_netdev;
1223 }
1224
1225 memset(lp, 0, sizeof(*lp));
1226 lp->dma_addr = lp_dma_addr;
1227 lp->pci_dev = pdev;
1228
1229 spin_lock_init(&lp->lock);
1230
1231 SET_MODULE_OWNER(dev);
1232 SET_NETDEV_DEV(dev, &pdev->dev);
1233 dev->priv = lp;
1234 lp->name = chipname;
1235 lp->shared_irq = shared;
1236 lp->mii_if.full_duplex = fdx;
1237 lp->mii_if.phy_id_mask = 0x1f;
1238 lp->mii_if.reg_num_mask = 0x1f;
1239 lp->dxsuflo = dxsuflo;
1240 lp->mii = mii;
1241 lp->msg_enable = pcnet32_debug;
1242 if ((cards_found >= MAX_UNITS) || (options[cards_found] > sizeof(options_mapping)))
1243 lp->options = PCNET32_PORT_ASEL;
1244 else
1245 lp->options = options_mapping[options[cards_found]];
1246 lp->mii_if.dev = dev;
1247 lp->mii_if.mdio_read = mdio_read;
1248 lp->mii_if.mdio_write = mdio_write;
1249
1250 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1251 ((cards_found>=MAX_UNITS) || full_duplex[cards_found]))
1252 lp->options |= PCNET32_PORT_FD;
1253
1254 if (!a) {
1255 if (pcnet32_debug & NETIF_MSG_PROBE)
1256 printk(KERN_ERR PFX "No access methods\n");
1257 ret = -ENODEV;
1258 goto err_free_consistent;
1259 }
1260 lp->a = *a;
1261
1262 /* detect special T1/E1 WAN card by checking for MAC address */
1263 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1264 && dev->dev_addr[2] == 0x75)
1265 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1266
1267 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1268 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
1269 for (i = 0; i < 6; i++)
1270 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1271 lp->init_block.filter[0] = 0x00000000;
1272 lp->init_block.filter[1] = 0x00000000;
1273 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr +
1274 offsetof(struct pcnet32_private, rx_ring));
1275 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr +
1276 offsetof(struct pcnet32_private, tx_ring));
1277
1278 /* switch pcnet32 to 32bit mode */
1279 a->write_bcr(ioaddr, 20, 2);
1280
1281 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1282 init_block)) & 0xffff);
1283 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1284 init_block)) >> 16);
1285
1286 if (pdev) { /* use the IRQ provided by PCI */
1287 dev->irq = pdev->irq;
1288 if (pcnet32_debug & NETIF_MSG_PROBE)
1289 printk(" assigned IRQ %d.\n", dev->irq);
1290 } else {
1291 unsigned long irq_mask = probe_irq_on();
1292
1293 /*
1294 * To auto-IRQ we enable the initialization-done and DMA error
1295 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1296 * boards will work.
1297 */
1298 /* Trigger an initialization just for the interrupt. */
1299 a->write_csr (ioaddr, 0, 0x41);
1300 mdelay (1);
1301
1302 dev->irq = probe_irq_off (irq_mask);
1303 if (!dev->irq) {
1304 if (pcnet32_debug & NETIF_MSG_PROBE)
1305 printk(", failed to detect IRQ line.\n");
1306 ret = -ENODEV;
1307 goto err_free_consistent;
1308 }
1309 if (pcnet32_debug & NETIF_MSG_PROBE)
1310 printk(", probed IRQ %d.\n", dev->irq);
1311 }
1312
1313 /* Set the mii phy_id so that we can query the link state */
1314 if (lp->mii)
1315 lp->mii_if.phy_id = ((lp->a.read_bcr (ioaddr, 33)) >> 5) & 0x1f;
1316
1317 init_timer (&lp->watchdog_timer);
1318 lp->watchdog_timer.data = (unsigned long) dev;
1319 lp->watchdog_timer.function = (void *) &pcnet32_watchdog;
1320
1321 /* The PCNET32-specific entries in the device structure. */
1322 dev->open = &pcnet32_open;
1323 dev->hard_start_xmit = &pcnet32_start_xmit;
1324 dev->stop = &pcnet32_close;
1325 dev->get_stats = &pcnet32_get_stats;
1326 dev->set_multicast_list = &pcnet32_set_multicast_list;
1327 dev->do_ioctl = &pcnet32_ioctl;
1328 dev->ethtool_ops = &pcnet32_ethtool_ops;
1329 dev->tx_timeout = pcnet32_tx_timeout;
1330 dev->watchdog_timeo = (5*HZ);
1331
1332 #ifdef CONFIG_NET_POLL_CONTROLLER
1333 dev->poll_controller = pcnet32_poll_controller;
1334 #endif
1335
1336 /* Fill in the generic fields of the device structure. */
1337 if (register_netdev(dev))
1338 goto err_free_consistent;
1339
1340 if (pdev) {
1341 pci_set_drvdata(pdev, dev);
1342 } else {
1343 lp->next = pcnet32_dev;
1344 pcnet32_dev = dev;
1345 }
1346
1347 if (pcnet32_debug & NETIF_MSG_PROBE)
1348 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1349 cards_found++;
1350
1351 /* enable LED writes */
1352 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1353
1354 return 0;
1355
1356 err_free_consistent:
1357 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1358 err_free_netdev:
1359 free_netdev(dev);
1360 err_release_region:
1361 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1362 return ret;
1363 }
1364
1365
1366 static int
1367 pcnet32_open(struct net_device *dev)
1368 {
1369 struct pcnet32_private *lp = dev->priv;
1370 unsigned long ioaddr = dev->base_addr;
1371 u16 val;
1372 int i;
1373 int rc;
1374 unsigned long flags;
1375
1376 if (request_irq(dev->irq, &pcnet32_interrupt,
1377 lp->shared_irq ? SA_SHIRQ : 0, dev->name, (void *)dev)) {
1378 return -EAGAIN;
1379 }
1380
1381 spin_lock_irqsave(&lp->lock, flags);
1382 /* Check for a valid station address */
1383 if (!is_valid_ether_addr(dev->dev_addr)) {
1384 rc = -EINVAL;
1385 goto err_free_irq;
1386 }
1387
1388 /* Reset the PCNET32 */
1389 lp->a.reset (ioaddr);
1390
1391 /* switch pcnet32 to 32bit mode */
1392 lp->a.write_bcr (ioaddr, 20, 2);
1393
1394 if (netif_msg_ifup(lp))
1395 printk(KERN_DEBUG "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1396 dev->name, dev->irq,
1397 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, tx_ring)),
1398 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, rx_ring)),
1399 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)));
1400
1401 /* set/reset autoselect bit */
1402 val = lp->a.read_bcr (ioaddr, 2) & ~2;
1403 if (lp->options & PCNET32_PORT_ASEL)
1404 val |= 2;
1405 lp->a.write_bcr (ioaddr, 2, val);
1406
1407 /* handle full duplex setting */
1408 if (lp->mii_if.full_duplex) {
1409 val = lp->a.read_bcr (ioaddr, 9) & ~3;
1410 if (lp->options & PCNET32_PORT_FD) {
1411 val |= 1;
1412 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
1413 val |= 2;
1414 } else if (lp->options & PCNET32_PORT_ASEL) {
1415 /* workaround of xSeries250, turn on for 79C975 only */
1416 i = ((lp->a.read_csr(ioaddr, 88) |
1417 (lp->a.read_csr(ioaddr,89) << 16)) >> 12) & 0xffff;
1418 if (i == 0x2627)
1419 val |= 3;
1420 }
1421 lp->a.write_bcr (ioaddr, 9, val);
1422 }
1423
1424 /* set/reset GPSI bit in test register */
1425 val = lp->a.read_csr (ioaddr, 124) & ~0x10;
1426 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
1427 val |= 0x10;
1428 lp->a.write_csr (ioaddr, 124, val);
1429
1430 /* 24 Jun 2004 according AMD, in order to change the PHY,
1431 * DANAS (or DISPM for 79C976) must be set; then select the speed,
1432 * duplex, and/or enable auto negotiation, and clear DANAS */
1433 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
1434 lp->a.write_bcr(ioaddr, 32, lp->a.read_bcr(ioaddr, 32) | 0x0080);
1435 /* disable Auto Negotiation, set 10Mpbs, HD */
1436 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
1437 if (lp->options & PCNET32_PORT_FD)
1438 val |= 0x10;
1439 if (lp->options & PCNET32_PORT_100)
1440 val |= 0x08;
1441 lp->a.write_bcr (ioaddr, 32, val);
1442 } else {
1443 if (lp->options & PCNET32_PORT_ASEL) {
1444 lp->a.write_bcr(ioaddr, 32, lp->a.read_bcr(ioaddr, 32) | 0x0080);
1445 /* enable auto negotiate, setup, disable fd */
1446 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
1447 val |= 0x20;
1448 lp->a.write_bcr(ioaddr, 32, val);
1449 }
1450 }
1451
1452 #ifdef DO_DXSUFLO
1453 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
1454 val = lp->a.read_csr (ioaddr, 3);
1455 val |= 0x40;
1456 lp->a.write_csr (ioaddr, 3, val);
1457 }
1458 #endif
1459
1460 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1461 pcnet32_load_multicast(dev);
1462
1463 if (pcnet32_init_ring(dev)) {
1464 rc = -ENOMEM;
1465 goto err_free_ring;
1466 }
1467
1468 /* Re-initialize the PCNET32, and start it when done. */
1469 lp->a.write_csr (ioaddr, 1, (lp->dma_addr +
1470 offsetof(struct pcnet32_private, init_block)) &0xffff);
1471 lp->a.write_csr (ioaddr, 2, (lp->dma_addr +
1472 offsetof(struct pcnet32_private, init_block)) >> 16);
1473
1474 lp->a.write_csr (ioaddr, 4, 0x0915);
1475 lp->a.write_csr (ioaddr, 0, 0x0001);
1476
1477 netif_start_queue(dev);
1478
1479 /* If we have mii, print the link status and start the watchdog */
1480 if (lp->mii) {
1481 mii_check_media (&lp->mii_if, netif_msg_link(lp), 1);
1482 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1483 }
1484
1485 i = 0;
1486 while (i++ < 100)
1487 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1488 break;
1489 /*
1490 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
1491 * reports that doing so triggers a bug in the '974.
1492 */
1493 lp->a.write_csr (ioaddr, 0, 0x0042);
1494
1495 if (netif_msg_ifup(lp))
1496 printk(KERN_DEBUG "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
1497 dev->name, i, (u32) (lp->dma_addr +
1498 offsetof(struct pcnet32_private, init_block)),
1499 lp->a.read_csr(ioaddr, 0));
1500
1501 spin_unlock_irqrestore(&lp->lock, flags);
1502
1503 return 0; /* Always succeed */
1504
1505 err_free_ring:
1506 /* free any allocated skbuffs */
1507 for (i = 0; i < RX_RING_SIZE; i++) {
1508 lp->rx_ring[i].status = 0;
1509 if (lp->rx_skbuff[i]) {
1510 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2,
1511 PCI_DMA_FROMDEVICE);
1512 dev_kfree_skb(lp->rx_skbuff[i]);
1513 }
1514 lp->rx_skbuff[i] = NULL;
1515 lp->rx_dma_addr[i] = 0;
1516 }
1517 /*
1518 * Switch back to 16bit mode to avoid problems with dumb
1519 * DOS packet driver after a warm reboot
1520 */
1521 lp->a.write_bcr (ioaddr, 20, 4);
1522
1523 err_free_irq:
1524 spin_unlock_irqrestore(&lp->lock, flags);
1525 free_irq(dev->irq, dev);
1526 return rc;
1527 }
1528
1529 /*
1530 * The LANCE has been halted for one reason or another (busmaster memory
1531 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
1532 * etc.). Modern LANCE variants always reload their ring-buffer
1533 * configuration when restarted, so we must reinitialize our ring
1534 * context before restarting. As part of this reinitialization,
1535 * find all packets still on the Tx ring and pretend that they had been
1536 * sent (in effect, drop the packets on the floor) - the higher-level
1537 * protocols will time out and retransmit. It'd be better to shuffle
1538 * these skbs to a temp list and then actually re-Tx them after
1539 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
1540 */
1541
1542 static void
1543 pcnet32_purge_tx_ring(struct net_device *dev)
1544 {
1545 struct pcnet32_private *lp = dev->priv;
1546 int i;
1547
1548 for (i = 0; i < TX_RING_SIZE; i++) {
1549 lp->tx_ring[i].status = 0; /* CPU owns buffer */
1550 wmb(); /* Make sure adapter sees owner change */
1551 if (lp->tx_skbuff[i]) {
1552 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
1553 lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
1554 dev_kfree_skb_any(lp->tx_skbuff[i]);
1555 }
1556 lp->tx_skbuff[i] = NULL;
1557 lp->tx_dma_addr[i] = 0;
1558 }
1559 }
1560
1561
1562 /* Initialize the PCNET32 Rx and Tx rings. */
1563 static int
1564 pcnet32_init_ring(struct net_device *dev)
1565 {
1566 struct pcnet32_private *lp = dev->priv;
1567 int i;
1568
1569 lp->tx_full = 0;
1570 lp->cur_rx = lp->cur_tx = 0;
1571 lp->dirty_rx = lp->dirty_tx = 0;
1572
1573 for (i = 0; i < RX_RING_SIZE; i++) {
1574 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
1575 if (rx_skbuff == NULL) {
1576 if (!(rx_skbuff = lp->rx_skbuff[i] = dev_alloc_skb (PKT_BUF_SZ))) {
1577 /* there is not much, we can do at this point */
1578 if (pcnet32_debug & NETIF_MSG_DRV)
1579 printk(KERN_ERR "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
1580 dev->name);
1581 return -1;
1582 }
1583 skb_reserve (rx_skbuff, 2);
1584 }
1585
1586 rmb();
1587 if (lp->rx_dma_addr[i] == 0)
1588 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, rx_skbuff->tail,
1589 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
1590 lp->rx_ring[i].base = (u32)le32_to_cpu(lp->rx_dma_addr[i]);
1591 lp->rx_ring[i].buf_length = le16_to_cpu(2-PKT_BUF_SZ);
1592 wmb(); /* Make sure owner changes after all others are visible */
1593 lp->rx_ring[i].status = le16_to_cpu(0x8000);
1594 }
1595 /* The Tx buffer address is filled in as needed, but we do need to clear
1596 * the upper ownership bit. */
1597 for (i = 0; i < TX_RING_SIZE; i++) {
1598 lp->tx_ring[i].status = 0; /* CPU owns buffer */
1599 wmb(); /* Make sure adapter sees owner change */
1600 lp->tx_ring[i].base = 0;
1601 lp->tx_dma_addr[i] = 0;
1602 }
1603
1604 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
1605 for (i = 0; i < 6; i++)
1606 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1607 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr +
1608 offsetof(struct pcnet32_private, rx_ring));
1609 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr +
1610 offsetof(struct pcnet32_private, tx_ring));
1611 wmb(); /* Make sure all changes are visible */
1612 return 0;
1613 }
1614
1615 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
1616 * then flush the pending transmit operations, re-initialize the ring,
1617 * and tell the chip to initialize.
1618 */
1619 static void
1620 pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1621 {
1622 struct pcnet32_private *lp = dev->priv;
1623 unsigned long ioaddr = dev->base_addr;
1624 int i;
1625
1626 /* wait for stop */
1627 for (i=0; i<100; i++)
1628 if (lp->a.read_csr(ioaddr, 0) & 0x0004)
1629 break;
1630
1631 if (i >= 100 && netif_msg_drv(lp))
1632 printk(KERN_ERR "%s: pcnet32_restart timed out waiting for stop.\n",
1633 dev->name);
1634
1635 pcnet32_purge_tx_ring(dev);
1636 if (pcnet32_init_ring(dev))
1637 return;
1638
1639 /* ReInit Ring */
1640 lp->a.write_csr (ioaddr, 0, 1);
1641 i = 0;
1642 while (i++ < 1000)
1643 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1644 break;
1645
1646 lp->a.write_csr (ioaddr, 0, csr0_bits);
1647 }
1648
1649
1650 static void
1651 pcnet32_tx_timeout (struct net_device *dev)
1652 {
1653 struct pcnet32_private *lp = dev->priv;
1654 unsigned long ioaddr = dev->base_addr, flags;
1655
1656 spin_lock_irqsave(&lp->lock, flags);
1657 /* Transmitter timeout, serious problems. */
1658 if (pcnet32_debug & NETIF_MSG_DRV)
1659 printk(KERN_ERR "%s: transmit timed out, status %4.4x, resetting.\n",
1660 dev->name, lp->a.read_csr(ioaddr, 0));
1661 lp->a.write_csr (ioaddr, 0, 0x0004);
1662 lp->stats.tx_errors++;
1663 if (netif_msg_tx_err(lp)) {
1664 int i;
1665 printk(KERN_DEBUG " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
1666 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
1667 lp->cur_rx);
1668 for (i = 0 ; i < RX_RING_SIZE; i++)
1669 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1670 le32_to_cpu(lp->rx_ring[i].base),
1671 (-le16_to_cpu(lp->rx_ring[i].buf_length)) & 0xffff,
1672 le32_to_cpu(lp->rx_ring[i].msg_length),
1673 le16_to_cpu(lp->rx_ring[i].status));
1674 for (i = 0 ; i < TX_RING_SIZE; i++)
1675 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1676 le32_to_cpu(lp->tx_ring[i].base),
1677 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
1678 le32_to_cpu(lp->tx_ring[i].misc),
1679 le16_to_cpu(lp->tx_ring[i].status));
1680 printk("\n");
1681 }
1682 pcnet32_restart(dev, 0x0042);
1683
1684 dev->trans_start = jiffies;
1685 netif_wake_queue(dev);
1686
1687 spin_unlock_irqrestore(&lp->lock, flags);
1688 }
1689
1690
1691 static int
1692 pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1693 {
1694 struct pcnet32_private *lp = dev->priv;
1695 unsigned long ioaddr = dev->base_addr;
1696 u16 status;
1697 int entry;
1698 unsigned long flags;
1699
1700 spin_lock_irqsave(&lp->lock, flags);
1701
1702 if (netif_msg_tx_queued(lp)) {
1703 printk(KERN_DEBUG "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
1704 dev->name, lp->a.read_csr(ioaddr, 0));
1705 }
1706
1707 /* Default status -- will not enable Successful-TxDone
1708 * interrupt when that option is available to us.
1709 */
1710 status = 0x8300;
1711
1712 /* Fill in a Tx ring entry */
1713
1714 /* Mask to ring buffer boundary. */
1715 entry = lp->cur_tx & TX_RING_MOD_MASK;
1716
1717 /* Caution: the write order is important here, set the status
1718 * with the "ownership" bits last. */
1719
1720 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1721
1722 lp->tx_ring[entry].misc = 0x00000000;
1723
1724 lp->tx_skbuff[entry] = skb;
1725 lp->tx_dma_addr[entry] = pci_map_single(lp->pci_dev, skb->data, skb->len,
1726 PCI_DMA_TODEVICE);
1727 lp->tx_ring[entry].base = (u32)le32_to_cpu(lp->tx_dma_addr[entry]);
1728 wmb(); /* Make sure owner changes after all others are visible */
1729 lp->tx_ring[entry].status = le16_to_cpu(status);
1730
1731 lp->cur_tx++;
1732 lp->stats.tx_bytes += skb->len;
1733
1734 /* Trigger an immediate send poll. */
1735 lp->a.write_csr (ioaddr, 0, 0x0048);
1736
1737 dev->trans_start = jiffies;
1738
1739 if (lp->tx_ring[(entry+1) & TX_RING_MOD_MASK].base != 0) {
1740 lp->tx_full = 1;
1741 netif_stop_queue(dev);
1742 }
1743 spin_unlock_irqrestore(&lp->lock, flags);
1744 return 0;
1745 }
1746
1747 /* The PCNET32 interrupt handler. */
1748 static void
1749 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1750 {
1751 struct net_device *dev = dev_id;
1752 struct pcnet32_private *lp;
1753 unsigned long ioaddr;
1754 u16 csr0,rap;
1755 int boguscnt = max_interrupt_work;
1756 int must_restart;
1757
1758 if (!dev) {
1759 if (pcnet32_debug & NETIF_MSG_INTR)
1760 printk (KERN_DEBUG "%s(): irq %d for unknown device\n",
1761 __FUNCTION__, irq);
1762 return;
1763 }
1764
1765 ioaddr = dev->base_addr;
1766 lp = dev->priv;
1767
1768 spin_lock(&lp->lock);
1769
1770 rap = lp->a.read_rap(ioaddr);
1771 while ((csr0 = lp->a.read_csr (ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) {
1772 if (csr0 == 0xffff) {
1773 break; /* PCMCIA remove happened */
1774 }
1775 /* Acknowledge all of the current interrupt sources ASAP. */
1776 lp->a.write_csr (ioaddr, 0, csr0 & ~0x004f);
1777
1778 must_restart = 0;
1779
1780 if (netif_msg_intr(lp))
1781 printk(KERN_DEBUG "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
1782 dev->name, csr0, lp->a.read_csr (ioaddr, 0));
1783
1784 if (csr0 & 0x0400) /* Rx interrupt */
1785 pcnet32_rx(dev);
1786
1787 if (csr0 & 0x0200) { /* Tx-done interrupt */
1788 unsigned int dirty_tx = lp->dirty_tx;
1789 int delta;
1790
1791 while (dirty_tx != lp->cur_tx) {
1792 int entry = dirty_tx & TX_RING_MOD_MASK;
1793 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1794
1795 if (status < 0)
1796 break; /* It still hasn't been Txed */
1797
1798 lp->tx_ring[entry].base = 0;
1799
1800 if (status & 0x4000) {
1801 /* There was an major error, log it. */
1802 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1803 lp->stats.tx_errors++;
1804 if (netif_msg_tx_err(lp))
1805 printk(KERN_ERR "%s: Tx error status=%04x err_status=%08x\n",
1806 dev->name, status, err_status);
1807 if (err_status & 0x04000000) lp->stats.tx_aborted_errors++;
1808 if (err_status & 0x08000000) lp->stats.tx_carrier_errors++;
1809 if (err_status & 0x10000000) lp->stats.tx_window_errors++;
1810 #ifndef DO_DXSUFLO
1811 if (err_status & 0x40000000) {
1812 lp->stats.tx_fifo_errors++;
1813 /* Ackk! On FIFO errors the Tx unit is turned off! */
1814 /* Remove this verbosity later! */
1815 if (netif_msg_tx_err(lp))
1816 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1817 dev->name, csr0);
1818 must_restart = 1;
1819 }
1820 #else
1821 if (err_status & 0x40000000) {
1822 lp->stats.tx_fifo_errors++;
1823 if (! lp->dxsuflo) { /* If controller doesn't recover ... */
1824 /* Ackk! On FIFO errors the Tx unit is turned off! */
1825 /* Remove this verbosity later! */
1826 if (netif_msg_tx_err(lp))
1827 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1828 dev->name, csr0);
1829 must_restart = 1;
1830 }
1831 }
1832 #endif
1833 } else {
1834 if (status & 0x1800)
1835 lp->stats.collisions++;
1836 lp->stats.tx_packets++;
1837 }
1838
1839 /* We must free the original skb */
1840 if (lp->tx_skbuff[entry]) {
1841 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[entry],
1842 lp->tx_skbuff[entry]->len, PCI_DMA_TODEVICE);
1843 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
1844 lp->tx_skbuff[entry] = 0;
1845 lp->tx_dma_addr[entry] = 0;
1846 }
1847 dirty_tx++;
1848 }
1849
1850 delta = (lp->cur_tx - dirty_tx) & (TX_RING_MOD_MASK + TX_RING_SIZE);
1851 if (delta > TX_RING_SIZE) {
1852 if (netif_msg_drv(lp))
1853 printk(KERN_ERR "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1854 dev->name, dirty_tx, lp->cur_tx, lp->tx_full);
1855 dirty_tx += TX_RING_SIZE;
1856 delta -= TX_RING_SIZE;
1857 }
1858
1859 if (lp->tx_full &&
1860 netif_queue_stopped(dev) &&
1861 delta < TX_RING_SIZE - 2) {
1862 /* The ring is no longer full, clear tbusy. */
1863 lp->tx_full = 0;
1864 netif_wake_queue (dev);
1865 }
1866 lp->dirty_tx = dirty_tx;
1867 }
1868
1869 /* Log misc errors. */
1870 if (csr0 & 0x4000) lp->stats.tx_errors++; /* Tx babble. */
1871 if (csr0 & 0x1000) {
1872 /*
1873 * this happens when our receive ring is full. This shouldn't
1874 * be a problem as we will see normal rx interrupts for the frames
1875 * in the receive ring. But there are some PCI chipsets (I can
1876 * reproduce this on SP3G with Intel saturn chipset) which have
1877 * sometimes problems and will fill up the receive ring with
1878 * error descriptors. In this situation we don't get a rx
1879 * interrupt, but a missed frame interrupt sooner or later.
1880 * So we try to clean up our receive ring here.
1881 */
1882 pcnet32_rx(dev);
1883 lp->stats.rx_errors++; /* Missed a Rx frame. */
1884 }
1885 if (csr0 & 0x0800) {
1886 if (netif_msg_drv(lp))
1887 printk(KERN_ERR "%s: Bus master arbitration failure, status %4.4x.\n",
1888 dev->name, csr0);
1889 /* unlike for the lance, there is no restart needed */
1890 }
1891
1892 if (must_restart) {
1893 /* reset the chip to clear the error condition, then restart */
1894 lp->a.reset(ioaddr);
1895 lp->a.write_csr(ioaddr, 4, 0x0915);
1896 pcnet32_restart(dev, 0x0002);
1897 netif_wake_queue(dev);
1898 }
1899 }
1900
1901 /* Set interrupt enable. */
1902 lp->a.write_csr (ioaddr, 0, 0x0040);
1903 lp->a.write_rap (ioaddr,rap);
1904
1905 if (netif_msg_intr(lp))
1906 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
1907 dev->name, lp->a.read_csr (ioaddr, 0));
1908
1909 spin_unlock(&lp->lock);
1910 }
1911
1912 static int
1913 pcnet32_rx(struct net_device *dev)
1914 {
1915 struct pcnet32_private *lp = dev->priv;
1916 int entry = lp->cur_rx & RX_RING_MOD_MASK;
1917 int boguscnt = RX_RING_SIZE / 2;
1918
1919 /* If we own the next entry, it's a new packet. Send it up. */
1920 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
1921 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
1922
1923 if (status != 0x03) { /* There was an error. */
1924 /*
1925 * There is a tricky error noted by John Murphy,
1926 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1927 * buffers it's possible for a jabber packet to use two
1928 * buffers, with only the last correctly noting the error.
1929 */
1930 if (status & 0x01) /* Only count a general error at the */
1931 lp->stats.rx_errors++; /* end of a packet.*/
1932 if (status & 0x20) lp->stats.rx_frame_errors++;
1933 if (status & 0x10) lp->stats.rx_over_errors++;
1934 if (status & 0x08) lp->stats.rx_crc_errors++;
1935 if (status & 0x04) lp->stats.rx_fifo_errors++;
1936 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
1937 } else {
1938 /* Malloc up new buffer, compatible with net-2e. */
1939 short pkt_len = (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)-4;
1940 struct sk_buff *skb;
1941
1942 /* Discard oversize frames. */
1943 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
1944 if (netif_msg_drv(lp))
1945 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1946 dev->name, pkt_len);
1947 lp->stats.rx_errors++;
1948 } else if (pkt_len < 60) {
1949 if (netif_msg_rx_err(lp))
1950 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1951 lp->stats.rx_errors++;
1952 } else {
1953 int rx_in_place = 0;
1954
1955 if (pkt_len > rx_copybreak) {
1956 struct sk_buff *newskb;
1957
1958 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
1959 skb_reserve (newskb, 2);
1960 skb = lp->rx_skbuff[entry];
1961 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[entry],
1962 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
1963 skb_put (skb, pkt_len);
1964 lp->rx_skbuff[entry] = newskb;
1965 newskb->dev = dev;
1966 lp->rx_dma_addr[entry] =
1967 pci_map_single(lp->pci_dev, newskb->tail,
1968 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
1969 lp->rx_ring[entry].base = le32_to_cpu(lp->rx_dma_addr[entry]);
1970 rx_in_place = 1;
1971 } else
1972 skb = NULL;
1973 } else {
1974 skb = dev_alloc_skb(pkt_len+2);
1975 }
1976
1977 if (skb == NULL) {
1978 int i;
1979 if (netif_msg_drv(lp))
1980 printk(KERN_ERR "%s: Memory squeeze, deferring packet.\n",
1981 dev->name);
1982 for (i = 0; i < RX_RING_SIZE; i++)
1983 if ((short)le16_to_cpu(lp->rx_ring[(entry+i)
1984 & RX_RING_MOD_MASK].status) < 0)
1985 break;
1986
1987 if (i > RX_RING_SIZE -2) {
1988 lp->stats.rx_dropped++;
1989 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
1990 wmb(); /* Make sure adapter sees owner change */
1991 lp->cur_rx++;
1992 }
1993 break;
1994 }
1995 skb->dev = dev;
1996 if (!rx_in_place) {
1997 skb_reserve(skb,2); /* 16 byte align */
1998 skb_put(skb,pkt_len); /* Make room */
1999 pci_dma_sync_single(lp->pci_dev,
2000 lp->rx_dma_addr[entry],
2001 PKT_BUF_SZ-2,
2002 PCI_DMA_FROMDEVICE);
2003 eth_copy_and_sum(skb,
2004 (unsigned char *)(lp->rx_skbuff[entry]->tail),
2005 pkt_len,0);
2006 }
2007 lp->stats.rx_bytes += skb->len;
2008 skb->protocol=eth_type_trans(skb,dev);
2009 netif_rx(skb);
2010 dev->last_rx = jiffies;
2011 lp->stats.rx_packets++;
2012 }
2013 }
2014 /*
2015 * The docs say that the buffer length isn't touched, but Andrew Boyd
2016 * of QNX reports that some revs of the 79C965 clear it.
2017 */
2018 lp->rx_ring[entry].buf_length = le16_to_cpu(2-PKT_BUF_SZ);
2019 wmb(); /* Make sure owner changes after all others are visible */
2020 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
2021 entry = (++lp->cur_rx) & RX_RING_MOD_MASK;
2022 if (--boguscnt <= 0) break; /* don't stay in loop forever */
2023 }
2024
2025 return 0;
2026 }
2027
2028 static int
2029 pcnet32_close(struct net_device *dev)
2030 {
2031 unsigned long ioaddr = dev->base_addr;
2032 struct pcnet32_private *lp = dev->priv;
2033 int i;
2034 unsigned long flags;
2035
2036 del_timer_sync(&lp->watchdog_timer);
2037
2038 netif_stop_queue(dev);
2039
2040 spin_lock_irqsave(&lp->lock, flags);
2041
2042 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
2043
2044 if (netif_msg_ifdown(lp))
2045 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
2046 dev->name, lp->a.read_csr (ioaddr, 0));
2047
2048 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2049 lp->a.write_csr (ioaddr, 0, 0x0004);
2050
2051 /*
2052 * Switch back to 16bit mode to avoid problems with dumb
2053 * DOS packet driver after a warm reboot
2054 */
2055 lp->a.write_bcr (ioaddr, 20, 4);
2056
2057 spin_unlock_irqrestore(&lp->lock, flags);
2058
2059 free_irq(dev->irq, dev);
2060
2061 spin_lock_irqsave(&lp->lock, flags);
2062
2063 /* free all allocated skbuffs */
2064 for (i = 0; i < RX_RING_SIZE; i++) {
2065 lp->rx_ring[i].status = 0;
2066 wmb(); /* Make sure adapter sees owner change */
2067 if (lp->rx_skbuff[i]) {
2068 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2,
2069 PCI_DMA_FROMDEVICE);
2070 dev_kfree_skb(lp->rx_skbuff[i]);
2071 }
2072 lp->rx_skbuff[i] = NULL;
2073 lp->rx_dma_addr[i] = 0;
2074 }
2075
2076 for (i = 0; i < TX_RING_SIZE; i++) {
2077 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2078 wmb(); /* Make sure adapter sees owner change */
2079 if (lp->tx_skbuff[i]) {
2080 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2081 lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
2082 dev_kfree_skb(lp->tx_skbuff[i]);
2083 }
2084 lp->tx_skbuff[i] = NULL;
2085 lp->tx_dma_addr[i] = 0;
2086 }
2087
2088 spin_unlock_irqrestore(&lp->lock, flags);
2089
2090 return 0;
2091 }
2092
2093 static struct net_device_stats *
2094 pcnet32_get_stats(struct net_device *dev)
2095 {
2096 struct pcnet32_private *lp = dev->priv;
2097 unsigned long ioaddr = dev->base_addr;
2098 u16 saved_addr;
2099 unsigned long flags;
2100
2101 spin_lock_irqsave(&lp->lock, flags);
2102 saved_addr = lp->a.read_rap(ioaddr);
2103 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
2104 lp->a.write_rap(ioaddr, saved_addr);
2105 spin_unlock_irqrestore(&lp->lock, flags);
2106
2107 return &lp->stats;
2108 }
2109
2110 /* taken from the sunlance driver, which it took from the depca driver */
2111 static void pcnet32_load_multicast (struct net_device *dev)
2112 {
2113 struct pcnet32_private *lp = dev->priv;
2114 volatile struct pcnet32_init_block *ib = &lp->init_block;
2115 volatile u16 *mcast_table = (u16 *)&ib->filter;
2116 struct dev_mc_list *dmi=dev->mc_list;
2117 char *addrs;
2118 int i;
2119 u32 crc;
2120
2121 /* set all multicast bits */
2122 if (dev->flags & IFF_ALLMULTI) {
2123 ib->filter[0] = 0xffffffff;
2124 ib->filter[1] = 0xffffffff;
2125 return;
2126 }
2127 /* clear the multicast filter */
2128 ib->filter[0] = 0;
2129 ib->filter[1] = 0;
2130
2131 /* Add addresses */
2132 for (i = 0; i < dev->mc_count; i++) {
2133 addrs = dmi->dmi_addr;
2134 dmi = dmi->next;
2135
2136 /* multicast address? */
2137 if (!(*addrs & 1))
2138 continue;
2139
2140 crc = ether_crc_le(6, addrs);
2141 crc = crc >> 26;
2142 mcast_table [crc >> 4] = le16_to_cpu(
2143 le16_to_cpu(mcast_table [crc >> 4]) | (1 << (crc & 0xf)));
2144 }
2145 return;
2146 }
2147
2148
2149 /*
2150 * Set or clear the multicast filter for this adaptor.
2151 */
2152 static void pcnet32_set_multicast_list(struct net_device *dev)
2153 {
2154 unsigned long ioaddr = dev->base_addr, flags;
2155 struct pcnet32_private *lp = dev->priv;
2156
2157 spin_lock_irqsave(&lp->lock, flags);
2158 if (dev->flags&IFF_PROMISC) {
2159 /* Log any net taps. */
2160 if (netif_msg_hw(lp))
2161 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
2162 lp->init_block.mode = le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 7);
2163 } else {
2164 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2165 pcnet32_load_multicast (dev);
2166 }
2167
2168 lp->a.write_csr (ioaddr, 0, 0x0004); /* Temporarily stop the lance. */
2169 pcnet32_restart(dev, 0x0042); /* Resume normal operation */
2170 netif_wake_queue(dev);
2171
2172 spin_unlock_irqrestore(&lp->lock, flags);
2173 }
2174
2175 /* This routine assumes that the lp->lock is held */
2176 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2177 {
2178 struct pcnet32_private *lp = dev->priv;
2179 unsigned long ioaddr = dev->base_addr;
2180 u16 val_out;
2181
2182 if (!lp->mii)
2183 return 0;
2184
2185 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2186 val_out = lp->a.read_bcr(ioaddr, 34);
2187
2188 return val_out;
2189 }
2190
2191 /* This routine assumes that the lp->lock is held */
2192 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2193 {
2194 struct pcnet32_private *lp = dev->priv;
2195 unsigned long ioaddr = dev->base_addr;
2196
2197 if (!lp->mii)
2198 return;
2199
2200 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2201 lp->a.write_bcr(ioaddr, 34, val);
2202 }
2203
2204 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2205 {
2206 struct pcnet32_private *lp = dev->priv;
2207 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
2208 int rc;
2209 unsigned long flags;
2210
2211 /* SIOC[GS]MIIxxx ioctls */
2212 if (lp->mii) {
2213 spin_lock_irqsave(&lp->lock, flags);
2214 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
2215 spin_unlock_irqrestore(&lp->lock, flags);
2216 } else {
2217 rc = -EOPNOTSUPP;
2218 }
2219
2220 return rc;
2221 }
2222
2223 static void pcnet32_watchdog(struct net_device *dev)
2224 {
2225 struct pcnet32_private *lp = dev->priv;
2226 unsigned long flags;
2227
2228 /* Print the link status if it has changed */
2229 if (lp->mii) {
2230 spin_lock_irqsave(&lp->lock, flags);
2231 mii_check_media (&lp->mii_if, netif_msg_link(lp), 0);
2232 spin_unlock_irqrestore(&lp->lock, flags);
2233 }
2234
2235 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2236 }
2237
2238 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2239 {
2240 struct net_device *dev = pci_get_drvdata(pdev);
2241
2242 if (dev) {
2243 struct pcnet32_private *lp = dev->priv;
2244
2245 unregister_netdev(dev);
2246 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2247 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2248 free_netdev(dev);
2249 pci_disable_device(pdev);
2250 pci_set_drvdata(pdev, NULL);
2251 }
2252 }
2253
2254 static struct pci_driver pcnet32_driver = {
2255 .name = DRV_NAME,
2256 .probe = pcnet32_probe_pci,
2257 .remove = __devexit_p(pcnet32_remove_one),
2258 .id_table = pcnet32_pci_tbl,
2259 };
2260
2261 MODULE_PARM(debug, "i");
2262 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2263 MODULE_PARM(max_interrupt_work, "i");
2264 MODULE_PARM_DESC(max_interrupt_work, DRV_NAME " maximum events handled per interrupt");
2265 MODULE_PARM(rx_copybreak, "i");
2266 MODULE_PARM_DESC(rx_copybreak, DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2267 MODULE_PARM(tx_start_pt, "i");
2268 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2269 MODULE_PARM(pcnet32vlb, "i");
2270 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2271 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
2272 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2273 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
2274 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2275 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2276 MODULE_PARM(homepna,"1-" __MODULE_STRING(MAX_UNITS) "i");
2277 MODULE_PARM_DESC(homepna, DRV_NAME " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2278
2279 MODULE_AUTHOR("Thomas Bogendoerfer");
2280 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2281 MODULE_LICENSE("GPL");
2282
2283 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2284
2285 /* An additional parameter that may be passed in... */
2286 static int debug = -1;
2287 static int tx_start_pt = -1;
2288 static int pcnet32_have_pci;
2289
2290 static int __init pcnet32_init_module(void)
2291 {
2292 printk(KERN_INFO "%s", version);
2293
2294 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2295
2296 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2297 tx_start = tx_start_pt;
2298
2299 /* find the PCI devices */
2300 if (!pci_module_init(&pcnet32_driver))
2301 pcnet32_have_pci = 1;
2302
2303 /* should we find any remaining VLbus devices ? */
2304 if (pcnet32vlb)
2305 pcnet32_probe_vlbus();
2306
2307 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2308 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
2309
2310 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2311 }
2312
2313 static void __exit pcnet32_cleanup_module(void)
2314 {
2315 struct net_device *next_dev;
2316
2317 while (pcnet32_dev) {
2318 struct pcnet32_private *lp = pcnet32_dev->priv;
2319 next_dev = lp->next;
2320 unregister_netdev(pcnet32_dev);
2321 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2322 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2323 free_netdev(pcnet32_dev);
2324 pcnet32_dev = next_dev;
2325 }
2326
2327 if (pcnet32_have_pci)
2328 pci_unregister_driver(&pcnet32_driver);
2329 }
2330
2331 module_init(pcnet32_init_module);
2332 module_exit(pcnet32_cleanup_module);
2333
2334 /*
2335 * Local variables:
2336 * c-indent-level: 4
2337 * tab-width: 8
2338 * End:
2339 */
2340