1 /*
2
3 drivers/net/pci-skeleton.c
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6
7 Original code came from 8139too.c, which in turns was based
8 originally on Donald Becker's rtl8139.c driver, versions 1.11
9 and older. This driver was originally based on rtl8139.c
10 version 1.07. Header of rtl8139.c version 1.11:
11
12 -----<snip>-----
13
14 Written 1997-2000 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41
42 -----------------------------------------------------------------------------
43
44 Theory of Operation
45
46 I. Board Compatibility
47
48 This device driver is designed for the RealTek RTL8139 series, the RealTek
49 Fast Ethernet controllers for PCI and CardBus. This chip is used on many
50 low-end boards, sometimes with its markings changed.
51
52
53 II. Board-specific settings
54
55 PCI bus devices are configured by the system at boot time, so no jumpers
56 need to be set on the board. The system BIOS will assign the
57 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
58
59 III. Driver operation
60
61 IIIa. Rx Ring buffers
62
63 The receive unit uses a single linear ring buffer rather than the more
64 common (and more efficient) descriptor-based architecture. Incoming frames
65 are sequentially stored into the Rx region, and the host copies them into
66 skbuffs.
67
68 Comment: While it is theoretically possible to process many frames in place,
69 any delay in Rx processing would cause us to drop frames. More importantly,
70 the Linux protocol stack is not designed to operate in this manner.
71
72 IIIb. Tx operation
73
74 The RTL8139 uses a fixed set of four Tx descriptors in register space.
75 In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
76 aligns the IP header on word boundaries, and 14 byte ethernet header means
77 that almost all frames will need to be copied to an alignment buffer.
78
79 IVb. References
80
81 http://www.realtek.com.tw/cn/cn.html
82 http://www.scyld.com/expert/NWay.html
83
84 IVc. Errata
85
86 */
87
88 #include <linux/config.h>
89 #include <linux/module.h>
90 #include <linux/kernel.h>
91 #include <linux/pci.h>
92 #include <linux/init.h>
93 #include <linux/ioport.h>
94 #include <linux/netdevice.h>
95 #include <linux/etherdevice.h>
96 #include <linux/delay.h>
97 #include <linux/ethtool.h>
98 #include <linux/mii.h>
99 #include <linux/crc32.h>
100 #include <asm/io.h>
101
102 #define NETDRV_VERSION "1.0.0"
103 #define MODNAME "netdrv"
104 #define NETDRV_DRIVER_LOAD_MSG "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
105 #define PFX MODNAME ": "
106
107 static char version[] __devinitdata =
108 KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
109 KERN_INFO " Support available from http://foo.com/bar/baz.html\n";
110
111 /* define to 1 to enable PIO instead of MMIO */
112 #undef USE_IO_OPS
113
114 /* define to 1 to enable copious debugging info */
115 #undef NETDRV_DEBUG
116
117 /* define to 1 to disable lightweight runtime debugging checks */
118 #undef NETDRV_NDEBUG
119
120
121 #ifdef NETDRV_DEBUG
122 /* note: prints function name for you */
123 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
124 #else
125 # define DPRINTK(fmt, args...)
126 #endif
127
128 #ifdef NETDRV_NDEBUG
129 # define assert(expr) do {} while (0)
130 #else
131 # define assert(expr) \
132 if(!(expr)) { \
133 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
134 #expr,__FILE__,__FUNCTION__,__LINE__); \
135 }
136 #endif
137
138
139 /* A few user-configurable values. */
140 /* media options */
141 static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
142
143 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
144 static int max_interrupt_work = 20;
145
146 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
147 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
148 static int multicast_filter_limit = 32;
149
150 /* Size of the in-memory receive ring. */
151 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
152 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
153 #define RX_BUF_PAD 16
154 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
155 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
156
157 /* Number of Tx descriptor registers. */
158 #define NUM_TX_DESC 4
159
160 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
161 #define MAX_ETH_FRAME_SIZE 1536
162
163 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
164 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
165 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
166
167 /* PCI Tuning Parameters
168 Threshold is bytes transferred to chip before transmission starts. */
169 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
170
171 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
172 #define RX_FIFO_THRESH 6 /* Rx buffer level before first PCI xfer. */
173 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
174 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
175
176
177 /* Operational parameters that usually are not changed. */
178 /* Time in jiffies before concluding the transmitter is hung. */
179 #define TX_TIMEOUT (6*HZ)
180
181
182 enum {
183 HAS_CHIP_XCVR = 0x020000,
184 HAS_LNK_CHNG = 0x040000,
185 };
186
187 #define NETDRV_MIN_IO_SIZE 0x80
188 #define RTL8139B_IO_SIZE 256
189
190 #define NETDRV_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
191
192 typedef enum {
193 RTL8139 = 0,
194 NETDRV_CB,
195 SMC1211TX,
196 /*MPX5030,*/
197 DELTA8139,
198 ADDTRON8139,
199 } board_t;
200
201
202 /* indexed by board_t, above */
203 static struct {
204 const char *name;
205 } board_info[] __devinitdata = {
206 { "RealTek RTL8139 Fast Ethernet" },
207 { "RealTek RTL8139B PCI/CardBus" },
208 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
209 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
210 { "Delta Electronics 8139 10/100BaseTX" },
211 { "Addtron Technolgy 8139 10/100BaseTX" },
212 };
213
214
215 static struct pci_device_id netdrv_pci_tbl[] __devinitdata = {
216 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
217 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
218 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
219 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
220 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
221 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
222 {0,}
223 };
224 MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
225
226
227 /* The rest of these values should never change. */
228
229 /* Symbolic offsets to registers. */
230 enum NETDRV_registers {
231 MAC0 = 0, /* Ethernet hardware address. */
232 MAR0 = 8, /* Multicast filter. */
233 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
234 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
235 RxBuf = 0x30,
236 RxEarlyCnt = 0x34,
237 RxEarlyStatus = 0x36,
238 ChipCmd = 0x37,
239 RxBufPtr = 0x38,
240 RxBufAddr = 0x3A,
241 IntrMask = 0x3C,
242 IntrStatus = 0x3E,
243 TxConfig = 0x40,
244 ChipVersion = 0x43,
245 RxConfig = 0x44,
246 Timer = 0x48, /* A general-purpose counter. */
247 RxMissed = 0x4C, /* 24 bits valid, write clears. */
248 Cfg9346 = 0x50,
249 Config0 = 0x51,
250 Config1 = 0x52,
251 FlashReg = 0x54,
252 MediaStatus = 0x58,
253 Config3 = 0x59,
254 Config4 = 0x5A, /* absent on RTL-8139A */
255 HltClk = 0x5B,
256 MultiIntr = 0x5C,
257 TxSummary = 0x60,
258 BasicModeCtrl = 0x62,
259 BasicModeStatus = 0x64,
260 NWayAdvert = 0x66,
261 NWayLPAR = 0x68,
262 NWayExpansion = 0x6A,
263 /* Undocumented registers, but required for proper operation. */
264 FIFOTMS = 0x70, /* FIFO Control and test. */
265 CSCR = 0x74, /* Chip Status and Configuration Register. */
266 PARA78 = 0x78,
267 PARA7c = 0x7c, /* Magic transceiver parameter register. */
268 Config5 = 0xD8, /* absent on RTL-8139A */
269 };
270
271 enum ClearBitMasks {
272 MultiIntrClear = 0xF000,
273 ChipCmdClear = 0xE2,
274 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
275 };
276
277 enum ChipCmdBits {
278 CmdReset = 0x10,
279 CmdRxEnb = 0x08,
280 CmdTxEnb = 0x04,
281 RxBufEmpty = 0x01,
282 };
283
284 /* Interrupt register bits, using my own meaningful names. */
285 enum IntrStatusBits {
286 PCIErr = 0x8000,
287 PCSTimeout = 0x4000,
288 RxFIFOOver = 0x40,
289 RxUnderrun = 0x20,
290 RxOverflow = 0x10,
291 TxErr = 0x08,
292 TxOK = 0x04,
293 RxErr = 0x02,
294 RxOK = 0x01,
295 };
296 enum TxStatusBits {
297 TxHostOwns = 0x2000,
298 TxUnderrun = 0x4000,
299 TxStatOK = 0x8000,
300 TxOutOfWindow = 0x20000000,
301 TxAborted = 0x40000000,
302 TxCarrierLost = 0x80000000,
303 };
304 enum RxStatusBits {
305 RxMulticast = 0x8000,
306 RxPhysical = 0x4000,
307 RxBroadcast = 0x2000,
308 RxBadSymbol = 0x0020,
309 RxRunt = 0x0010,
310 RxTooLong = 0x0008,
311 RxCRCErr = 0x0004,
312 RxBadAlign = 0x0002,
313 RxStatusOK = 0x0001,
314 };
315
316 /* Bits in RxConfig. */
317 enum rx_mode_bits {
318 AcceptErr = 0x20,
319 AcceptRunt = 0x10,
320 AcceptBroadcast = 0x08,
321 AcceptMulticast = 0x04,
322 AcceptMyPhys = 0x02,
323 AcceptAllPhys = 0x01,
324 };
325
326 /* Bits in TxConfig. */
327 enum tx_config_bits {
328 TxIFG1 = (1 << 25), /* Interframe Gap Time */
329 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
330 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
331 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
332 TxClearAbt = (1 << 0), /* Clear abort (WO) */
333 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
334
335 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
336 };
337
338 /* Bits in Config1 */
339 enum Config1Bits {
340 Cfg1_PM_Enable = 0x01,
341 Cfg1_VPD_Enable = 0x02,
342 Cfg1_PIO = 0x04,
343 Cfg1_MMIO = 0x08,
344 Cfg1_LWAKE = 0x10,
345 Cfg1_Driver_Load = 0x20,
346 Cfg1_LED0 = 0x40,
347 Cfg1_LED1 = 0x80,
348 };
349
350 enum RxConfigBits {
351 /* Early Rx threshold, none or X/16 */
352 RxCfgEarlyRxNone = 0,
353 RxCfgEarlyRxShift = 24,
354
355 /* rx fifo threshold */
356 RxCfgFIFOShift = 13,
357 RxCfgFIFONone = (7 << RxCfgFIFOShift),
358
359 /* Max DMA burst */
360 RxCfgDMAShift = 8,
361 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
362
363 /* rx ring buffer length */
364 RxCfgRcv8K = 0,
365 RxCfgRcv16K = (1 << 11),
366 RxCfgRcv32K = (1 << 12),
367 RxCfgRcv64K = (1 << 11) | (1 << 12),
368
369 /* Disable packet wrap at end of Rx buffer */
370 RxNoWrap = (1 << 7),
371 };
372
373
374 /* Twister tuning parameters from RealTek.
375 Completely undocumented, but required to tune bad links. */
376 enum CSCRBits {
377 CSCR_LinkOKBit = 0x0400,
378 CSCR_LinkChangeBit = 0x0800,
379 CSCR_LinkStatusBits = 0x0f000,
380 CSCR_LinkDownOffCmd = 0x003c0,
381 CSCR_LinkDownCmd = 0x0f3c0,
382 };
383
384
385 enum Cfg9346Bits {
386 Cfg9346_Lock = 0x00,
387 Cfg9346_Unlock = 0xC0,
388 };
389
390
391 #define PARA78_default 0x78fa8388
392 #define PARA7c_default 0xcb38de43 /* param[0][3] */
393 #define PARA7c_xxx 0xcb38de43
394 static const unsigned long param[4][4] = {
395 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
396 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
397 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
398 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
399 };
400
401 struct ring_info {
402 struct sk_buff *skb;
403 dma_addr_t mapping;
404 };
405
406
407 typedef enum {
408 CH_8139 = 0,
409 CH_8139_K,
410 CH_8139A,
411 CH_8139B,
412 CH_8130,
413 CH_8139C,
414 } chip_t;
415
416
417 /* directly indexed by chip_t, above */
418 const static struct {
419 const char *name;
420 u8 version; /* from RTL8139C docs */
421 u32 RxConfigMask; /* should clear the bits supported by this chip */
422 } rtl_chip_info[] = {
423 { "RTL-8139",
424 0x40,
425 0xf0fe0040, /* XXX copied from RTL8139A, verify */
426 },
427
428 { "RTL-8139 rev K",
429 0x60,
430 0xf0fe0040,
431 },
432
433 { "RTL-8139A",
434 0x70,
435 0xf0fe0040,
436 },
437
438 { "RTL-8139B",
439 0x78,
440 0xf0fc0040
441 },
442
443 { "RTL-8130",
444 0x7C,
445 0xf0fe0040, /* XXX copied from RTL8139A, verify */
446 },
447
448 { "RTL-8139C",
449 0x74,
450 0xf0fc0040, /* XXX copied from RTL8139B, verify */
451 },
452
453 };
454
455
456 struct netdrv_private {
457 board_t board;
458 void *mmio_addr;
459 int drv_flags;
460 struct pci_dev *pci_dev;
461 struct net_device_stats stats;
462 struct timer_list timer; /* Media selection timer. */
463 unsigned char *rx_ring;
464 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
465 unsigned int tx_flag;
466 atomic_t cur_tx;
467 atomic_t dirty_tx;
468 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
469 struct ring_info tx_info[NUM_TX_DESC];
470 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
471 unsigned char *tx_bufs; /* Tx bounce buffer region. */
472 dma_addr_t rx_ring_dma;
473 dma_addr_t tx_bufs_dma;
474 char phys[4]; /* MII device addresses. */
475 char twistie, twist_row, twist_col; /* Twister tune state. */
476 unsigned int full_duplex:1; /* Full-duplex operation requested. */
477 unsigned int duplex_lock:1;
478 unsigned int default_port:4; /* Last dev->if_port value. */
479 unsigned int media2:4; /* Secondary monitored media port. */
480 unsigned int medialock:1; /* Don't sense media type. */
481 unsigned int mediasense:1; /* Media sensing in progress. */
482 spinlock_t lock;
483 chip_t chipset;
484 };
485
486 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
487 MODULE_DESCRIPTION ("Skeleton for a PCI Fast Ethernet driver");
488 MODULE_LICENSE("GPL");
489 MODULE_PARM (multicast_filter_limit, "i");
490 MODULE_PARM (max_interrupt_work, "i");
491 MODULE_PARM (debug, "i");
492 MODULE_PARM (media, "1-" __MODULE_STRING(8) "i");
493 MODULE_PARM_DESC (multicast_filter_limit, "pci-skeleton maximum number of filtered multicast addresses");
494 MODULE_PARM_DESC (max_interrupt_work, "pci-skeleton maximum events handled per interrupt");
495 MODULE_PARM_DESC (media, "pci-skeleton: Bits 0-3: media type, bit 17: full duplex");
496 MODULE_PARM_DESC (debug, "(unused)");
497
498 static int read_eeprom (void *ioaddr, int location, int addr_len);
499 static int netdrv_open (struct net_device *dev);
500 static int mdio_read (struct net_device *dev, int phy_id, int location);
501 static void mdio_write (struct net_device *dev, int phy_id, int location,
502 int val);
503 static void netdrv_timer (unsigned long data);
504 static void netdrv_tx_timeout (struct net_device *dev);
505 static void netdrv_init_ring (struct net_device *dev);
506 static int netdrv_start_xmit (struct sk_buff *skb,
507 struct net_device *dev);
508 static void netdrv_interrupt (int irq, void *dev_instance,
509 struct pt_regs *regs);
510 static int netdrv_close (struct net_device *dev);
511 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
512 static struct net_device_stats *netdrv_get_stats (struct net_device *dev);
513 static void netdrv_set_rx_mode (struct net_device *dev);
514 static void netdrv_hw_start (struct net_device *dev);
515
516
517 #ifdef USE_IO_OPS
518
519 #define NETDRV_R8(reg) inb (((unsigned long)ioaddr) + (reg))
520 #define NETDRV_R16(reg) inw (((unsigned long)ioaddr) + (reg))
521 #define NETDRV_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
522 #define NETDRV_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
523 #define NETDRV_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
524 #define NETDRV_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
525 #define NETDRV_W8_F NETDRV_W8
526 #define NETDRV_W16_F NETDRV_W16
527 #define NETDRV_W32_F NETDRV_W32
528 #undef readb
529 #undef readw
530 #undef readl
531 #undef writeb
532 #undef writew
533 #undef writel
534 #define readb(addr) inb((unsigned long)(addr))
535 #define readw(addr) inw((unsigned long)(addr))
536 #define readl(addr) inl((unsigned long)(addr))
537 #define writeb(val,addr) outb((val),(unsigned long)(addr))
538 #define writew(val,addr) outw((val),(unsigned long)(addr))
539 #define writel(val,addr) outl((val),(unsigned long)(addr))
540
541 #else
542
543 /* write MMIO register, with flush */
544 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
545 #define NETDRV_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
546 #define NETDRV_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
547 #define NETDRV_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
548
549
550 #if MMIO_FLUSH_AUDIT_COMPLETE
551
552 /* write MMIO register */
553 #define NETDRV_W8(reg, val8) writeb ((val8), ioaddr + (reg))
554 #define NETDRV_W16(reg, val16) writew ((val16), ioaddr + (reg))
555 #define NETDRV_W32(reg, val32) writel ((val32), ioaddr + (reg))
556
557 #else
558
559 /* write MMIO register, then flush */
560 #define NETDRV_W8 NETDRV_W8_F
561 #define NETDRV_W16 NETDRV_W16_F
562 #define NETDRV_W32 NETDRV_W32_F
563
564 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
565
566 /* read MMIO register */
567 #define NETDRV_R8(reg) readb (ioaddr + (reg))
568 #define NETDRV_R16(reg) readw (ioaddr + (reg))
569 #define NETDRV_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
570
571 #endif /* USE_IO_OPS */
572
573
574 static const u16 netdrv_intr_mask =
575 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
576 TxErr | TxOK | RxErr | RxOK;
577
578 static const unsigned int netdrv_rx_config =
579 RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
580 (RX_FIFO_THRESH << RxCfgFIFOShift) |
581 (RX_DMA_BURST << RxCfgDMAShift);
582
583
netdrv_init_board(struct pci_dev * pdev,struct net_device ** dev_out,void ** ioaddr_out)584 static int __devinit netdrv_init_board (struct pci_dev *pdev,
585 struct net_device **dev_out,
586 void **ioaddr_out)
587 {
588 void *ioaddr = NULL;
589 struct net_device *dev;
590 struct netdrv_private *tp;
591 u8 tmp8;
592 int rc, i;
593 u32 pio_start, pio_end, pio_flags, pio_len;
594 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
595 u32 tmp;
596
597 DPRINTK ("ENTER\n");
598
599 assert (pdev != NULL);
600 assert (ioaddr_out != NULL);
601
602 *ioaddr_out = NULL;
603 *dev_out = NULL;
604
605 /* dev zeroed in alloc_etherdev */
606 dev = alloc_etherdev (sizeof (*tp));
607 if (dev == NULL) {
608 printk (KERN_ERR PFX "unable to alloc new ethernet\n");
609 DPRINTK ("EXIT, returning -ENOMEM\n");
610 return -ENOMEM;
611 }
612 SET_MODULE_OWNER(dev);
613 tp = dev->priv;
614
615 /* enable device (incl. PCI PM wakeup), and bus-mastering */
616 rc = pci_enable_device (pdev);
617 if (rc)
618 goto err_out;
619
620 pio_start = pci_resource_start (pdev, 0);
621 pio_end = pci_resource_end (pdev, 0);
622 pio_flags = pci_resource_flags (pdev, 0);
623 pio_len = pci_resource_len (pdev, 0);
624
625 mmio_start = pci_resource_start (pdev, 1);
626 mmio_end = pci_resource_end (pdev, 1);
627 mmio_flags = pci_resource_flags (pdev, 1);
628 mmio_len = pci_resource_len (pdev, 1);
629
630 /* set this immediately, we need to know before
631 * we talk to the chip directly */
632 DPRINTK("PIO region size == 0x%02X\n", pio_len);
633 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
634
635 /* make sure PCI base addr 0 is PIO */
636 if (!(pio_flags & IORESOURCE_IO)) {
637 printk (KERN_ERR PFX "region #0 not a PIO resource, aborting\n");
638 rc = -ENODEV;
639 goto err_out;
640 }
641
642 /* make sure PCI base addr 1 is MMIO */
643 if (!(mmio_flags & IORESOURCE_MEM)) {
644 printk (KERN_ERR PFX "region #1 not an MMIO resource, aborting\n");
645 rc = -ENODEV;
646 goto err_out;
647 }
648
649 /* check for weird/broken PCI region reporting */
650 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
651 (mmio_len < NETDRV_MIN_IO_SIZE)) {
652 printk (KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
653 rc = -ENODEV;
654 goto err_out;
655 }
656
657 rc = pci_request_regions (pdev, "pci-skeleton");
658 if (rc)
659 goto err_out;
660
661 pci_set_master (pdev);
662
663 #ifdef USE_IO_OPS
664 ioaddr = (void *) pio_start;
665 #else
666 /* ioremap MMIO region */
667 ioaddr = ioremap (mmio_start, mmio_len);
668 if (ioaddr == NULL) {
669 printk (KERN_ERR PFX "cannot remap MMIO, aborting\n");
670 rc = -EIO;
671 goto err_out_free_res;
672 }
673 #endif /* USE_IO_OPS */
674
675 /* Soft reset the chip. */
676 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
677
678 /* Check that the chip has finished the reset. */
679 for (i = 1000; i > 0; i--)
680 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
681 break;
682 else
683 udelay (10);
684
685 /* Bring the chip out of low-power mode. */
686 /* <insert device-specific code here> */
687
688 #ifndef USE_IO_OPS
689 /* sanity checks -- ensure PIO and MMIO registers agree */
690 assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
691 assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
692 assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
693 assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
694 #endif /* !USE_IO_OPS */
695
696 /* identify chip attached to board */
697 tmp = NETDRV_R8 (ChipVersion);
698 for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
699 if (tmp == rtl_chip_info[i].version) {
700 tp->chipset = i;
701 goto match;
702 }
703
704 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
705 printk (KERN_DEBUG PFX "PCI device %s: unknown chip version, assuming RTL-8139\n",
706 pdev->slot_name);
707 printk (KERN_DEBUG PFX "PCI device %s: TxConfig = 0x%lx\n", pdev->slot_name, NETDRV_R32 (TxConfig));
708 tp->chipset = 0;
709
710 match:
711 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
712 tmp,
713 tp->chipset,
714 rtl_chip_info[tp->chipset].name);
715
716 i = register_netdev (dev);
717 if (i)
718 goto err_out_unmap;
719
720 DPRINTK ("EXIT, returning 0\n");
721 *ioaddr_out = ioaddr;
722 *dev_out = dev;
723 return 0;
724
725 err_out_unmap:
726 #ifndef USE_IO_OPS
727 iounmap(ioaddr);
728 err_out_free_res:
729 #endif
730 pci_release_regions (pdev);
731 err_out:
732 kfree (dev);
733 DPRINTK ("EXIT, returning %d\n", rc);
734 return rc;
735 }
736
737
netdrv_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)738 static int __devinit netdrv_init_one (struct pci_dev *pdev,
739 const struct pci_device_id *ent)
740 {
741 struct net_device *dev = NULL;
742 struct netdrv_private *tp;
743 int i, addr_len, option;
744 void *ioaddr = NULL;
745 static int board_idx = -1;
746 u8 tmp;
747
748 /* when built into the kernel, we only print version if device is found */
749 #ifndef MODULE
750 static int printed_version;
751 if (!printed_version++)
752 printk(version);
753 #endif
754
755 DPRINTK ("ENTER\n");
756
757 assert (pdev != NULL);
758 assert (ent != NULL);
759
760 board_idx++;
761
762 i = netdrv_init_board (pdev, &dev, &ioaddr);
763 if (i < 0) {
764 DPRINTK ("EXIT, returning %d\n", i);
765 return i;
766 }
767
768 tp = dev->priv;
769
770 assert (ioaddr != NULL);
771 assert (dev != NULL);
772 assert (tp != NULL);
773
774 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
775 for (i = 0; i < 3; i++)
776 ((u16 *) (dev->dev_addr))[i] =
777 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
778
779 /* The Rtl8139-specific entries in the device structure. */
780 dev->open = netdrv_open;
781 dev->hard_start_xmit = netdrv_start_xmit;
782 dev->stop = netdrv_close;
783 dev->get_stats = netdrv_get_stats;
784 dev->set_multicast_list = netdrv_set_rx_mode;
785 dev->do_ioctl = netdrv_ioctl;
786 dev->tx_timeout = netdrv_tx_timeout;
787 dev->watchdog_timeo = TX_TIMEOUT;
788
789 dev->irq = pdev->irq;
790 dev->base_addr = (unsigned long) ioaddr;
791
792 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
793 tp = dev->priv;
794
795 /* note: tp->chipset set in netdrv_init_board */
796 tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
797 PCI_COMMAND_MASTER | NETDRV_CAPS;
798 tp->pci_dev = pdev;
799 tp->board = ent->driver_data;
800 tp->mmio_addr = ioaddr;
801 tp->lock = SPIN_LOCK_UNLOCKED;
802
803 pci_set_drvdata(pdev, dev);
804
805 tp->phys[0] = 32;
806
807 printk (KERN_INFO "%s: %s at 0x%lx, "
808 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
809 "IRQ %d\n",
810 dev->name,
811 board_info[ent->driver_data].name,
812 dev->base_addr,
813 dev->dev_addr[0], dev->dev_addr[1],
814 dev->dev_addr[2], dev->dev_addr[3],
815 dev->dev_addr[4], dev->dev_addr[5],
816 dev->irq);
817
818 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
819 dev->name, rtl_chip_info[tp->chipset].name);
820
821 /* Put the chip into low-power mode. */
822 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
823
824 /* The lower four bits are the media type. */
825 option = (board_idx > 7) ? 0 : media[board_idx];
826 if (option > 0) {
827 tp->full_duplex = (option & 0x200) ? 1 : 0;
828 tp->default_port = option & 15;
829 if (tp->default_port)
830 tp->medialock = 1;
831 }
832
833 if (tp->full_duplex) {
834 printk (KERN_INFO
835 "%s: Media type forced to Full Duplex.\n",
836 dev->name);
837 mdio_write (dev, tp->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
838 tp->duplex_lock = 1;
839 }
840
841 DPRINTK ("EXIT - returning 0\n");
842 return 0;
843 }
844
845
netdrv_remove_one(struct pci_dev * pdev)846 static void __devexit netdrv_remove_one (struct pci_dev *pdev)
847 {
848 struct net_device *dev = pci_get_drvdata (pdev);
849 struct netdrv_private *np;
850
851 DPRINTK ("ENTER\n");
852
853 assert (dev != NULL);
854
855 np = dev->priv;
856 assert (np != NULL);
857
858 unregister_netdev (dev);
859
860 #ifndef USE_IO_OPS
861 iounmap (np->mmio_addr);
862 #endif /* !USE_IO_OPS */
863
864 pci_release_regions (pdev);
865
866 #ifndef NETDRV_NDEBUG
867 /* poison memory before freeing */
868 memset (dev, 0xBC,
869 sizeof (struct net_device) +
870 sizeof (struct netdrv_private));
871 #endif /* NETDRV_NDEBUG */
872
873 kfree (dev);
874
875 pci_set_drvdata (pdev, NULL);
876
877 pci_power_off (pdev, -1);
878
879 DPRINTK ("EXIT\n");
880 }
881
882
883 /* Serial EEPROM section. */
884
885 /* EEPROM_Ctrl bits. */
886 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
887 #define EE_CS 0x08 /* EEPROM chip select. */
888 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
889 #define EE_WRITE_0 0x00
890 #define EE_WRITE_1 0x02
891 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
892 #define EE_ENB (0x80 | EE_CS)
893
894 /* Delay between EEPROM clock transitions.
895 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
896 */
897
898 #define eeprom_delay() readl(ee_addr)
899
900 /* The EEPROM commands include the alway-set leading bit. */
901 #define EE_WRITE_CMD (5)
902 #define EE_READ_CMD (6)
903 #define EE_ERASE_CMD (7)
904
read_eeprom(void * ioaddr,int location,int addr_len)905 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
906 {
907 int i;
908 unsigned retval = 0;
909 void *ee_addr = ioaddr + Cfg9346;
910 int read_cmd = location | (EE_READ_CMD << addr_len);
911
912 DPRINTK ("ENTER\n");
913
914 writeb (EE_ENB & ~EE_CS, ee_addr);
915 writeb (EE_ENB, ee_addr);
916 eeprom_delay ();
917
918 /* Shift the read command bits out. */
919 for (i = 4 + addr_len; i >= 0; i--) {
920 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
921 writeb (EE_ENB | dataval, ee_addr);
922 eeprom_delay ();
923 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
924 eeprom_delay ();
925 }
926 writeb (EE_ENB, ee_addr);
927 eeprom_delay ();
928
929 for (i = 16; i > 0; i--) {
930 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
931 eeprom_delay ();
932 retval =
933 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
934 0);
935 writeb (EE_ENB, ee_addr);
936 eeprom_delay ();
937 }
938
939 /* Terminate the EEPROM access. */
940 writeb (~EE_CS, ee_addr);
941 eeprom_delay ();
942
943 DPRINTK ("EXIT - returning %d\n", retval);
944 return retval;
945 }
946
947 /* MII serial management: mostly bogus for now. */
948 /* Read and write the MII management registers using software-generated
949 serial MDIO protocol.
950 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
951 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
952 "overclocking" issues. */
953 #define MDIO_DIR 0x80
954 #define MDIO_DATA_OUT 0x04
955 #define MDIO_DATA_IN 0x02
956 #define MDIO_CLK 0x01
957 #define MDIO_WRITE0 (MDIO_DIR)
958 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
959
960 #define mdio_delay() readb(mdio_addr)
961
962
963 static char mii_2_8139_map[8] = {
964 BasicModeCtrl,
965 BasicModeStatus,
966 0,
967 0,
968 NWayAdvert,
969 NWayLPAR,
970 NWayExpansion,
971 0
972 };
973
974
975 /* Syncronize the MII management interface by shifting 32 one bits out. */
mdio_sync(void * mdio_addr)976 static void mdio_sync (void *mdio_addr)
977 {
978 int i;
979
980 DPRINTK ("ENTER\n");
981
982 for (i = 32; i >= 0; i--) {
983 writeb (MDIO_WRITE1, mdio_addr);
984 mdio_delay ();
985 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
986 mdio_delay ();
987 }
988
989 DPRINTK ("EXIT\n");
990 }
991
992
mdio_read(struct net_device * dev,int phy_id,int location)993 static int mdio_read (struct net_device *dev, int phy_id, int location)
994 {
995 struct netdrv_private *tp = dev->priv;
996 void *mdio_addr = tp->mmio_addr + Config4;
997 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
998 int retval = 0;
999 int i;
1000
1001 DPRINTK ("ENTER\n");
1002
1003 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1004 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1005 return location < 8 && mii_2_8139_map[location] ?
1006 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1007 }
1008 mdio_sync (mdio_addr);
1009 /* Shift the read command bits out. */
1010 for (i = 15; i >= 0; i--) {
1011 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1012
1013 writeb (MDIO_DIR | dataval, mdio_addr);
1014 mdio_delay ();
1015 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1016 mdio_delay ();
1017 }
1018
1019 /* Read the two transition, 16 data, and wire-idle bits. */
1020 for (i = 19; i > 0; i--) {
1021 writeb (0, mdio_addr);
1022 mdio_delay ();
1023 retval =
1024 (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1025 : 0);
1026 writeb (MDIO_CLK, mdio_addr);
1027 mdio_delay ();
1028 }
1029
1030 DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1031 return (retval >> 1) & 0xffff;
1032 }
1033
1034
mdio_write(struct net_device * dev,int phy_id,int location,int value)1035 static void mdio_write (struct net_device *dev, int phy_id, int location,
1036 int value)
1037 {
1038 struct netdrv_private *tp = dev->priv;
1039 void *mdio_addr = tp->mmio_addr + Config4;
1040 int mii_cmd =
1041 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1042 int i;
1043
1044 DPRINTK ("ENTER\n");
1045
1046 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1047 if (location < 8 && mii_2_8139_map[location]) {
1048 writew (value,
1049 tp->mmio_addr + mii_2_8139_map[location]);
1050 readw (tp->mmio_addr + mii_2_8139_map[location]);
1051 }
1052 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1053 return;
1054 }
1055 mdio_sync (mdio_addr);
1056
1057 /* Shift the command bits out. */
1058 for (i = 31; i >= 0; i--) {
1059 int dataval =
1060 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1061 writeb (dataval, mdio_addr);
1062 mdio_delay ();
1063 writeb (dataval | MDIO_CLK, mdio_addr);
1064 mdio_delay ();
1065 }
1066
1067 /* Clear out extra bits. */
1068 for (i = 2; i > 0; i--) {
1069 writeb (0, mdio_addr);
1070 mdio_delay ();
1071 writeb (MDIO_CLK, mdio_addr);
1072 mdio_delay ();
1073 }
1074
1075 DPRINTK ("EXIT\n");
1076 }
1077
1078
netdrv_open(struct net_device * dev)1079 static int netdrv_open (struct net_device *dev)
1080 {
1081 struct netdrv_private *tp = dev->priv;
1082 int retval;
1083 #ifdef NETDRV_DEBUG
1084 void *ioaddr = tp->mmio_addr;
1085 #endif
1086
1087 DPRINTK ("ENTER\n");
1088
1089 retval = request_irq (dev->irq, netdrv_interrupt, SA_SHIRQ, dev->name, dev);
1090 if (retval) {
1091 DPRINTK ("EXIT, returning %d\n", retval);
1092 return retval;
1093 }
1094
1095 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1096 &tp->tx_bufs_dma);
1097 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1098 &tp->rx_ring_dma);
1099 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1100 free_irq(dev->irq, dev);
1101
1102 if (tp->tx_bufs)
1103 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1104 tp->tx_bufs, tp->tx_bufs_dma);
1105 if (tp->rx_ring)
1106 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1107 tp->rx_ring, tp->rx_ring_dma);
1108
1109 DPRINTK ("EXIT, returning -ENOMEM\n");
1110 return -ENOMEM;
1111
1112 }
1113
1114 tp->full_duplex = tp->duplex_lock;
1115 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1116
1117 netdrv_init_ring (dev);
1118 netdrv_hw_start (dev);
1119
1120 DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1121 " GP Pins %2.2x %s-duplex.\n",
1122 dev->name, pci_resource_start (tp->pci_dev, 1),
1123 dev->irq, NETDRV_R8 (MediaStatus),
1124 tp->full_duplex ? "full" : "half");
1125
1126 /* Set the timer to switch to check for link beat and perhaps switch
1127 to an alternate media type. */
1128 init_timer (&tp->timer);
1129 tp->timer.expires = jiffies + 3 * HZ;
1130 tp->timer.data = (unsigned long) dev;
1131 tp->timer.function = &netdrv_timer;
1132 add_timer (&tp->timer);
1133
1134 DPRINTK ("EXIT, returning 0\n");
1135 return 0;
1136 }
1137
1138
1139 /* Start the hardware at open or resume. */
netdrv_hw_start(struct net_device * dev)1140 static void netdrv_hw_start (struct net_device *dev)
1141 {
1142 struct netdrv_private *tp = dev->priv;
1143 void *ioaddr = tp->mmio_addr;
1144 u32 i;
1145 u8 tmp;
1146
1147 DPRINTK ("ENTER\n");
1148
1149 /* Soft reset the chip. */
1150 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1151 udelay (100);
1152
1153 /* Check that the chip has finished the reset. */
1154 for (i = 1000; i > 0; i--)
1155 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1156 break;
1157
1158 /* Restore our idea of the MAC address. */
1159 NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1160 NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1161
1162 /* Must enable Tx/Rx before setting transfer thresholds! */
1163 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1164 CmdRxEnb | CmdTxEnb);
1165
1166 i = netdrv_rx_config |
1167 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1168 NETDRV_W32_F (RxConfig, i);
1169
1170 /* Check this value: the documentation for IFG contradicts ifself. */
1171 NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1172
1173 /* unlock Config[01234] and BMCR register writes */
1174 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1175 udelay (10);
1176
1177 tp->cur_rx = 0;
1178
1179 /* Lock Config[01234] and BMCR register writes */
1180 NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1181 udelay (10);
1182
1183 /* init Rx ring buffer DMA address */
1184 NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1185
1186 /* init Tx buffer DMA addresses */
1187 for (i = 0; i < NUM_TX_DESC; i++)
1188 NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1189
1190 NETDRV_W32_F (RxMissed, 0);
1191
1192 netdrv_set_rx_mode (dev);
1193
1194 /* no early-rx interrupts */
1195 NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1196
1197 /* make sure RxTx has started */
1198 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1199 CmdRxEnb | CmdTxEnb);
1200
1201 /* Enable all known interrupts by setting the interrupt mask. */
1202 NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1203
1204 netif_start_queue (dev);
1205
1206 DPRINTK ("EXIT\n");
1207 }
1208
1209
1210 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
netdrv_init_ring(struct net_device * dev)1211 static void netdrv_init_ring (struct net_device *dev)
1212 {
1213 struct netdrv_private *tp = dev->priv;
1214 int i;
1215
1216 DPRINTK ("ENTER\n");
1217
1218 tp->cur_rx = 0;
1219 atomic_set (&tp->cur_tx, 0);
1220 atomic_set (&tp->dirty_tx, 0);
1221
1222 for (i = 0; i < NUM_TX_DESC; i++) {
1223 tp->tx_info[i].skb = NULL;
1224 tp->tx_info[i].mapping = 0;
1225 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1226 }
1227
1228 DPRINTK ("EXIT\n");
1229 }
1230
1231
netdrv_timer(unsigned long data)1232 static void netdrv_timer (unsigned long data)
1233 {
1234 struct net_device *dev = (struct net_device *) data;
1235 struct netdrv_private *tp = dev->priv;
1236 void *ioaddr = tp->mmio_addr;
1237 int next_tick = 60 * HZ;
1238 int mii_lpa;
1239
1240 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1241
1242 if (!tp->duplex_lock && mii_lpa != 0xffff) {
1243 int duplex = (mii_lpa & LPA_100FULL)
1244 || (mii_lpa & 0x01C0) == 0x0040;
1245 if (tp->full_duplex != duplex) {
1246 tp->full_duplex = duplex;
1247 printk (KERN_INFO
1248 "%s: Setting %s-duplex based on MII #%d link"
1249 " partner ability of %4.4x.\n", dev->name,
1250 tp->full_duplex ? "full" : "half",
1251 tp->phys[0], mii_lpa);
1252 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1253 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1254 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1255 }
1256 }
1257
1258 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1259 dev->name, NETDRV_R16 (NWayLPAR));
1260 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x"
1261 " RxStatus %4.4x.\n", dev->name,
1262 NETDRV_R16 (IntrMask),
1263 NETDRV_R16 (IntrStatus),
1264 NETDRV_R32 (RxEarlyStatus));
1265 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1266 dev->name, NETDRV_R8 (Config0),
1267 NETDRV_R8 (Config1));
1268
1269 tp->timer.expires = jiffies + next_tick;
1270 add_timer (&tp->timer);
1271 }
1272
1273
netdrv_tx_clear(struct netdrv_private * tp)1274 static void netdrv_tx_clear (struct netdrv_private *tp)
1275 {
1276 int i;
1277
1278 atomic_set (&tp->cur_tx, 0);
1279 atomic_set (&tp->dirty_tx, 0);
1280
1281 /* Dump the unsent Tx packets. */
1282 for (i = 0; i < NUM_TX_DESC; i++) {
1283 struct ring_info *rp = &tp->tx_info[i];
1284 if (rp->mapping != 0) {
1285 pci_unmap_single (tp->pci_dev, rp->mapping,
1286 rp->skb->len, PCI_DMA_TODEVICE);
1287 rp->mapping = 0;
1288 }
1289 if (rp->skb) {
1290 dev_kfree_skb (rp->skb);
1291 rp->skb = NULL;
1292 tp->stats.tx_dropped++;
1293 }
1294 }
1295 }
1296
1297
netdrv_tx_timeout(struct net_device * dev)1298 static void netdrv_tx_timeout (struct net_device *dev)
1299 {
1300 struct netdrv_private *tp = dev->priv;
1301 void *ioaddr = tp->mmio_addr;
1302 int i;
1303 u8 tmp8;
1304 unsigned long flags;
1305
1306 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1307 "media %2.2x.\n", dev->name,
1308 NETDRV_R8 (ChipCmd),
1309 NETDRV_R16 (IntrStatus),
1310 NETDRV_R8 (MediaStatus));
1311
1312 /* disable Tx ASAP, if not already */
1313 tmp8 = NETDRV_R8 (ChipCmd);
1314 if (tmp8 & CmdTxEnb)
1315 NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1316
1317 /* Disable interrupts by clearing the interrupt mask. */
1318 NETDRV_W16 (IntrMask, 0x0000);
1319
1320 /* Emit info to figure out what went wrong. */
1321 printk (KERN_DEBUG "%s: Tx queue start entry %d dirty entry %d.\n",
1322 dev->name, atomic_read (&tp->cur_tx),
1323 atomic_read (&tp->dirty_tx));
1324 for (i = 0; i < NUM_TX_DESC; i++)
1325 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1326 dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1327 i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1328 " (queue head)" : "");
1329
1330 /* Stop a shared interrupt from scavenging while we are. */
1331 spin_lock_irqsave (&tp->lock, flags);
1332
1333 netdrv_tx_clear (tp);
1334
1335 spin_unlock_irqrestore (&tp->lock, flags);
1336
1337 /* ...and finally, reset everything */
1338 netdrv_hw_start (dev);
1339
1340 netif_wake_queue (dev);
1341 }
1342
1343
1344
netdrv_start_xmit(struct sk_buff * skb,struct net_device * dev)1345 static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1346 {
1347 struct netdrv_private *tp = dev->priv;
1348 void *ioaddr = tp->mmio_addr;
1349 int entry;
1350
1351 /* If we don't have auto-pad remember not to send random
1352 memory! */
1353
1354 if (skb->len < ETH_ZLEN)
1355 {
1356 skb = skb_padto(skb, ETH_ZLEN);
1357 if(skb == NULL)
1358 return 0;
1359 }
1360
1361 /* Calculate the next Tx descriptor entry. */
1362 entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1363
1364 assert (tp->tx_info[entry].skb == NULL);
1365 assert (tp->tx_info[entry].mapping == 0);
1366
1367 tp->tx_info[entry].skb = skb;
1368 /* tp->tx_info[entry].mapping = 0; */
1369 memcpy (tp->tx_buf[entry], skb->data, skb->len);
1370
1371 NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1372 tp->tx_flag | skb->len);
1373
1374 dev->trans_start = jiffies;
1375 atomic_inc (&tp->cur_tx);
1376 if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1377 netif_stop_queue (dev);
1378
1379 DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1380 dev->name, skb->data, skb->len, entry);
1381
1382 return 0;
1383 }
1384
1385
netdrv_tx_interrupt(struct net_device * dev,struct netdrv_private * tp,void * ioaddr)1386 static void netdrv_tx_interrupt (struct net_device *dev,
1387 struct netdrv_private *tp,
1388 void *ioaddr)
1389 {
1390 int cur_tx, dirty_tx, tx_left;
1391
1392 assert (dev != NULL);
1393 assert (tp != NULL);
1394 assert (ioaddr != NULL);
1395
1396 dirty_tx = atomic_read (&tp->dirty_tx);
1397
1398 cur_tx = atomic_read (&tp->cur_tx);
1399 tx_left = cur_tx - dirty_tx;
1400 while (tx_left > 0) {
1401 int entry = dirty_tx % NUM_TX_DESC;
1402 int txstatus;
1403
1404 txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1405
1406 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1407 break; /* It still hasn't been Txed */
1408
1409 /* Note: TxCarrierLost is always asserted at 100mbps. */
1410 if (txstatus & (TxOutOfWindow | TxAborted)) {
1411 /* There was an major error, log it. */
1412 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1413 dev->name, txstatus);
1414 tp->stats.tx_errors++;
1415 if (txstatus & TxAborted) {
1416 tp->stats.tx_aborted_errors++;
1417 NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1418 }
1419 if (txstatus & TxCarrierLost)
1420 tp->stats.tx_carrier_errors++;
1421 if (txstatus & TxOutOfWindow)
1422 tp->stats.tx_window_errors++;
1423 } else {
1424 if (txstatus & TxUnderrun) {
1425 /* Add 64 to the Tx FIFO threshold. */
1426 if (tp->tx_flag < 0x00300000)
1427 tp->tx_flag += 0x00020000;
1428 tp->stats.tx_fifo_errors++;
1429 }
1430 tp->stats.collisions += (txstatus >> 24) & 15;
1431 tp->stats.tx_bytes += txstatus & 0x7ff;
1432 tp->stats.tx_packets++;
1433 }
1434
1435 /* Free the original skb. */
1436 if (tp->tx_info[entry].mapping != 0) {
1437 pci_unmap_single(tp->pci_dev,
1438 tp->tx_info[entry].mapping,
1439 tp->tx_info[entry].skb->len,
1440 PCI_DMA_TODEVICE);
1441 tp->tx_info[entry].mapping = 0;
1442 }
1443 dev_kfree_skb_irq (tp->tx_info[entry].skb);
1444 tp->tx_info[entry].skb = NULL;
1445 dirty_tx++;
1446 if (dirty_tx < 0) { /* handle signed int overflow */
1447 atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1448 dirty_tx = cur_tx - tx_left + 1;
1449 }
1450 if (netif_queue_stopped (dev))
1451 netif_wake_queue (dev);
1452
1453 cur_tx = atomic_read (&tp->cur_tx);
1454 tx_left = cur_tx - dirty_tx;
1455
1456 }
1457
1458 #ifndef NETDRV_NDEBUG
1459 if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1460 printk (KERN_ERR
1461 "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1462 dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1463 dirty_tx += NUM_TX_DESC;
1464 }
1465 #endif /* NETDRV_NDEBUG */
1466
1467 atomic_set (&tp->dirty_tx, dirty_tx);
1468 }
1469
1470
1471 /* TODO: clean this up! Rx reset need not be this intensive */
netdrv_rx_err(u32 rx_status,struct net_device * dev,struct netdrv_private * tp,void * ioaddr)1472 static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1473 struct netdrv_private *tp, void *ioaddr)
1474 {
1475 u8 tmp8;
1476 int tmp_work = 1000;
1477
1478 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1479 dev->name, rx_status);
1480 if (rx_status & RxTooLong) {
1481 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1482 dev->name, rx_status);
1483 /* A.C.: The chip hangs here. */
1484 }
1485 tp->stats.rx_errors++;
1486 if (rx_status & (RxBadSymbol | RxBadAlign))
1487 tp->stats.rx_frame_errors++;
1488 if (rx_status & (RxRunt | RxTooLong))
1489 tp->stats.rx_length_errors++;
1490 if (rx_status & RxCRCErr)
1491 tp->stats.rx_crc_errors++;
1492 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1493 tp->cur_rx = 0;
1494
1495 /* disable receive */
1496 tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1497 NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1498
1499 /* A.C.: Reset the multicast list. */
1500 netdrv_set_rx_mode (dev);
1501
1502 /* XXX potentially temporary hack to
1503 * restart hung receiver */
1504 while (--tmp_work > 0) {
1505 tmp8 = NETDRV_R8 (ChipCmd);
1506 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1507 break;
1508 NETDRV_W8_F (ChipCmd,
1509 (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1510 }
1511
1512 /* G.S.: Re-enable receiver */
1513 /* XXX temporary hack to work around receiver hang */
1514 netdrv_set_rx_mode (dev);
1515
1516 if (tmp_work <= 0)
1517 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1518 }
1519
1520
1521 /* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1522 field alignments and semantics. */
netdrv_rx_interrupt(struct net_device * dev,struct netdrv_private * tp,void * ioaddr)1523 static void netdrv_rx_interrupt (struct net_device *dev,
1524 struct netdrv_private *tp, void *ioaddr)
1525 {
1526 unsigned char *rx_ring;
1527 u16 cur_rx;
1528
1529 assert (dev != NULL);
1530 assert (tp != NULL);
1531 assert (ioaddr != NULL);
1532
1533 rx_ring = tp->rx_ring;
1534 cur_rx = tp->cur_rx;
1535
1536 DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1537 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1538 NETDRV_R16 (RxBufAddr),
1539 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1540
1541 while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1542 int ring_offset = cur_rx % RX_BUF_LEN;
1543 u32 rx_status;
1544 unsigned int rx_size;
1545 unsigned int pkt_size;
1546 struct sk_buff *skb;
1547
1548 /* read size+status of next frame from DMA ring buffer */
1549 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1550 rx_size = rx_status >> 16;
1551 pkt_size = rx_size - 4;
1552
1553 DPRINTK ("%s: netdrv_rx() status %4.4x, size %4.4x,"
1554 " cur %4.4x.\n", dev->name, rx_status,
1555 rx_size, cur_rx);
1556 #if NETDRV_DEBUG > 2
1557 {
1558 int i;
1559 DPRINTK ("%s: Frame contents ", dev->name);
1560 for (i = 0; i < 70; i++)
1561 printk (" %2.2x",
1562 rx_ring[ring_offset + i]);
1563 printk (".\n");
1564 }
1565 #endif
1566
1567 /* If Rx err or invalid rx_size/rx_status received
1568 * (which happens if we get lost in the ring),
1569 * Rx process gets reset, so we abort any further
1570 * Rx processing.
1571 */
1572 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1573 (!(rx_status & RxStatusOK))) {
1574 netdrv_rx_err (rx_status, dev, tp, ioaddr);
1575 return;
1576 }
1577
1578 /* Malloc up new buffer, compatible with net-2e. */
1579 /* Omit the four octet CRC from the length. */
1580
1581 /* TODO: consider allocating skb's outside of
1582 * interrupt context, both to speed interrupt processing,
1583 * and also to reduce the chances of having to
1584 * drop packets here under memory pressure.
1585 */
1586
1587 skb = dev_alloc_skb (pkt_size + 2);
1588 if (skb) {
1589 skb->dev = dev;
1590 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1591
1592 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
1593 skb_put (skb, pkt_size);
1594
1595 skb->protocol = eth_type_trans (skb, dev);
1596 netif_rx (skb);
1597 dev->last_rx = jiffies;
1598 tp->stats.rx_bytes += pkt_size;
1599 tp->stats.rx_packets++;
1600 } else {
1601 printk (KERN_WARNING
1602 "%s: Memory squeeze, dropping packet.\n",
1603 dev->name);
1604 tp->stats.rx_dropped++;
1605 }
1606
1607 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1608 NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1609 }
1610
1611 DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1612 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1613 NETDRV_R16 (RxBufAddr),
1614 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1615
1616 tp->cur_rx = cur_rx;
1617 }
1618
1619
netdrv_weird_interrupt(struct net_device * dev,struct netdrv_private * tp,void * ioaddr,int status,int link_changed)1620 static void netdrv_weird_interrupt (struct net_device *dev,
1621 struct netdrv_private *tp,
1622 void *ioaddr,
1623 int status, int link_changed)
1624 {
1625 printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1626 dev->name, status);
1627
1628 assert (dev != NULL);
1629 assert (tp != NULL);
1630 assert (ioaddr != NULL);
1631
1632 /* Update the error count. */
1633 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1634 NETDRV_W32 (RxMissed, 0);
1635
1636 if ((status & RxUnderrun) && link_changed &&
1637 (tp->drv_flags & HAS_LNK_CHNG)) {
1638 /* Really link-change on new chips. */
1639 int lpar = NETDRV_R16 (NWayLPAR);
1640 int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1641 || tp->duplex_lock;
1642 if (tp->full_duplex != duplex) {
1643 tp->full_duplex = duplex;
1644 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1645 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1646 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1647 }
1648 status &= ~RxUnderrun;
1649 }
1650
1651 /* XXX along with netdrv_rx_err, are we double-counting errors? */
1652 if (status &
1653 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1654 tp->stats.rx_errors++;
1655
1656 if (status & (PCSTimeout))
1657 tp->stats.rx_length_errors++;
1658 if (status & (RxUnderrun | RxFIFOOver))
1659 tp->stats.rx_fifo_errors++;
1660 if (status & RxOverflow) {
1661 tp->stats.rx_over_errors++;
1662 tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1663 NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1664 }
1665 if (status & PCIErr) {
1666 u16 pci_cmd_status;
1667 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1668
1669 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1670 dev->name, pci_cmd_status);
1671 }
1672 }
1673
1674
1675 /* The interrupt handler does all of the Rx thread work and cleans up
1676 after the Tx thread. */
netdrv_interrupt(int irq,void * dev_instance,struct pt_regs * regs)1677 static void netdrv_interrupt (int irq, void *dev_instance,
1678 struct pt_regs *regs)
1679 {
1680 struct net_device *dev = (struct net_device *) dev_instance;
1681 struct netdrv_private *tp = dev->priv;
1682 int boguscnt = max_interrupt_work;
1683 void *ioaddr = tp->mmio_addr;
1684 int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1685
1686 spin_lock (&tp->lock);
1687
1688 do {
1689 status = NETDRV_R16 (IntrStatus);
1690
1691 /* h/w no longer present (hotplug?) or major error, bail */
1692 if (status == 0xFFFF)
1693 break;
1694
1695 /* Acknowledge all of the current interrupt sources ASAP */
1696 NETDRV_W16_F (IntrStatus, status);
1697
1698 DPRINTK ("%s: interrupt status=%#4.4x new intstat=%#4.4x.\n",
1699 dev->name, status,
1700 NETDRV_R16 (IntrStatus));
1701
1702 if ((status &
1703 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1704 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1705 break;
1706
1707 /* Check uncommon events with one test. */
1708 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1709 RxFIFOOver | TxErr | RxErr))
1710 netdrv_weird_interrupt (dev, tp, ioaddr,
1711 status, link_changed);
1712
1713 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) /* Rx interrupt */
1714 netdrv_rx_interrupt (dev, tp, ioaddr);
1715
1716 if (status & (TxOK | TxErr))
1717 netdrv_tx_interrupt (dev, tp, ioaddr);
1718
1719 boguscnt--;
1720 } while (boguscnt > 0);
1721
1722 if (boguscnt <= 0) {
1723 printk (KERN_WARNING
1724 "%s: Too much work at interrupt, "
1725 "IntrStatus=0x%4.4x.\n", dev->name,
1726 status);
1727
1728 /* Clear all interrupt sources. */
1729 NETDRV_W16 (IntrStatus, 0xffff);
1730 }
1731
1732 spin_unlock (&tp->lock);
1733
1734 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1735 dev->name, NETDRV_R16 (IntrStatus));
1736 }
1737
1738
netdrv_close(struct net_device * dev)1739 static int netdrv_close (struct net_device *dev)
1740 {
1741 struct netdrv_private *tp = dev->priv;
1742 void *ioaddr = tp->mmio_addr;
1743 unsigned long flags;
1744
1745 DPRINTK ("ENTER\n");
1746
1747 netif_stop_queue (dev);
1748
1749 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1750 dev->name, NETDRV_R16 (IntrStatus));
1751
1752 del_timer_sync (&tp->timer);
1753
1754 spin_lock_irqsave (&tp->lock, flags);
1755
1756 /* Stop the chip's Tx and Rx DMA processes. */
1757 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1758
1759 /* Disable interrupts by clearing the interrupt mask. */
1760 NETDRV_W16 (IntrMask, 0x0000);
1761
1762 /* Update the error counts. */
1763 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1764 NETDRV_W32 (RxMissed, 0);
1765
1766 spin_unlock_irqrestore (&tp->lock, flags);
1767
1768 synchronize_irq ();
1769 free_irq (dev->irq, dev);
1770
1771 netdrv_tx_clear (tp);
1772
1773 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1774 tp->rx_ring, tp->rx_ring_dma);
1775 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1776 tp->tx_bufs, tp->tx_bufs_dma);
1777 tp->rx_ring = NULL;
1778 tp->tx_bufs = NULL;
1779
1780 /* Green! Put the chip in low-power mode. */
1781 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1782 NETDRV_W8 (Config1, 0x03);
1783 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1784
1785 DPRINTK ("EXIT\n");
1786 return 0;
1787 }
1788
1789
netdrv_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1790 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1791 {
1792 struct netdrv_private *tp = dev->priv;
1793 struct mii_ioctl_data *data = (struct mii_ioctl_data *) & rq->ifr_data;
1794 unsigned long flags;
1795 int rc = 0;
1796
1797 DPRINTK ("ENTER\n");
1798
1799 switch (cmd) {
1800 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1801 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
1802 data->phy_id = tp->phys[0] & 0x3f;
1803 /* Fall Through */
1804
1805 case SIOCGMIIREG: /* Read MII PHY register. */
1806 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
1807 spin_lock_irqsave (&tp->lock, flags);
1808 data->val_out = mdio_read (dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1809 spin_unlock_irqrestore (&tp->lock, flags);
1810 break;
1811
1812 case SIOCSMIIREG: /* Write MII PHY register. */
1813 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
1814 if (!capable (CAP_NET_ADMIN)) {
1815 rc = -EPERM;
1816 break;
1817 }
1818
1819 spin_lock_irqsave (&tp->lock, flags);
1820 mdio_write (dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1821 spin_unlock_irqrestore (&tp->lock, flags);
1822 break;
1823
1824 default:
1825 rc = -EOPNOTSUPP;
1826 break;
1827 }
1828
1829 DPRINTK ("EXIT, returning %d\n", rc);
1830 return rc;
1831 }
1832
1833
netdrv_get_stats(struct net_device * dev)1834 static struct net_device_stats *netdrv_get_stats (struct net_device *dev)
1835 {
1836 struct netdrv_private *tp = dev->priv;
1837 void *ioaddr = tp->mmio_addr;
1838
1839 DPRINTK ("ENTER\n");
1840
1841 assert (tp != NULL);
1842
1843 if (netif_running(dev)) {
1844 unsigned long flags;
1845
1846 spin_lock_irqsave (&tp->lock, flags);
1847
1848 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1849 NETDRV_W32 (RxMissed, 0);
1850
1851 spin_unlock_irqrestore (&tp->lock, flags);
1852 }
1853
1854 DPRINTK ("EXIT\n");
1855 return &tp->stats;
1856 }
1857
1858 /* Set or clear the multicast filter for this adaptor.
1859 This routine is not state sensitive and need not be SMP locked. */
1860
netdrv_set_rx_mode(struct net_device * dev)1861 static void netdrv_set_rx_mode (struct net_device *dev)
1862 {
1863 struct netdrv_private *tp = dev->priv;
1864 void *ioaddr = tp->mmio_addr;
1865 u32 mc_filter[2]; /* Multicast hash filter */
1866 int i, rx_mode;
1867 u32 tmp;
1868
1869 DPRINTK ("ENTER\n");
1870
1871 DPRINTK ("%s: netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1872 dev->name, dev->flags, NETDRV_R32 (RxConfig));
1873
1874 /* Note: do not reorder, GCC is clever about common statements. */
1875 if (dev->flags & IFF_PROMISC) {
1876 /* Unconditionally log net taps. */
1877 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1878 dev->name);
1879 rx_mode =
1880 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1881 AcceptAllPhys;
1882 mc_filter[1] = mc_filter[0] = 0xffffffff;
1883 } else if ((dev->mc_count > multicast_filter_limit)
1884 || (dev->flags & IFF_ALLMULTI)) {
1885 /* Too many to filter perfectly -- accept all multicasts. */
1886 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1887 mc_filter[1] = mc_filter[0] = 0xffffffff;
1888 } else {
1889 struct dev_mc_list *mclist;
1890 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1891 mc_filter[1] = mc_filter[0] = 0;
1892 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1893 i++, mclist = mclist->next)
1894 set_bit (ether_crc (ETH_ALEN, mclist->dmi_addr) >> 26,
1895 mc_filter);
1896 }
1897
1898 /* if called from irq handler, lock already acquired */
1899 if (!in_irq ())
1900 spin_lock_irq (&tp->lock);
1901
1902 /* We can safely update without stopping the chip. */
1903 tmp = netdrv_rx_config | rx_mode |
1904 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1905 NETDRV_W32_F (RxConfig, tmp);
1906 NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1907 NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1908
1909 if (!in_irq ())
1910 spin_unlock_irq (&tp->lock);
1911
1912 DPRINTK ("EXIT\n");
1913 }
1914
1915
1916 #ifdef CONFIG_PM
1917
netdrv_suspend(struct pci_dev * pdev,u32 state)1918 static int netdrv_suspend (struct pci_dev *pdev, u32 state)
1919 {
1920 struct net_device *dev = pci_get_drvdata (pdev);
1921 struct netdrv_private *tp = dev->priv;
1922 void *ioaddr = tp->mmio_addr;
1923 unsigned long flags;
1924
1925 if (!netif_running(dev))
1926 return;
1927 netif_device_detach (dev);
1928
1929 spin_lock_irqsave (&tp->lock, flags);
1930
1931 /* Disable interrupts, stop Tx and Rx. */
1932 NETDRV_W16 (IntrMask, 0x0000);
1933 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1934
1935 /* Update the error counts. */
1936 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1937 NETDRV_W32 (RxMissed, 0);
1938
1939 spin_unlock_irqrestore (&tp->lock, flags);
1940
1941 pci_power_off (pdev, -1);
1942
1943 return 0;
1944 }
1945
1946
netdrv_resume(struct pci_dev * pdev)1947 static int netdrv_resume (struct pci_dev *pdev)
1948 {
1949 struct net_device *dev = pci_get_drvdata (pdev);
1950
1951 if (!netif_running(dev))
1952 return;
1953 pci_power_on (pdev);
1954 netif_device_attach (dev);
1955 netdrv_hw_start (dev);
1956
1957 return 0;
1958 }
1959
1960 #endif /* CONFIG_PM */
1961
1962
1963 static struct pci_driver netdrv_pci_driver = {
1964 name: MODNAME,
1965 id_table: netdrv_pci_tbl,
1966 probe: netdrv_init_one,
1967 remove: __devexit_p(netdrv_remove_one),
1968 #ifdef CONFIG_PM
1969 suspend: netdrv_suspend,
1970 resume: netdrv_resume,
1971 #endif /* CONFIG_PM */
1972 };
1973
1974
netdrv_init_module(void)1975 static int __init netdrv_init_module (void)
1976 {
1977 /* when a module, this is printed whether or not devices are found in probe */
1978 #ifdef MODULE
1979 printk(version);
1980 #endif
1981 return pci_module_init (&netdrv_pci_driver);
1982 }
1983
1984
netdrv_cleanup_module(void)1985 static void __exit netdrv_cleanup_module (void)
1986 {
1987 pci_unregister_driver (&netdrv_pci_driver);
1988 }
1989
1990
1991 module_init(netdrv_init_module);
1992 module_exit(netdrv_cleanup_module);
1993