1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2006 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 30 /* glue for the OS independent part of e1000 31 * includes register access macros 32 */ 33 34 #ifndef _E1000_OSDEP_H_ 35 #define _E1000_OSDEP_H_ 36 37 #include <linux/types.h> 38 #include <linux/pci.h> 39 #include <linux/delay.h> 40 #include <asm/io.h> 41 #include <linux/interrupt.h> 42 #include <linux/sched.h> 43 #include "kcompat.h" 44 45 #define usec_delay(x) udelay(x) 46 #ifndef msec_delay 47 #define msec_delay(x) do { if(in_interrupt()) { \ 48 /* Don't mdelay in interrupt context! */ \ 49 BUG(); \ 50 } else { \ 51 msleep(x); \ 52 } } while (0) 53 54 /* Some workarounds require millisecond delays and are run during interrupt 55 * context. Most notably, when establishing link, the phy may need tweaking 56 * but cannot process phy register reads/writes faster than millisecond 57 * intervals...and we establish link due to a "link status change" interrupt. 58 */ 59 #define msec_delay_irq(x) mdelay(x) 60 #endif 61 62 #define PCI_COMMAND_REGISTER PCI_COMMAND 63 #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE 64 65 typedef enum { 66 #undef FALSE 67 FALSE = 0, 68 #undef TRUE 69 TRUE = 1 70 } boolean_t; 71 72 #define DEBUGOUT(S) 73 #define DEBUGOUT1(S, A...) 74 75 #define DEBUGFUNC(F) DEBUGOUT(F "\n") 76 #define DEBUGOUT2 DEBUGOUT1 77 #define DEBUGOUT3 DEBUGOUT2 78 #define DEBUGOUT7 DEBUGOUT3 79 80 #ifdef __BIG_ENDIAN 81 #define E1000_BIG_ENDIAN __BIG_ENDIAN 82 #endif 83 84 #define E1000_WRITE_REG(a, reg, value) ( \ 85 writel((value), ((a)->hw_addr + \ 86 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg)))) 87 88 #define E1000_READ_REG(a, reg) ( \ 89 readl((a)->hw_addr + \ 90 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg))) 91 92 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \ 93 writel((value), ((a)->hw_addr + \ 94 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ 95 ((offset) << 2)))) 96 97 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ 98 readl((a)->hw_addr + \ 99 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ 100 ((offset) << 2))) 101 102 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY 103 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY 104 105 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \ 106 writew((value), ((a)->hw_addr + \ 107 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ 108 ((offset) << 1)))) 109 110 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \ 111 readw((a)->hw_addr + \ 112 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ 113 ((offset) << 1))) 114 115 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \ 116 writeb((value), ((a)->hw_addr + \ 117 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ 118 (offset)))) 119 120 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \ 121 readb((a)->hw_addr + \ 122 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ 123 (offset))) 124 125 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) 126 127 #define E1000_WRITE_ICH_FLASH_REG(a, reg, value) ( \ 128 writel((value), ((a)->flash_address + reg))) 129 130 #define E1000_READ_ICH_FLASH_REG(a, reg) ( \ 131 readl((a)->flash_address + reg)) 132 133 #define E1000_WRITE_ICH_FLASH_REG16(a, reg, value) ( \ 134 writew((value), ((a)->flash_address + reg))) 135 136 #define E1000_READ_ICH_FLASH_REG16(a, reg) ( \ 137 readw((a)->flash_address + reg)) 138 139 #endif /* _E1000_OSDEP_H_ */ 140