1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringstr�m - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 See 8139too.txt for more details.
91
92 */
93
94 #define DRV_NAME "8139too"
95 #define DRV_VERSION "0.9.26"
96
97
98 #include <linux/config.h>
99 #include <linux/module.h>
100 #include <linux/kernel.h>
101 #include <linux/compiler.h>
102 #include <linux/pci.h>
103 #include <linux/init.h>
104 #include <linux/ioport.h>
105 #include <linux/netdevice.h>
106 #include <linux/etherdevice.h>
107 #include <linux/rtnetlink.h>
108 #include <linux/delay.h>
109 #include <linux/ethtool.h>
110 #include <linux/mii.h>
111 #include <linux/completion.h>
112 #include <linux/crc32.h>
113 #include <asm/io.h>
114 #include <asm/uaccess.h>
115
116 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
117 #define PFX DRV_NAME ": "
118
119 /* Default Message level */
120 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
121 NETIF_MSG_PROBE | \
122 NETIF_MSG_LINK)
123
124
125 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
126 #ifdef CONFIG_8139TOO_PIO
127 #define USE_IO_OPS 1
128 #endif
129
130 /* use a 16K rx ring buffer instead of the default 32K */
131 #ifdef CONFIG_SH_DREAMCAST
132 #define USE_BUF16K 1
133 #endif
134
135 /* define to 1 to enable copious debugging info */
136 #undef RTL8139_DEBUG
137
138 /* define to 1 to disable lightweight runtime debugging checks */
139 #undef RTL8139_NDEBUG
140
141
142 #ifdef RTL8139_DEBUG
143 /* note: prints function name for you */
144 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
145 #else
146 # define DPRINTK(fmt, args...)
147 #endif
148
149 #ifdef RTL8139_NDEBUG
150 # define assert(expr) do {} while (0)
151 #else
152 # define assert(expr) \
153 if(!(expr)) { \
154 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
155 #expr,__FILE__,__FUNCTION__,__LINE__); \
156 }
157 #endif
158
159
160 /* A few user-configurable values. */
161 /* media options */
162 #define MAX_UNITS 8
163 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
164 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
165
166 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
167 static int max_interrupt_work = 20;
168
169 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
170 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
171 static int multicast_filter_limit = 32;
172
173 /* bitmapped message enable number */
174 static int debug = -1;
175
176 /* Size of the in-memory receive ring. */
177 #ifdef USE_BUF16K
178 #define RX_BUF_LEN_IDX 1 /* 0==8K, 1==16K, 2==32K, 3==64K */
179 #else
180 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
181 #endif
182 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
183 #define RX_BUF_PAD 16
184 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
185 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
186
187 /* Number of Tx descriptor registers. */
188 #define NUM_TX_DESC 4
189
190 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
191 #define MAX_ETH_FRAME_SIZE 1536
192
193 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
194 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
195 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
196
197 /* PCI Tuning Parameters
198 Threshold is bytes transferred to chip before transmission starts. */
199 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
200
201 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
202 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
203 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
205 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
206
207 /* Operational parameters that usually are not changed. */
208 /* Time in jiffies before concluding the transmitter is hung. */
209 #define TX_TIMEOUT (6*HZ)
210
211
212 enum {
213 HAS_MII_XCVR = 0x010000,
214 HAS_CHIP_XCVR = 0x020000,
215 HAS_LNK_CHNG = 0x040000,
216 };
217
218 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
219 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
220 #define RTL_MIN_IO_SIZE 0x80
221 #define RTL8139B_IO_SIZE 256
222
223 #define RTL8129_CAPS HAS_MII_XCVR
224 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
225
226 typedef enum {
227 RTL8139 = 0,
228 RTL8129,
229 } board_t;
230
231
232 /* indexed by board_t, above */
233 static struct {
234 const char *name;
235 u32 hw_flags;
236 } board_info[] __devinitdata = {
237 { "RealTek RTL8139", RTL8139_CAPS },
238 { "RealTek RTL8129", RTL8129_CAPS },
239 };
240
241
242 static struct pci_device_id rtl8139_pci_tbl[] = {
243 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
262
263 #ifdef CONFIG_SH_SECUREEDGE5410
264 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
265 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
266 #endif
267 #ifdef CONFIG_8139TOO_8129
268 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
269 #endif
270
271 /* some crazy cards report invalid vendor ids like
272 * 0x0001 here. The other ids are valid and constant,
273 * so we simply don't match on the main vendor id.
274 */
275 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
277 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
278
279 {0,}
280 };
281 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
282
283 static struct {
284 const char str[ETH_GSTRING_LEN];
285 } ethtool_stats_keys[] = {
286 { "early_rx" },
287 { "tx_buf_mapped" },
288 { "tx_timeouts" },
289 { "rx_lost_in_ring" },
290 };
291
292 /* The rest of these values should never change. */
293
294 /* Symbolic offsets to registers. */
295 enum RTL8139_registers {
296 MAC0 = 0, /* Ethernet hardware address. */
297 MAR0 = 8, /* Multicast filter. */
298 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
299 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
300 RxBuf = 0x30,
301 ChipCmd = 0x37,
302 RxBufPtr = 0x38,
303 RxBufAddr = 0x3A,
304 IntrMask = 0x3C,
305 IntrStatus = 0x3E,
306 TxConfig = 0x40,
307 RxConfig = 0x44,
308 Timer = 0x48, /* A general-purpose counter. */
309 RxMissed = 0x4C, /* 24 bits valid, write clears. */
310 Cfg9346 = 0x50,
311 Config0 = 0x51,
312 Config1 = 0x52,
313 FlashReg = 0x54,
314 MediaStatus = 0x58,
315 Config3 = 0x59,
316 Config4 = 0x5A, /* absent on RTL-8139A */
317 HltClk = 0x5B,
318 MultiIntr = 0x5C,
319 TxSummary = 0x60,
320 BasicModeCtrl = 0x62,
321 BasicModeStatus = 0x64,
322 NWayAdvert = 0x66,
323 NWayLPAR = 0x68,
324 NWayExpansion = 0x6A,
325 /* Undocumented registers, but required for proper operation. */
326 FIFOTMS = 0x70, /* FIFO Control and test. */
327 CSCR = 0x74, /* Chip Status and Configuration Register. */
328 PARA78 = 0x78,
329 PARA7c = 0x7c, /* Magic transceiver parameter register. */
330 Config5 = 0xD8, /* absent on RTL-8139A */
331 };
332
333 enum ClearBitMasks {
334 MultiIntrClear = 0xF000,
335 ChipCmdClear = 0xE2,
336 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
337 };
338
339 enum ChipCmdBits {
340 CmdReset = 0x10,
341 CmdRxEnb = 0x08,
342 CmdTxEnb = 0x04,
343 RxBufEmpty = 0x01,
344 };
345
346 /* Interrupt register bits, using my own meaningful names. */
347 enum IntrStatusBits {
348 PCIErr = 0x8000,
349 PCSTimeout = 0x4000,
350 RxFIFOOver = 0x40,
351 RxUnderrun = 0x20,
352 RxOverflow = 0x10,
353 TxErr = 0x08,
354 TxOK = 0x04,
355 RxErr = 0x02,
356 RxOK = 0x01,
357
358 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
359 };
360
361 enum TxStatusBits {
362 TxHostOwns = 0x2000,
363 TxUnderrun = 0x4000,
364 TxStatOK = 0x8000,
365 TxOutOfWindow = 0x20000000,
366 TxAborted = 0x40000000,
367 TxCarrierLost = 0x80000000,
368 };
369 enum RxStatusBits {
370 RxMulticast = 0x8000,
371 RxPhysical = 0x4000,
372 RxBroadcast = 0x2000,
373 RxBadSymbol = 0x0020,
374 RxRunt = 0x0010,
375 RxTooLong = 0x0008,
376 RxCRCErr = 0x0004,
377 RxBadAlign = 0x0002,
378 RxStatusOK = 0x0001,
379 };
380
381 /* Bits in RxConfig. */
382 enum rx_mode_bits {
383 AcceptErr = 0x20,
384 AcceptRunt = 0x10,
385 AcceptBroadcast = 0x08,
386 AcceptMulticast = 0x04,
387 AcceptMyPhys = 0x02,
388 AcceptAllPhys = 0x01,
389 };
390
391 /* Bits in TxConfig. */
392 enum tx_config_bits {
393 TxIFG1 = (1 << 25), /* Interframe Gap Time */
394 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
395 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
396 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
397 TxClearAbt = (1 << 0), /* Clear abort (WO) */
398 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
399 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
400
401 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
402 };
403
404 /* Bits in Config1 */
405 enum Config1Bits {
406 Cfg1_PM_Enable = 0x01,
407 Cfg1_VPD_Enable = 0x02,
408 Cfg1_PIO = 0x04,
409 Cfg1_MMIO = 0x08,
410 LWAKE = 0x10, /* not on 8139, 8139A */
411 Cfg1_Driver_Load = 0x20,
412 Cfg1_LED0 = 0x40,
413 Cfg1_LED1 = 0x80,
414 SLEEP = (1 << 1), /* only on 8139, 8139A */
415 PWRDN = (1 << 0), /* only on 8139, 8139A */
416 };
417
418 /* Bits in Config3 */
419 enum Config3Bits {
420 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
421 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
422 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
423 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
424 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
425 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
426 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
427 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
428 };
429
430 /* Bits in Config4 */
431 enum Config4Bits {
432 LWPTN = (1 << 2), /* not on 8139, 8139A */
433 };
434
435 /* Bits in Config5 */
436 enum Config5Bits {
437 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
438 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
439 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
440 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
441 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
442 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
443 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
444 };
445
446 enum RxConfigBits {
447 /* rx fifo threshold */
448 RxCfgFIFOShift = 13,
449 RxCfgFIFONone = (7 << RxCfgFIFOShift),
450
451 /* Max DMA burst */
452 RxCfgDMAShift = 8,
453 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
454
455 /* rx ring buffer length */
456 RxCfgRcv8K = 0,
457 RxCfgRcv16K = (1 << 11),
458 RxCfgRcv32K = (1 << 12),
459 RxCfgRcv64K = (1 << 11) | (1 << 12),
460
461 /* Disable packet wrap at end of Rx buffer */
462 RxNoWrap = (1 << 7),
463 };
464
465 /* Twister tuning parameters from RealTek.
466 Completely undocumented, but required to tune bad links on some boards. */
467 enum CSCRBits {
468 CSCR_LinkOKBit = 0x0400,
469 CSCR_LinkChangeBit = 0x0800,
470 CSCR_LinkStatusBits = 0x0f000,
471 CSCR_LinkDownOffCmd = 0x003c0,
472 CSCR_LinkDownCmd = 0x0f3c0,
473 };
474
475 enum Cfg9346Bits {
476 Cfg9346_Lock = 0x00,
477 Cfg9346_Unlock = 0xC0,
478 };
479
480 typedef enum {
481 CH_8139 = 0,
482 CH_8139_K,
483 CH_8139A,
484 CH_8139A_G,
485 CH_8139B,
486 CH_8130,
487 CH_8139C,
488 CH_8100,
489 CH_8100B_8139D,
490 CH_8101,
491 } chip_t;
492
493 enum chip_flags {
494 HasHltClk = (1 << 0),
495 HasLWake = (1 << 1),
496 };
497
498 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
499 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
500 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
501
502 /* directly indexed by chip_t, above */
503 const static struct {
504 const char *name;
505 u32 version; /* from RTL8139C/RTL8139D docs */
506 u32 flags;
507 } rtl_chip_info[] = {
508 { "RTL-8139",
509 HW_REVID(1, 0, 0, 0, 0, 0, 0),
510 HasHltClk,
511 },
512
513 { "RTL-8139 rev K",
514 HW_REVID(1, 1, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139A",
519 HW_REVID(1, 1, 1, 0, 0, 0, 0),
520 HasHltClk, /* XXX undocumented? */
521 },
522
523 { "RTL-8139A rev G",
524 HW_REVID(1, 1, 1, 0, 0, 1, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139B",
529 HW_REVID(1, 1, 1, 1, 0, 0, 0),
530 HasLWake,
531 },
532
533 { "RTL-8130",
534 HW_REVID(1, 1, 1, 1, 1, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8139C",
539 HW_REVID(1, 1, 1, 0, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8100",
544 HW_REVID(1, 1, 1, 1, 0, 1, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100B/8139D",
549 HW_REVID(1, 1, 1, 0, 1, 0, 1),
550 HasLWake,
551 },
552
553 { "RTL-8101",
554 HW_REVID(1, 1, 1, 0, 1, 1, 1),
555 HasLWake,
556 },
557 };
558
559 struct rtl_extra_stats {
560 unsigned long early_rx;
561 unsigned long tx_buf_mapped;
562 unsigned long tx_timeouts;
563 unsigned long rx_lost_in_ring;
564 };
565
566 struct rtl8139_private {
567 void *mmio_addr;
568 int drv_flags;
569 struct pci_dev *pci_dev;
570 u32 pci_state[16];
571 u32 msg_enable;
572 struct net_device_stats stats;
573 unsigned char *rx_ring;
574 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
575 unsigned int tx_flag;
576 unsigned long cur_tx;
577 unsigned long dirty_tx;
578 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
579 unsigned char *tx_bufs; /* Tx bounce buffer region. */
580 dma_addr_t rx_ring_dma;
581 dma_addr_t tx_bufs_dma;
582 signed char phys[4]; /* MII device addresses. */
583 char twistie, twist_row, twist_col; /* Twister tune state. */
584 unsigned int default_port:4; /* Last dev->if_port value. */
585 spinlock_t lock;
586 chip_t chipset;
587 pid_t thr_pid;
588 wait_queue_head_t thr_wait;
589 struct completion thr_exited;
590 u32 rx_config;
591 struct rtl_extra_stats xstats;
592 int time_to_die;
593 struct mii_if_info mii;
594 unsigned int regs_len;
595 };
596
597 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
598 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
599 MODULE_LICENSE("GPL");
600
601 MODULE_PARM (multicast_filter_limit, "i");
602 MODULE_PARM (max_interrupt_work, "i");
603 MODULE_PARM (media, "1-" __MODULE_STRING(MAX_UNITS) "i");
604 MODULE_PARM (full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
605 MODULE_PARM (debug, "i");
606 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
607 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
608 MODULE_PARM_DESC (max_interrupt_work, "8139too maximum events handled per interrupt");
609 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
610 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
611
612 static int read_eeprom (void *ioaddr, int location, int addr_len);
613 static int rtl8139_open (struct net_device *dev);
614 static int mdio_read (struct net_device *dev, int phy_id, int location);
615 static void mdio_write (struct net_device *dev, int phy_id, int location,
616 int val);
617 static void rtl8139_start_thread(struct net_device *dev);
618 static void rtl8139_tx_timeout (struct net_device *dev);
619 static void rtl8139_init_ring (struct net_device *dev);
620 static int rtl8139_start_xmit (struct sk_buff *skb,
621 struct net_device *dev);
622 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
623 struct pt_regs *regs);
624 static int rtl8139_close (struct net_device *dev);
625 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
626 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
627 static void rtl8139_set_rx_mode (struct net_device *dev);
628 static void __set_rx_mode (struct net_device *dev);
629 static void rtl8139_hw_start (struct net_device *dev);
630 static struct ethtool_ops rtl8139_ethtool_ops;
631
632 #ifdef USE_IO_OPS
633
634 #define RTL_R8(reg) inb (((unsigned long)ioaddr) + (reg))
635 #define RTL_R16(reg) inw (((unsigned long)ioaddr) + (reg))
636 #define RTL_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
637 #define RTL_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
638 #define RTL_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
639 #define RTL_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
640 #define RTL_W8_F RTL_W8
641 #define RTL_W16_F RTL_W16
642 #define RTL_W32_F RTL_W32
643 #undef readb
644 #undef readw
645 #undef readl
646 #undef writeb
647 #undef writew
648 #undef writel
649 #define readb(addr) inb((unsigned long)(addr))
650 #define readw(addr) inw((unsigned long)(addr))
651 #define readl(addr) inl((unsigned long)(addr))
652 #define writeb(val,addr) outb((val),(unsigned long)(addr))
653 #define writew(val,addr) outw((val),(unsigned long)(addr))
654 #define writel(val,addr) outl((val),(unsigned long)(addr))
655
656 #else
657
658 /* write MMIO register, with flush */
659 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
660 #define RTL_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
661 #define RTL_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
662 #define RTL_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
663
664
665 #define MMIO_FLUSH_AUDIT_COMPLETE 1
666 #if MMIO_FLUSH_AUDIT_COMPLETE
667
668 /* write MMIO register */
669 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
670 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
671 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
672
673 #else
674
675 /* write MMIO register, then flush */
676 #define RTL_W8 RTL_W8_F
677 #define RTL_W16 RTL_W16_F
678 #define RTL_W32 RTL_W32_F
679
680 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
681
682 /* read MMIO register */
683 #define RTL_R8(reg) readb (ioaddr + (reg))
684 #define RTL_R16(reg) readw (ioaddr + (reg))
685 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
686
687 #endif /* USE_IO_OPS */
688
689
690 static const u16 rtl8139_intr_mask =
691 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
692 TxErr | TxOK | RxErr | RxOK;
693
694 #ifdef USE_BUF16K
695 static const unsigned int rtl8139_rx_config =
696 RxCfgRcv16K | RxNoWrap |
697 (RX_FIFO_THRESH << RxCfgFIFOShift) |
698 (RX_DMA_BURST << RxCfgDMAShift);
699 #else
700 static const unsigned int rtl8139_rx_config =
701 RxCfgRcv32K | RxNoWrap |
702 (RX_FIFO_THRESH << RxCfgFIFOShift) |
703 (RX_DMA_BURST << RxCfgDMAShift);
704 #endif
705
706 static const unsigned int rtl8139_tx_config =
707 (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
708
__rtl8139_cleanup_dev(struct net_device * dev)709 static void __rtl8139_cleanup_dev (struct net_device *dev)
710 {
711 struct rtl8139_private *tp;
712 struct pci_dev *pdev;
713
714 assert (dev != NULL);
715 assert (dev->priv != NULL);
716
717 tp = dev->priv;
718 assert (tp->pci_dev != NULL);
719 pdev = tp->pci_dev;
720
721 #ifndef USE_IO_OPS
722 if (tp->mmio_addr)
723 iounmap (tp->mmio_addr);
724 #endif /* !USE_IO_OPS */
725
726 /* it's ok to call this even if we have no regions to free */
727 pci_release_regions (pdev);
728
729 kfree (dev);
730
731 pci_set_drvdata (pdev, NULL);
732 }
733
734
rtl8139_chip_reset(void * ioaddr)735 static void rtl8139_chip_reset (void *ioaddr)
736 {
737 int i;
738
739 /* Soft reset the chip. */
740 RTL_W8 (ChipCmd, CmdReset);
741
742 /* Check that the chip has finished the reset. */
743 for (i = 1000; i > 0; i--) {
744 barrier();
745 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
746 break;
747 udelay (10);
748 }
749 }
750
751
rtl8139_init_board(struct pci_dev * pdev,struct net_device ** dev_out)752 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
753 struct net_device **dev_out)
754 {
755 void *ioaddr;
756 struct net_device *dev;
757 struct rtl8139_private *tp;
758 u8 tmp8;
759 int rc;
760 unsigned int i;
761 u32 pio_start, pio_end, pio_flags, pio_len;
762 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
763 u32 version;
764
765 assert (pdev != NULL);
766
767 *dev_out = NULL;
768
769 /* dev and dev->priv zeroed in alloc_etherdev */
770 dev = alloc_etherdev (sizeof (*tp));
771 if (dev == NULL) {
772 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pci_name(pdev));
773 return -ENOMEM;
774 }
775 SET_MODULE_OWNER(dev);
776
777 tp = dev->priv;
778 tp->pci_dev = pdev;
779
780 /* enable device (incl. PCI PM wakeup and hotplug setup) */
781 rc = pci_enable_device (pdev);
782 if (rc)
783 goto err_out;
784
785 pio_start = pci_resource_start (pdev, 0);
786 pio_end = pci_resource_end (pdev, 0);
787 pio_flags = pci_resource_flags (pdev, 0);
788 pio_len = pci_resource_len (pdev, 0);
789
790 mmio_start = pci_resource_start (pdev, 1);
791 mmio_end = pci_resource_end (pdev, 1);
792 mmio_flags = pci_resource_flags (pdev, 1);
793 mmio_len = pci_resource_len (pdev, 1);
794
795 /* set this immediately, we need to know before
796 * we talk to the chip directly */
797 DPRINTK("PIO region size == 0x%02X\n", pio_len);
798 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
799
800 #ifdef USE_IO_OPS
801 /* make sure PCI base addr 0 is PIO */
802 if (!(pio_flags & IORESOURCE_IO)) {
803 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pci_name(pdev));
804 rc = -ENODEV;
805 goto err_out;
806 }
807 /* check for weird/broken PCI region reporting */
808 if (pio_len < RTL_MIN_IO_SIZE) {
809 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pci_name(pdev));
810 rc = -ENODEV;
811 goto err_out;
812 }
813 #else
814 /* make sure PCI base addr 1 is MMIO */
815 if (!(mmio_flags & IORESOURCE_MEM)) {
816 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pci_name(pdev));
817 rc = -ENODEV;
818 goto err_out;
819 }
820 if (mmio_len < RTL_MIN_IO_SIZE) {
821 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pci_name(pdev));
822 rc = -ENODEV;
823 goto err_out;
824 }
825 #endif
826
827 rc = pci_request_regions (pdev, "8139too");
828 if (rc)
829 goto err_out;
830
831 /* enable PCI bus-mastering */
832 pci_set_master (pdev);
833
834 #ifdef USE_IO_OPS
835 ioaddr = (void *) pio_start;
836 dev->base_addr = pio_start;
837 tp->mmio_addr = ioaddr;
838 tp->regs_len = pio_len;
839 #else
840 /* ioremap MMIO region */
841 ioaddr = ioremap (mmio_start, mmio_len);
842 if (ioaddr == NULL) {
843 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev));
844 rc = -EIO;
845 goto err_out;
846 }
847 dev->base_addr = (long) ioaddr;
848 tp->mmio_addr = ioaddr;
849 tp->regs_len = mmio_len;
850 #endif /* USE_IO_OPS */
851
852 /* Bring old chips out of low-power mode. */
853 RTL_W8 (HltClk, 'R');
854
855 /* check for missing/broken hardware */
856 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
857 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
858 pci_name(pdev));
859 rc = -EIO;
860 goto err_out;
861 }
862
863 /* identify chip attached to board */
864 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
865 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
866 if (version == rtl_chip_info[i].version) {
867 tp->chipset = i;
868 goto match;
869 }
870
871 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
872 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
873 pci_name(pdev));
874 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pci_name(pdev), RTL_R32 (TxConfig));
875 tp->chipset = 0;
876
877 match:
878 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
879 tmp,
880 tp->chipset,
881 rtl_chip_info[tp->chipset].name);
882
883 if (tp->chipset >= CH_8139B) {
884 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
885 DPRINTK("PCI PM wakeup\n");
886 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
887 (tmp8 & LWAKE))
888 new_tmp8 &= ~LWAKE;
889 new_tmp8 |= Cfg1_PM_Enable;
890 if (new_tmp8 != tmp8) {
891 RTL_W8 (Cfg9346, Cfg9346_Unlock);
892 RTL_W8 (Config1, tmp8);
893 RTL_W8 (Cfg9346, Cfg9346_Lock);
894 }
895 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
896 tmp8 = RTL_R8 (Config4);
897 if (tmp8 & LWPTN) {
898 RTL_W8 (Cfg9346, Cfg9346_Unlock);
899 RTL_W8 (Config4, tmp8 & ~LWPTN);
900 RTL_W8 (Cfg9346, Cfg9346_Lock);
901 }
902 }
903 } else {
904 DPRINTK("Old chip wakeup\n");
905 tmp8 = RTL_R8 (Config1);
906 tmp8 &= ~(SLEEP | PWRDN);
907 RTL_W8 (Config1, tmp8);
908 }
909
910 rtl8139_chip_reset (ioaddr);
911
912 *dev_out = dev;
913 return 0;
914
915 err_out:
916 __rtl8139_cleanup_dev (dev);
917 return rc;
918 }
919
920
rtl8139_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)921 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
922 const struct pci_device_id *ent)
923 {
924 struct net_device *dev = NULL;
925 struct rtl8139_private *tp;
926 int i, addr_len, option;
927 void *ioaddr;
928 static int board_idx = -1;
929 u8 pci_rev;
930
931 assert (pdev != NULL);
932 assert (ent != NULL);
933
934 board_idx++;
935
936 /* when we're built into the kernel, the driver version message
937 * is only printed if at least one 8139 board has been found
938 */
939 #ifndef MODULE
940 {
941 static int printed_version;
942 if (!printed_version++)
943 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
944 }
945 #endif
946
947 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
948
949 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
950 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
951 printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
952 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
953 printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
954 }
955
956 i = rtl8139_init_board (pdev, &dev);
957 if (i < 0)
958 return i;
959
960 assert (dev != NULL);
961 tp = dev->priv;
962 assert (tp != NULL);
963 ioaddr = tp->mmio_addr;
964 assert (ioaddr != NULL);
965
966 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
967 for (i = 0; i < 3; i++)
968 ((u16 *) (dev->dev_addr))[i] =
969 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
970
971 /* The Rtl8139-specific entries in the device structure. */
972 dev->open = rtl8139_open;
973 dev->hard_start_xmit = rtl8139_start_xmit;
974 dev->stop = rtl8139_close;
975 dev->get_stats = rtl8139_get_stats;
976 dev->set_multicast_list = rtl8139_set_rx_mode;
977 dev->do_ioctl = netdev_ioctl;
978 dev->ethtool_ops = &rtl8139_ethtool_ops;
979 dev->tx_timeout = rtl8139_tx_timeout;
980 dev->watchdog_timeo = TX_TIMEOUT;
981
982 /* note: the hardware is not capable of sg/csum/highdma, however
983 * through the use of skb_copy_and_csum_dev we enable these
984 * features
985 */
986 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
987
988 dev->irq = pdev->irq;
989
990 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
991 tp = dev->priv;
992
993 /* note: tp->chipset set in rtl8139_init_board */
994 tp->drv_flags = board_info[ent->driver_data].hw_flags;
995 tp->mmio_addr = ioaddr;
996 tp->msg_enable =
997 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
998 spin_lock_init (&tp->lock);
999 init_waitqueue_head (&tp->thr_wait);
1000 init_completion (&tp->thr_exited);
1001 tp->mii.dev = dev;
1002 tp->mii.mdio_read = mdio_read;
1003 tp->mii.mdio_write = mdio_write;
1004 tp->mii.phy_id_mask = 0x3f;
1005 tp->mii.reg_num_mask = 0x1f;
1006
1007 /* dev is fully set up and ready to use now */
1008 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1009 i = register_netdev (dev);
1010 if (i) goto err_out;
1011
1012 pci_set_drvdata (pdev, dev);
1013
1014 printk (KERN_INFO "%s: %s at 0x%lx, "
1015 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1016 "IRQ %d\n",
1017 dev->name,
1018 board_info[ent->driver_data].name,
1019 dev->base_addr,
1020 dev->dev_addr[0], dev->dev_addr[1],
1021 dev->dev_addr[2], dev->dev_addr[3],
1022 dev->dev_addr[4], dev->dev_addr[5],
1023 dev->irq);
1024
1025 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1026 dev->name, rtl_chip_info[tp->chipset].name);
1027
1028 /* Find the connected MII xcvrs.
1029 Doing this in open() would allow detecting external xcvrs later, but
1030 takes too much time. */
1031 #ifdef CONFIG_8139TOO_8129
1032 if (tp->drv_flags & HAS_MII_XCVR) {
1033 int phy, phy_idx = 0;
1034 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1035 int mii_status = mdio_read(dev, phy, 1);
1036 if (mii_status != 0xffff && mii_status != 0x0000) {
1037 u16 advertising = mdio_read(dev, phy, 4);
1038 tp->phys[phy_idx++] = phy;
1039 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1040 "advertising %4.4x.\n",
1041 dev->name, phy, mii_status, advertising);
1042 }
1043 }
1044 if (phy_idx == 0) {
1045 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1046 "transceiver.\n",
1047 dev->name);
1048 tp->phys[0] = 32;
1049 }
1050 } else
1051 #endif
1052 tp->phys[0] = 32;
1053 tp->mii.phy_id = tp->phys[0];
1054
1055 /* The lower four bits are the media type. */
1056 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1057 if (option > 0) {
1058 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1059 tp->default_port = option & 0xFF;
1060 if (tp->default_port)
1061 tp->mii.force_media = 1;
1062 }
1063 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1064 tp->mii.full_duplex = full_duplex[board_idx];
1065 if (tp->mii.full_duplex) {
1066 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1067 /* Changing the MII-advertised media because might prevent
1068 re-connection. */
1069 tp->mii.force_media = 1;
1070 }
1071 if (tp->default_port) {
1072 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1073 (option & 0x20 ? 100 : 10),
1074 (option & 0x10 ? "full" : "half"));
1075 mdio_write(dev, tp->phys[0], 0,
1076 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1077 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1078 }
1079
1080 /* Put the chip into low-power mode. */
1081 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1082 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1083
1084 return 0;
1085
1086 err_out:
1087 __rtl8139_cleanup_dev (dev);
1088 return i;
1089 }
1090
1091
rtl8139_remove_one(struct pci_dev * pdev)1092 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1093 {
1094 struct net_device *dev = pci_get_drvdata (pdev);
1095 struct rtl8139_private *np;
1096
1097 assert (dev != NULL);
1098 np = dev->priv;
1099 assert (np != NULL);
1100
1101 unregister_netdev (dev);
1102
1103 __rtl8139_cleanup_dev (dev);
1104 }
1105
1106
1107 /* Serial EEPROM section. */
1108
1109 /* EEPROM_Ctrl bits. */
1110 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1111 #define EE_CS 0x08 /* EEPROM chip select. */
1112 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1113 #define EE_WRITE_0 0x00
1114 #define EE_WRITE_1 0x02
1115 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1116 #define EE_ENB (0x80 | EE_CS)
1117
1118 /* Delay between EEPROM clock transitions.
1119 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1120 */
1121
1122 #define eeprom_delay() readl(ee_addr)
1123
1124 /* The EEPROM commands include the alway-set leading bit. */
1125 #define EE_WRITE_CMD (5)
1126 #define EE_READ_CMD (6)
1127 #define EE_ERASE_CMD (7)
1128
read_eeprom(void * ioaddr,int location,int addr_len)1129 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
1130 {
1131 int i;
1132 unsigned retval = 0;
1133 void *ee_addr = ioaddr + Cfg9346;
1134 int read_cmd = location | (EE_READ_CMD << addr_len);
1135
1136 writeb (EE_ENB & ~EE_CS, ee_addr);
1137 writeb (EE_ENB, ee_addr);
1138 eeprom_delay ();
1139
1140 /* Shift the read command bits out. */
1141 for (i = 4 + addr_len; i >= 0; i--) {
1142 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1143 writeb (EE_ENB | dataval, ee_addr);
1144 eeprom_delay ();
1145 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1146 eeprom_delay ();
1147 }
1148 writeb (EE_ENB, ee_addr);
1149 eeprom_delay ();
1150
1151 for (i = 16; i > 0; i--) {
1152 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1153 eeprom_delay ();
1154 retval =
1155 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1156 0);
1157 writeb (EE_ENB, ee_addr);
1158 eeprom_delay ();
1159 }
1160
1161 /* Terminate the EEPROM access. */
1162 writeb (~EE_CS, ee_addr);
1163 eeprom_delay ();
1164
1165 return retval;
1166 }
1167
1168 /* MII serial management: mostly bogus for now. */
1169 /* Read and write the MII management registers using software-generated
1170 serial MDIO protocol.
1171 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1172 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1173 "overclocking" issues. */
1174 #define MDIO_DIR 0x80
1175 #define MDIO_DATA_OUT 0x04
1176 #define MDIO_DATA_IN 0x02
1177 #define MDIO_CLK 0x01
1178 #define MDIO_WRITE0 (MDIO_DIR)
1179 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1180
1181 #define mdio_delay(mdio_addr) readb(mdio_addr)
1182
1183
1184 static char mii_2_8139_map[8] = {
1185 BasicModeCtrl,
1186 BasicModeStatus,
1187 0,
1188 0,
1189 NWayAdvert,
1190 NWayLPAR,
1191 NWayExpansion,
1192 0
1193 };
1194
1195
1196 #ifdef CONFIG_8139TOO_8129
1197 /* Syncronize the MII management interface by shifting 32 one bits out. */
mdio_sync(void * mdio_addr)1198 static void mdio_sync (void *mdio_addr)
1199 {
1200 int i;
1201
1202 for (i = 32; i >= 0; i--) {
1203 writeb (MDIO_WRITE1, mdio_addr);
1204 mdio_delay (mdio_addr);
1205 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
1206 mdio_delay (mdio_addr);
1207 }
1208 }
1209 #endif
1210
mdio_read(struct net_device * dev,int phy_id,int location)1211 static int mdio_read (struct net_device *dev, int phy_id, int location)
1212 {
1213 struct rtl8139_private *tp = dev->priv;
1214 int retval = 0;
1215 #ifdef CONFIG_8139TOO_8129
1216 void *mdio_addr = tp->mmio_addr + Config4;
1217 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1218 int i;
1219 #endif
1220
1221 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1222 return location < 8 && mii_2_8139_map[location] ?
1223 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1224 }
1225
1226 #ifdef CONFIG_8139TOO_8129
1227 mdio_sync (mdio_addr);
1228 /* Shift the read command bits out. */
1229 for (i = 15; i >= 0; i--) {
1230 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1231
1232 writeb (MDIO_DIR | dataval, mdio_addr);
1233 mdio_delay (mdio_addr);
1234 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1235 mdio_delay (mdio_addr);
1236 }
1237
1238 /* Read the two transition, 16 data, and wire-idle bits. */
1239 for (i = 19; i > 0; i--) {
1240 writeb (0, mdio_addr);
1241 mdio_delay (mdio_addr);
1242 retval = (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1 : 0);
1243 writeb (MDIO_CLK, mdio_addr);
1244 mdio_delay (mdio_addr);
1245 }
1246 #endif
1247
1248 return (retval >> 1) & 0xffff;
1249 }
1250
1251
mdio_write(struct net_device * dev,int phy_id,int location,int value)1252 static void mdio_write (struct net_device *dev, int phy_id, int location,
1253 int value)
1254 {
1255 struct rtl8139_private *tp = dev->priv;
1256 #ifdef CONFIG_8139TOO_8129
1257 void *mdio_addr = tp->mmio_addr + Config4;
1258 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1259 int i;
1260 #endif
1261
1262 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1263 void *ioaddr = tp->mmio_addr;
1264 if (location == 0) {
1265 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1266 RTL_W16 (BasicModeCtrl, value);
1267 RTL_W8 (Cfg9346, Cfg9346_Lock);
1268 } else if (location < 8 && mii_2_8139_map[location])
1269 RTL_W16 (mii_2_8139_map[location], value);
1270 return;
1271 }
1272
1273 #ifdef CONFIG_8139TOO_8129
1274 mdio_sync (mdio_addr);
1275
1276 /* Shift the command bits out. */
1277 for (i = 31; i >= 0; i--) {
1278 int dataval =
1279 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1280 writeb (dataval, mdio_addr);
1281 mdio_delay (mdio_addr);
1282 writeb (dataval | MDIO_CLK, mdio_addr);
1283 mdio_delay (mdio_addr);
1284 }
1285 /* Clear out extra bits. */
1286 for (i = 2; i > 0; i--) {
1287 writeb (0, mdio_addr);
1288 mdio_delay (mdio_addr);
1289 writeb (MDIO_CLK, mdio_addr);
1290 mdio_delay (mdio_addr);
1291 }
1292 #endif
1293 }
1294
1295
rtl8139_open(struct net_device * dev)1296 static int rtl8139_open (struct net_device *dev)
1297 {
1298 struct rtl8139_private *tp = dev->priv;
1299 int retval;
1300 void *ioaddr = tp->mmio_addr;
1301
1302 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1303 if (retval)
1304 return retval;
1305
1306 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1307 &tp->tx_bufs_dma);
1308 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1309 &tp->rx_ring_dma);
1310 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1311 free_irq(dev->irq, dev);
1312
1313 if (tp->tx_bufs)
1314 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1315 tp->tx_bufs, tp->tx_bufs_dma);
1316 if (tp->rx_ring)
1317 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1318 tp->rx_ring, tp->rx_ring_dma);
1319
1320 return -ENOMEM;
1321
1322 }
1323
1324 tp->mii.full_duplex = tp->mii.force_media;
1325 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1326
1327 rtl8139_init_ring (dev);
1328 rtl8139_hw_start (dev);
1329
1330 if (netif_msg_ifup(tp))
1331 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#lx IRQ %d"
1332 " GP Pins %2.2x %s-duplex.\n",
1333 dev->name, pci_resource_start (tp->pci_dev, 1),
1334 dev->irq, RTL_R8 (MediaStatus),
1335 tp->mii.full_duplex ? "full" : "half");
1336
1337 rtl8139_start_thread(dev);
1338
1339 return 0;
1340 }
1341
1342
rtl_check_media(struct net_device * dev,unsigned int init_media)1343 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1344 {
1345 struct rtl8139_private *tp = dev->priv;
1346
1347 if (tp->phys[0] >= 0) {
1348 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1349 }
1350 }
1351
1352 /* Start the hardware at open or resume. */
rtl8139_hw_start(struct net_device * dev)1353 static void rtl8139_hw_start (struct net_device *dev)
1354 {
1355 struct rtl8139_private *tp = dev->priv;
1356 void *ioaddr = tp->mmio_addr;
1357 u32 i;
1358 u8 tmp;
1359
1360 /* Bring old chips out of low-power mode. */
1361 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1362 RTL_W8 (HltClk, 'R');
1363
1364 rtl8139_chip_reset (ioaddr);
1365
1366 /* unlock Config[01234] and BMCR register writes */
1367 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1368 /* Restore our idea of the MAC address. */
1369 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1370 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1371
1372 /* Must enable Tx/Rx before setting transfer thresholds! */
1373 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1374
1375 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1376 RTL_W32 (RxConfig, tp->rx_config);
1377
1378 /* Check this value: the documentation for IFG contradicts ifself. */
1379 RTL_W32 (TxConfig, rtl8139_tx_config);
1380
1381 tp->cur_rx = 0;
1382
1383 rtl_check_media (dev, 1);
1384
1385 if (tp->chipset >= CH_8139B) {
1386 /* Disable magic packet scanning, which is enabled
1387 * when PM is enabled in Config1. It can be reenabled
1388 * via ETHTOOL_SWOL if desired. */
1389 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1390 }
1391
1392 DPRINTK("init buffer addresses\n");
1393
1394 /* Lock Config[01234] and BMCR register writes */
1395 RTL_W8 (Cfg9346, Cfg9346_Lock);
1396
1397 /* init Rx ring buffer DMA address */
1398 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1399
1400 /* init Tx buffer DMA addresses */
1401 for (i = 0; i < NUM_TX_DESC; i++)
1402 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1403
1404 RTL_W32 (RxMissed, 0);
1405
1406 rtl8139_set_rx_mode (dev);
1407
1408 /* no early-rx interrupts */
1409 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1410
1411 /* make sure RxTx has started */
1412 tmp = RTL_R8 (ChipCmd);
1413 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1414 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1415
1416 /* Enable all known interrupts by setting the interrupt mask. */
1417 RTL_W16 (IntrMask, rtl8139_intr_mask);
1418
1419 netif_start_queue (dev);
1420 }
1421
1422
1423 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
rtl8139_init_ring(struct net_device * dev)1424 static void rtl8139_init_ring (struct net_device *dev)
1425 {
1426 struct rtl8139_private *tp = dev->priv;
1427 int i;
1428
1429 tp->cur_rx = 0;
1430 tp->cur_tx = 0;
1431 tp->dirty_tx = 0;
1432
1433 for (i = 0; i < NUM_TX_DESC; i++)
1434 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1435 }
1436
1437
1438 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1439 static int next_tick = 3 * HZ;
1440
1441 #ifndef CONFIG_8139TOO_TUNE_TWISTER
rtl8139_tune_twister(struct net_device * dev,struct rtl8139_private * tp)1442 static inline void rtl8139_tune_twister (struct net_device *dev,
1443 struct rtl8139_private *tp) {}
1444 #else
1445 enum TwisterParamVals {
1446 PARA78_default = 0x78fa8388,
1447 PARA7c_default = 0xcb38de43, /* param[0][3] */
1448 PARA7c_xxx = 0xcb38de43,
1449 };
1450
1451 static const unsigned long param[4][4] = {
1452 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1453 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1454 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1455 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1456 };
1457
rtl8139_tune_twister(struct net_device * dev,struct rtl8139_private * tp)1458 static void rtl8139_tune_twister (struct net_device *dev,
1459 struct rtl8139_private *tp)
1460 {
1461 int linkcase;
1462 void *ioaddr = tp->mmio_addr;
1463
1464 /* This is a complicated state machine to configure the "twister" for
1465 impedance/echos based on the cable length.
1466 All of this is magic and undocumented.
1467 */
1468 switch (tp->twistie) {
1469 case 1:
1470 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1471 /* We have link beat, let us tune the twister. */
1472 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1473 tp->twistie = 2; /* Change to state 2. */
1474 next_tick = HZ / 10;
1475 } else {
1476 /* Just put in some reasonable defaults for when beat returns. */
1477 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1478 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1479 RTL_W32 (PARA78, PARA78_default);
1480 RTL_W32 (PARA7c, PARA7c_default);
1481 tp->twistie = 0; /* Bail from future actions. */
1482 }
1483 break;
1484 case 2:
1485 /* Read how long it took to hear the echo. */
1486 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1487 if (linkcase == 0x7000)
1488 tp->twist_row = 3;
1489 else if (linkcase == 0x3000)
1490 tp->twist_row = 2;
1491 else if (linkcase == 0x1000)
1492 tp->twist_row = 1;
1493 else
1494 tp->twist_row = 0;
1495 tp->twist_col = 0;
1496 tp->twistie = 3; /* Change to state 2. */
1497 next_tick = HZ / 10;
1498 break;
1499 case 3:
1500 /* Put out four tuning parameters, one per 100msec. */
1501 if (tp->twist_col == 0)
1502 RTL_W16 (FIFOTMS, 0);
1503 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1504 [(int) tp->twist_col]);
1505 next_tick = HZ / 10;
1506 if (++tp->twist_col >= 4) {
1507 /* For short cables we are done.
1508 For long cables (row == 3) check for mistune. */
1509 tp->twistie =
1510 (tp->twist_row == 3) ? 4 : 0;
1511 }
1512 break;
1513 case 4:
1514 /* Special case for long cables: check for mistune. */
1515 if ((RTL_R16 (CSCR) &
1516 CSCR_LinkStatusBits) == 0x7000) {
1517 tp->twistie = 0;
1518 break;
1519 } else {
1520 RTL_W32 (PARA7c, 0xfb38de03);
1521 tp->twistie = 5;
1522 next_tick = HZ / 10;
1523 }
1524 break;
1525 case 5:
1526 /* Retune for shorter cable (column 2). */
1527 RTL_W32 (FIFOTMS, 0x20);
1528 RTL_W32 (PARA78, PARA78_default);
1529 RTL_W32 (PARA7c, PARA7c_default);
1530 RTL_W32 (FIFOTMS, 0x00);
1531 tp->twist_row = 2;
1532 tp->twist_col = 0;
1533 tp->twistie = 3;
1534 next_tick = HZ / 10;
1535 break;
1536
1537 default:
1538 /* do nothing */
1539 break;
1540 }
1541 }
1542 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1543
rtl8139_thread_iter(struct net_device * dev,struct rtl8139_private * tp,void * ioaddr)1544 static inline void rtl8139_thread_iter (struct net_device *dev,
1545 struct rtl8139_private *tp,
1546 void *ioaddr)
1547 {
1548 int mii_lpa;
1549
1550 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1551
1552 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1553 int duplex = (mii_lpa & LPA_100FULL)
1554 || (mii_lpa & 0x01C0) == 0x0040;
1555 if (tp->mii.full_duplex != duplex) {
1556 tp->mii.full_duplex = duplex;
1557
1558 if (mii_lpa) {
1559 printk (KERN_INFO
1560 "%s: Setting %s-duplex based on MII #%d link"
1561 " partner ability of %4.4x.\n",
1562 dev->name,
1563 tp->mii.full_duplex ? "full" : "half",
1564 tp->phys[0], mii_lpa);
1565 } else {
1566 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1567 dev->name);
1568 }
1569 #if 0
1570 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1571 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1572 RTL_W8 (Cfg9346, Cfg9346_Lock);
1573 #endif
1574 }
1575 }
1576
1577 next_tick = HZ * 60;
1578
1579 rtl8139_tune_twister (dev, tp);
1580
1581 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1582 dev->name, RTL_R16 (NWayLPAR));
1583 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1584 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1585 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1586 dev->name, RTL_R8 (Config0),
1587 RTL_R8 (Config1));
1588 }
1589
rtl8139_thread(void * data)1590 static int rtl8139_thread (void *data)
1591 {
1592 struct net_device *dev = data;
1593 struct rtl8139_private *tp = dev->priv;
1594 unsigned long timeout;
1595
1596 daemonize ();
1597 reparent_to_init();
1598 spin_lock_irq(¤t->sigmask_lock);
1599 sigemptyset(¤t->blocked);
1600 recalc_sigpending(current);
1601 spin_unlock_irq(¤t->sigmask_lock);
1602
1603 strncpy (current->comm, dev->name, sizeof(current->comm) - 1);
1604 current->comm[sizeof(current->comm) - 1] = '\0';
1605
1606 while (1) {
1607 timeout = next_tick;
1608 do {
1609 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
1610 } while (!signal_pending (current) && (timeout > 0));
1611
1612 if (signal_pending (current)) {
1613 spin_lock_irq(¤t->sigmask_lock);
1614 flush_signals(current);
1615 spin_unlock_irq(¤t->sigmask_lock);
1616 }
1617
1618 if (tp->time_to_die)
1619 break;
1620
1621 rtnl_lock ();
1622 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1623 rtnl_unlock ();
1624 }
1625
1626 complete_and_exit (&tp->thr_exited, 0);
1627 }
1628
rtl8139_start_thread(struct net_device * dev)1629 static void rtl8139_start_thread(struct net_device *dev)
1630 {
1631 struct rtl8139_private *tp = dev->priv;
1632
1633 tp->thr_pid = -1;
1634 tp->twistie = 0;
1635 tp->time_to_die = 0;
1636 if (tp->chipset == CH_8139_K)
1637 tp->twistie = 1;
1638 else if (tp->drv_flags & HAS_LNK_CHNG)
1639 return;
1640
1641 tp->thr_pid = kernel_thread(rtl8139_thread, dev, CLONE_FS|CLONE_FILES);
1642 if (tp->thr_pid < 0) {
1643 printk (KERN_WARNING "%s: unable to start kernel thread\n",
1644 dev->name);
1645 }
1646 }
1647
rtl8139_tx_clear(struct rtl8139_private * tp)1648 static void rtl8139_tx_clear (struct rtl8139_private *tp)
1649 {
1650 tp->cur_tx = 0;
1651 tp->dirty_tx = 0;
1652
1653 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1654 }
1655
1656
rtl8139_tx_timeout(struct net_device * dev)1657 static void rtl8139_tx_timeout (struct net_device *dev)
1658 {
1659 struct rtl8139_private *tp = dev->priv;
1660 void *ioaddr = tp->mmio_addr;
1661 int i;
1662 u8 tmp8;
1663 unsigned long flags;
1664
1665 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1666 "media %2.2x.\n", dev->name,
1667 RTL_R8 (ChipCmd),
1668 RTL_R16 (IntrStatus),
1669 RTL_R8 (MediaStatus));
1670
1671 tp->xstats.tx_timeouts++;
1672
1673 /* disable Tx ASAP, if not already */
1674 tmp8 = RTL_R8 (ChipCmd);
1675 if (tmp8 & CmdTxEnb)
1676 RTL_W8 (ChipCmd, CmdRxEnb);
1677
1678 /* Disable interrupts by clearing the interrupt mask. */
1679 RTL_W16 (IntrMask, 0x0000);
1680
1681 /* Emit info to figure out what went wrong. */
1682 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1683 dev->name, tp->cur_tx, tp->dirty_tx);
1684 for (i = 0; i < NUM_TX_DESC; i++)
1685 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1686 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1687 i == tp->dirty_tx % NUM_TX_DESC ?
1688 " (queue head)" : "");
1689
1690 /* Stop a shared interrupt from scavenging while we are. */
1691 spin_lock_irqsave (&tp->lock, flags);
1692 rtl8139_tx_clear (tp);
1693 spin_unlock_irqrestore (&tp->lock, flags);
1694
1695 /* ...and finally, reset everything */
1696 rtl8139_hw_start (dev);
1697
1698 netif_wake_queue (dev);
1699 }
1700
1701
rtl8139_start_xmit(struct sk_buff * skb,struct net_device * dev)1702 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1703 {
1704 struct rtl8139_private *tp = dev->priv;
1705 void *ioaddr = tp->mmio_addr;
1706 unsigned int entry;
1707 unsigned int len = skb->len;
1708
1709 /* Calculate the next Tx descriptor entry. */
1710 entry = tp->cur_tx % NUM_TX_DESC;
1711
1712 if (likely(len < TX_BUF_SIZE)) {
1713 if (len < ETH_ZLEN)
1714 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1715 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1716 dev_kfree_skb(skb);
1717 } else {
1718 dev_kfree_skb(skb);
1719 tp->stats.tx_dropped++;
1720 return 0;
1721 }
1722
1723 /* Note: the chip doesn't have auto-pad! */
1724 spin_lock_irq(&tp->lock);
1725 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1726 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1727
1728 dev->trans_start = jiffies;
1729
1730 tp->cur_tx++;
1731 wmb();
1732
1733 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1734 netif_stop_queue (dev);
1735 spin_unlock_irq(&tp->lock);
1736
1737 if (netif_msg_tx_queued(tp))
1738 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1739 dev->name, len, entry);
1740
1741 return 0;
1742 }
1743
1744
rtl8139_tx_interrupt(struct net_device * dev,struct rtl8139_private * tp,void * ioaddr)1745 static void rtl8139_tx_interrupt (struct net_device *dev,
1746 struct rtl8139_private *tp,
1747 void *ioaddr)
1748 {
1749 unsigned long dirty_tx, tx_left;
1750
1751 assert (dev != NULL);
1752 assert (tp != NULL);
1753 assert (ioaddr != NULL);
1754
1755 dirty_tx = tp->dirty_tx;
1756 tx_left = tp->cur_tx - dirty_tx;
1757 while (tx_left > 0) {
1758 int entry = dirty_tx % NUM_TX_DESC;
1759 int txstatus;
1760
1761 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1762
1763 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1764 break; /* It still hasn't been Txed */
1765
1766 /* Note: TxCarrierLost is always asserted at 100mbps. */
1767 if (txstatus & (TxOutOfWindow | TxAborted)) {
1768 /* There was an major error, log it. */
1769 if (netif_msg_tx_err(tp))
1770 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1771 dev->name, txstatus);
1772 tp->stats.tx_errors++;
1773 if (txstatus & TxAborted) {
1774 tp->stats.tx_aborted_errors++;
1775 RTL_W32 (TxConfig, TxClearAbt);
1776 RTL_W16 (IntrStatus, TxErr);
1777 wmb();
1778 }
1779 if (txstatus & TxCarrierLost)
1780 tp->stats.tx_carrier_errors++;
1781 if (txstatus & TxOutOfWindow)
1782 tp->stats.tx_window_errors++;
1783 } else {
1784 if (txstatus & TxUnderrun) {
1785 /* Add 64 to the Tx FIFO threshold. */
1786 if (tp->tx_flag < 0x00300000)
1787 tp->tx_flag += 0x00020000;
1788 tp->stats.tx_fifo_errors++;
1789 }
1790 tp->stats.collisions += (txstatus >> 24) & 15;
1791 tp->stats.tx_bytes += txstatus & 0x7ff;
1792 tp->stats.tx_packets++;
1793 }
1794
1795 dirty_tx++;
1796 tx_left--;
1797 }
1798
1799 #ifndef RTL8139_NDEBUG
1800 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1801 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1802 dev->name, dirty_tx, tp->cur_tx);
1803 dirty_tx += NUM_TX_DESC;
1804 }
1805 #endif /* RTL8139_NDEBUG */
1806
1807 /* only wake the queue if we did work, and the queue is stopped */
1808 if (tp->dirty_tx != dirty_tx) {
1809 tp->dirty_tx = dirty_tx;
1810 mb();
1811 if (netif_queue_stopped (dev))
1812 netif_wake_queue (dev);
1813 }
1814 }
1815
1816
1817 /* TODO: clean this up! Rx reset need not be this intensive */
rtl8139_rx_err(u32 rx_status,struct net_device * dev,struct rtl8139_private * tp,void * ioaddr)1818 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1819 struct rtl8139_private *tp, void *ioaddr)
1820 {
1821 u8 tmp8;
1822 #ifdef CONFIG_8139_OLD_RX_RESET
1823 int tmp_work;
1824 #endif
1825
1826 if (netif_msg_rx_err (tp))
1827 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1828 dev->name, rx_status);
1829 tp->stats.rx_errors++;
1830 if (!(rx_status & RxStatusOK)) {
1831 if (rx_status & RxTooLong) {
1832 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1833 dev->name, rx_status);
1834 /* A.C.: The chip hangs here. */
1835 }
1836 if (rx_status & (RxBadSymbol | RxBadAlign))
1837 tp->stats.rx_frame_errors++;
1838 if (rx_status & (RxRunt | RxTooLong))
1839 tp->stats.rx_length_errors++;
1840 if (rx_status & RxCRCErr)
1841 tp->stats.rx_crc_errors++;
1842 } else {
1843 tp->xstats.rx_lost_in_ring++;
1844 }
1845
1846 #ifndef CONFIG_8139_OLD_RX_RESET
1847 tmp8 = RTL_R8 (ChipCmd);
1848 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1849 RTL_W8 (ChipCmd, tmp8);
1850 RTL_W32 (RxConfig, tp->rx_config);
1851 tp->cur_rx = 0;
1852 #else
1853 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1854
1855 /* disable receive */
1856 RTL_W8_F (ChipCmd, CmdTxEnb);
1857 tmp_work = 200;
1858 while (--tmp_work > 0) {
1859 udelay(1);
1860 tmp8 = RTL_R8 (ChipCmd);
1861 if (!(tmp8 & CmdRxEnb))
1862 break;
1863 }
1864 if (tmp_work <= 0)
1865 printk (KERN_WARNING PFX "rx stop wait too long\n");
1866 /* restart receive */
1867 tmp_work = 200;
1868 while (--tmp_work > 0) {
1869 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1870 udelay(1);
1871 tmp8 = RTL_R8 (ChipCmd);
1872 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1873 break;
1874 }
1875 if (tmp_work <= 0)
1876 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1877
1878 /* and reinitialize all rx related registers */
1879 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1880 /* Must enable Tx/Rx before setting transfer thresholds! */
1881 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1882
1883 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1884 RTL_W32 (RxConfig, tp->rx_config);
1885 tp->cur_rx = 0;
1886
1887 DPRINTK("init buffer addresses\n");
1888
1889 /* Lock Config[01234] and BMCR register writes */
1890 RTL_W8 (Cfg9346, Cfg9346_Lock);
1891
1892 /* init Rx ring buffer DMA address */
1893 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1894
1895 /* A.C.: Reset the multicast list. */
1896 __set_rx_mode (dev);
1897 #endif
1898 }
1899
rtl8139_rx_interrupt(struct net_device * dev,struct rtl8139_private * tp,void * ioaddr)1900 static void rtl8139_rx_interrupt (struct net_device *dev,
1901 struct rtl8139_private *tp, void *ioaddr)
1902 {
1903 unsigned char *rx_ring;
1904 u16 cur_rx;
1905
1906 assert (dev != NULL);
1907 assert (tp != NULL);
1908 assert (ioaddr != NULL);
1909
1910 rx_ring = tp->rx_ring;
1911 cur_rx = tp->cur_rx;
1912
1913 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1914 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1915 RTL_R16 (RxBufAddr),
1916 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1917
1918 while ((RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1919 int ring_offset = cur_rx % RX_BUF_LEN;
1920 u32 rx_status;
1921 unsigned int rx_size;
1922 unsigned int pkt_size;
1923 struct sk_buff *skb;
1924
1925 rmb();
1926
1927 /* read size+status of next frame from DMA ring buffer */
1928 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1929 rx_size = rx_status >> 16;
1930 pkt_size = rx_size - 4;
1931
1932 if (netif_msg_rx_status(tp))
1933 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1934 " cur %4.4x.\n", dev->name, rx_status,
1935 rx_size, cur_rx);
1936 #if RTL8139_DEBUG > 2
1937 {
1938 int i;
1939 DPRINTK ("%s: Frame contents ", dev->name);
1940 for (i = 0; i < 70; i++)
1941 printk (" %2.2x",
1942 rx_ring[ring_offset + i]);
1943 printk (".\n");
1944 }
1945 #endif
1946
1947 /* Packet copy from FIFO still in progress.
1948 * Theoretically, this should never happen
1949 * since EarlyRx is disabled.
1950 */
1951 if (rx_size == 0xfff0) {
1952 tp->xstats.early_rx++;
1953 break;
1954 }
1955
1956 /* If Rx err or invalid rx_size/rx_status received
1957 * (which happens if we get lost in the ring),
1958 * Rx process gets reset, so we abort any further
1959 * Rx processing.
1960 */
1961 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1962 (rx_size < 8) ||
1963 (!(rx_status & RxStatusOK))) {
1964 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
1965 return;
1966 }
1967
1968 /* Malloc up new buffer, compatible with net-2e. */
1969 /* Omit the four octet CRC from the length. */
1970
1971 /* TODO: consider allocating skb's outside of
1972 * interrupt context, both to speed interrupt processing,
1973 * and also to reduce the chances of having to
1974 * drop packets here under memory pressure.
1975 */
1976
1977 skb = dev_alloc_skb (pkt_size + 2);
1978 if (skb) {
1979 skb->dev = dev;
1980 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1981
1982 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
1983 skb_put (skb, pkt_size);
1984
1985 skb->protocol = eth_type_trans (skb, dev);
1986 netif_rx (skb);
1987 dev->last_rx = jiffies;
1988 tp->stats.rx_bytes += pkt_size;
1989 tp->stats.rx_packets++;
1990 } else {
1991 printk (KERN_WARNING
1992 "%s: Memory squeeze, dropping packet.\n",
1993 dev->name);
1994 tp->stats.rx_dropped++;
1995 }
1996
1997 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1998 RTL_W16 (RxBufPtr, cur_rx - 16);
1999
2000 if (RTL_R16 (IntrStatus) & RxAckBits)
2001 RTL_W16_F (IntrStatus, RxAckBits);
2002 }
2003
2004 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2005 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2006 RTL_R16 (RxBufAddr),
2007 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2008
2009 tp->cur_rx = cur_rx;
2010 }
2011
2012
rtl8139_weird_interrupt(struct net_device * dev,struct rtl8139_private * tp,void * ioaddr,int status,int link_changed)2013 static void rtl8139_weird_interrupt (struct net_device *dev,
2014 struct rtl8139_private *tp,
2015 void *ioaddr,
2016 int status, int link_changed)
2017 {
2018 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2019 dev->name, status);
2020
2021 assert (dev != NULL);
2022 assert (tp != NULL);
2023 assert (ioaddr != NULL);
2024
2025 /* Update the error count. */
2026 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2027 RTL_W32 (RxMissed, 0);
2028
2029 if ((status & RxUnderrun) && link_changed &&
2030 (tp->drv_flags & HAS_LNK_CHNG)) {
2031 rtl_check_media(dev, 0);
2032 status &= ~RxUnderrun;
2033 }
2034
2035 /* XXX along with rtl8139_rx_err, are we double-counting errors? */
2036 if (status &
2037 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
2038 tp->stats.rx_errors++;
2039
2040 if (status & PCSTimeout)
2041 tp->stats.rx_length_errors++;
2042 if (status & (RxUnderrun | RxFIFOOver))
2043 tp->stats.rx_fifo_errors++;
2044 if (status & PCIErr) {
2045 u16 pci_cmd_status;
2046 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2047 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2048
2049 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2050 dev->name, pci_cmd_status);
2051 }
2052 }
2053
2054
2055 /* The interrupt handler does all of the Rx thread work and cleans up
2056 after the Tx thread. */
rtl8139_interrupt(int irq,void * dev_instance,struct pt_regs * regs)2057 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2058 struct pt_regs *regs)
2059 {
2060 struct net_device *dev = (struct net_device *) dev_instance;
2061 struct rtl8139_private *tp = dev->priv;
2062 int boguscnt = max_interrupt_work;
2063 void *ioaddr = tp->mmio_addr;
2064 int ackstat, status;
2065 int link_changed = 0; /* avoid bogus "uninit" warning */
2066 int handled = 0;
2067
2068 spin_lock (&tp->lock);
2069
2070 do {
2071 status = RTL_R16 (IntrStatus);
2072
2073 /* h/w no longer present (hotplug?) or major error, bail */
2074 if (status == 0xFFFF)
2075 break;
2076
2077 if ((status &
2078 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
2079 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
2080 break;
2081
2082 handled = 1;
2083
2084 /* Acknowledge all of the current interrupt sources ASAP, but
2085 an first get an additional status bit from CSCR. */
2086 if (status & RxUnderrun)
2087 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2088
2089 /* The chip takes special action when we clear RxAckBits,
2090 * so we clear them later in rtl8139_rx_interrupt
2091 */
2092 ackstat = status & ~(RxAckBits | TxErr);
2093 RTL_W16 (IntrStatus, ackstat);
2094
2095 if (netif_msg_intr(tp))
2096 printk (KERN_DEBUG "%s: interrupt status=%#4.4x ackstat=%#4.4x new intstat=%#4.4x.\n",
2097 dev->name, status, ackstat, RTL_R16 (IntrStatus));
2098
2099 if (netif_running (dev) && (status & RxAckBits))
2100 rtl8139_rx_interrupt (dev, tp, ioaddr);
2101
2102 /* Check uncommon events with one test. */
2103 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
2104 RxFIFOOver | RxErr))
2105 rtl8139_weird_interrupt (dev, tp, ioaddr,
2106 status, link_changed);
2107
2108 if (netif_running (dev) && (status & (TxOK | TxErr))) {
2109 rtl8139_tx_interrupt (dev, tp, ioaddr);
2110 if (status & TxErr)
2111 RTL_W16 (IntrStatus, TxErr);
2112 }
2113
2114 boguscnt--;
2115 } while (boguscnt > 0);
2116
2117 if (boguscnt <= 0) {
2118 printk (KERN_WARNING "%s: Too much work at interrupt, "
2119 "IntrStatus=0x%4.4x.\n", dev->name, status);
2120
2121 /* Clear all interrupt sources. */
2122 RTL_W16 (IntrStatus, 0xffff);
2123 }
2124
2125 spin_unlock (&tp->lock);
2126
2127 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2128 dev->name, RTL_R16 (IntrStatus));
2129 return IRQ_RETVAL(handled);
2130 }
2131
2132
rtl8139_close(struct net_device * dev)2133 static int rtl8139_close (struct net_device *dev)
2134 {
2135 struct rtl8139_private *tp = dev->priv;
2136 void *ioaddr = tp->mmio_addr;
2137 int ret = 0;
2138 unsigned long flags;
2139
2140 netif_stop_queue (dev);
2141
2142 if (tp->thr_pid >= 0) {
2143 tp->time_to_die = 1;
2144 wmb();
2145 ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2146 if (ret) {
2147 printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2148 return ret;
2149 }
2150 wait_for_completion (&tp->thr_exited);
2151 }
2152
2153 if (netif_msg_ifdown(tp))
2154 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2155 dev->name, RTL_R16 (IntrStatus));
2156
2157 spin_lock_irqsave (&tp->lock, flags);
2158
2159 /* Stop the chip's Tx and Rx DMA processes. */
2160 RTL_W8 (ChipCmd, 0);
2161
2162 /* Disable interrupts by clearing the interrupt mask. */
2163 RTL_W16 (IntrMask, 0);
2164
2165 /* Update the error counts. */
2166 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2167 RTL_W32 (RxMissed, 0);
2168
2169 spin_unlock_irqrestore (&tp->lock, flags);
2170
2171 synchronize_irq (); /* racy, but that's ok here */
2172 free_irq (dev->irq, dev);
2173
2174 rtl8139_tx_clear (tp);
2175
2176 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2177 tp->rx_ring, tp->rx_ring_dma);
2178 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2179 tp->tx_bufs, tp->tx_bufs_dma);
2180 tp->rx_ring = NULL;
2181 tp->tx_bufs = NULL;
2182
2183 /* Green! Put the chip in low-power mode. */
2184 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2185
2186 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2187 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2188
2189 return 0;
2190 }
2191
2192
2193 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2194 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2195 other threads or interrupts aren't messing with the 8139. */
rtl8139_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)2196 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2197 {
2198 struct rtl8139_private *np = dev->priv;
2199 void *ioaddr = np->mmio_addr;
2200
2201 spin_lock_irq(&np->lock);
2202 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2203 u8 cfg3 = RTL_R8 (Config3);
2204 u8 cfg5 = RTL_R8 (Config5);
2205
2206 wol->supported = WAKE_PHY | WAKE_MAGIC
2207 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2208
2209 wol->wolopts = 0;
2210 if (cfg3 & Cfg3_LinkUp)
2211 wol->wolopts |= WAKE_PHY;
2212 if (cfg3 & Cfg3_Magic)
2213 wol->wolopts |= WAKE_MAGIC;
2214 /* (KON)FIXME: See how netdev_set_wol() handles the
2215 following constants. */
2216 if (cfg5 & Cfg5_UWF)
2217 wol->wolopts |= WAKE_UCAST;
2218 if (cfg5 & Cfg5_MWF)
2219 wol->wolopts |= WAKE_MCAST;
2220 if (cfg5 & Cfg5_BWF)
2221 wol->wolopts |= WAKE_BCAST;
2222 }
2223 spin_unlock_irq(&np->lock);
2224 }
2225
2226
2227 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2228 that wol points to kernel memory and other threads or interrupts
2229 aren't messing with the 8139. */
rtl8139_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)2230 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2231 {
2232 struct rtl8139_private *np = dev->priv;
2233 void *ioaddr = np->mmio_addr;
2234 u32 support;
2235 u8 cfg3, cfg5;
2236
2237 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2238 ? (WAKE_PHY | WAKE_MAGIC
2239 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2240 : 0);
2241 if (wol->wolopts & ~support)
2242 return -EINVAL;
2243
2244 spin_lock_irq(&np->lock);
2245 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2246 if (wol->wolopts & WAKE_PHY)
2247 cfg3 |= Cfg3_LinkUp;
2248 if (wol->wolopts & WAKE_MAGIC)
2249 cfg3 |= Cfg3_Magic;
2250 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2251 RTL_W8 (Config3, cfg3);
2252 RTL_W8 (Cfg9346, Cfg9346_Lock);
2253
2254 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2255 /* (KON)FIXME: These are untested. We may have to set the
2256 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2257 documentation. */
2258 if (wol->wolopts & WAKE_UCAST)
2259 cfg5 |= Cfg5_UWF;
2260 if (wol->wolopts & WAKE_MCAST)
2261 cfg5 |= Cfg5_MWF;
2262 if (wol->wolopts & WAKE_BCAST)
2263 cfg5 |= Cfg5_BWF;
2264 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2265 spin_unlock_irq(&np->lock);
2266
2267 return 0;
2268 }
2269
rtl8139_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)2270 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2271 {
2272 struct rtl8139_private *np = dev->priv;
2273 strcpy(info->driver, DRV_NAME);
2274 strcpy(info->version, DRV_VERSION);
2275 strcpy(info->bus_info, pci_name(np->pci_dev));
2276 info->regdump_len = np->regs_len;
2277 }
2278
rtl8139_get_settings(struct net_device * dev,struct ethtool_cmd * cmd)2279 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2280 {
2281 struct rtl8139_private *np = dev->priv;
2282 spin_lock_irq(&np->lock);
2283 mii_ethtool_gset(&np->mii, cmd);
2284 spin_unlock_irq(&np->lock);
2285 return 0;
2286 }
2287
rtl8139_set_settings(struct net_device * dev,struct ethtool_cmd * cmd)2288 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2289 {
2290 struct rtl8139_private *np = dev->priv;
2291 int rc;
2292 spin_lock_irq(&np->lock);
2293 rc = mii_ethtool_sset(&np->mii, cmd);
2294 spin_unlock_irq(&np->lock);
2295 return rc;
2296 }
2297
rtl8139_nway_reset(struct net_device * dev)2298 static int rtl8139_nway_reset(struct net_device *dev)
2299 {
2300 struct rtl8139_private *np = dev->priv;
2301 return mii_nway_restart(&np->mii);
2302 }
2303
rtl8139_get_link(struct net_device * dev)2304 static u32 rtl8139_get_link(struct net_device *dev)
2305 {
2306 struct rtl8139_private *np = dev->priv;
2307 return mii_link_ok(&np->mii);
2308 }
2309
rtl8139_get_msglevel(struct net_device * dev)2310 static u32 rtl8139_get_msglevel(struct net_device *dev)
2311 {
2312 struct rtl8139_private *np = dev->priv;
2313 return np->msg_enable;
2314 }
2315
rtl8139_set_msglevel(struct net_device * dev,u32 datum)2316 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2317 {
2318 struct rtl8139_private *np = dev->priv;
2319 np->msg_enable = datum;
2320 }
2321
2322 /* TODO: we are too slack to do reg dumping for pio, for now */
2323 #ifdef CONFIG_8139TOO_PIO
2324 #define rtl8139_get_regs_len NULL
2325 #define rtl8139_get_regs NULL
2326 #else
rtl8139_get_regs_len(struct net_device * dev)2327 static int rtl8139_get_regs_len(struct net_device *dev)
2328 {
2329 struct rtl8139_private *np = dev->priv;
2330 return np->regs_len;
2331 }
2332
rtl8139_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * regbuf)2333 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2334 {
2335 struct rtl8139_private *np = dev->priv;
2336
2337 regs->version = RTL_REGS_VER;
2338
2339 spin_lock_irq(&np->lock);
2340 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2341 spin_unlock_irq(&np->lock);
2342 }
2343 #endif /* CONFIG_8139TOO_MMIO */
2344
rtl8139_get_stats_count(struct net_device * dev)2345 static int rtl8139_get_stats_count(struct net_device *dev)
2346 {
2347 return RTL_NUM_STATS;
2348 }
2349
rtl8139_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2350 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2351 {
2352 struct rtl8139_private *np = dev->priv;
2353
2354 data[0] = np->xstats.early_rx;
2355 data[1] = np->xstats.tx_buf_mapped;
2356 data[2] = np->xstats.tx_timeouts;
2357 data[3] = np->xstats.rx_lost_in_ring;
2358 }
2359
rtl8139_get_strings(struct net_device * dev,u32 stringset,u8 * data)2360 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2361 {
2362 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2363 }
2364
2365 static struct ethtool_ops rtl8139_ethtool_ops = {
2366 .get_drvinfo = rtl8139_get_drvinfo,
2367 .get_settings = rtl8139_get_settings,
2368 .set_settings = rtl8139_set_settings,
2369 .get_regs_len = rtl8139_get_regs_len,
2370 .get_regs = rtl8139_get_regs,
2371 .nway_reset = rtl8139_nway_reset,
2372 .get_link = rtl8139_get_link,
2373 .get_msglevel = rtl8139_get_msglevel,
2374 .set_msglevel = rtl8139_set_msglevel,
2375 .get_wol = rtl8139_get_wol,
2376 .set_wol = rtl8139_set_wol,
2377 .get_strings = rtl8139_get_strings,
2378 .get_stats_count = rtl8139_get_stats_count,
2379 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2380 };
2381
netdev_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)2382 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2383 {
2384 struct rtl8139_private *np = dev->priv;
2385 struct mii_ioctl_data *data = (struct mii_ioctl_data *) & rq->ifr_data;
2386 int rc;
2387
2388 if (!netif_running(dev))
2389 return -EINVAL;
2390
2391 spin_lock_irq(&np->lock);
2392 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
2393 spin_unlock_irq(&np->lock);
2394
2395 return rc;
2396 }
2397
2398
rtl8139_get_stats(struct net_device * dev)2399 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2400 {
2401 struct rtl8139_private *tp = dev->priv;
2402 void *ioaddr = tp->mmio_addr;
2403 unsigned long flags;
2404
2405 if (netif_running(dev)) {
2406 spin_lock_irqsave (&tp->lock, flags);
2407 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2408 RTL_W32 (RxMissed, 0);
2409 spin_unlock_irqrestore (&tp->lock, flags);
2410 }
2411
2412 return &tp->stats;
2413 }
2414
2415 /* Set or clear the multicast filter for this adaptor.
2416 This routine is not state sensitive and need not be SMP locked. */
2417
__set_rx_mode(struct net_device * dev)2418 static void __set_rx_mode (struct net_device *dev)
2419 {
2420 struct rtl8139_private *tp = dev->priv;
2421 void *ioaddr = tp->mmio_addr;
2422 u32 mc_filter[2]; /* Multicast hash filter */
2423 int i, rx_mode;
2424 u32 tmp;
2425
2426 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2427 dev->name, dev->flags, RTL_R32 (RxConfig));
2428
2429 /* Note: do not reorder, GCC is clever about common statements. */
2430 if (dev->flags & IFF_PROMISC) {
2431 /* Unconditionally log net taps. */
2432 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2433 dev->name);
2434 rx_mode =
2435 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2436 AcceptAllPhys;
2437 mc_filter[1] = mc_filter[0] = 0xffffffff;
2438 } else if ((dev->mc_count > multicast_filter_limit)
2439 || (dev->flags & IFF_ALLMULTI)) {
2440 /* Too many to filter perfectly -- accept all multicasts. */
2441 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2442 mc_filter[1] = mc_filter[0] = 0xffffffff;
2443 } else {
2444 struct dev_mc_list *mclist;
2445 rx_mode = AcceptBroadcast | AcceptMyPhys;
2446 mc_filter[1] = mc_filter[0] = 0;
2447 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2448 i++, mclist = mclist->next) {
2449 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2450
2451 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2452 rx_mode |= AcceptMulticast;
2453 }
2454 }
2455
2456 /* We can safely update without stopping the chip. */
2457 tmp = rtl8139_rx_config | rx_mode;
2458 if (tp->rx_config != tmp) {
2459 RTL_W32_F (RxConfig, tmp);
2460 tp->rx_config = tmp;
2461 }
2462 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2463 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2464 }
2465
rtl8139_set_rx_mode(struct net_device * dev)2466 static void rtl8139_set_rx_mode (struct net_device *dev)
2467 {
2468 unsigned long flags;
2469 struct rtl8139_private *tp = dev->priv;
2470
2471 spin_lock_irqsave (&tp->lock, flags);
2472 __set_rx_mode(dev);
2473 spin_unlock_irqrestore (&tp->lock, flags);
2474 }
2475
2476 #ifdef CONFIG_PM
2477
rtl8139_suspend(struct pci_dev * pdev,u32 state)2478 static int rtl8139_suspend (struct pci_dev *pdev, u32 state)
2479 {
2480 struct net_device *dev = pci_get_drvdata (pdev);
2481 struct rtl8139_private *tp = dev->priv;
2482 void *ioaddr = tp->mmio_addr;
2483 unsigned long flags;
2484
2485 pci_save_state (pdev, tp->pci_state);
2486
2487 if (!netif_running (dev))
2488 return 0;
2489
2490 netif_device_detach (dev);
2491
2492 spin_lock_irqsave (&tp->lock, flags);
2493
2494 /* Disable interrupts, stop Tx and Rx. */
2495 RTL_W16 (IntrMask, 0);
2496 RTL_W8 (ChipCmd, 0);
2497
2498 /* Update the error counts. */
2499 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2500 RTL_W32 (RxMissed, 0);
2501
2502 pci_set_power_state (pdev, 3);
2503
2504 spin_unlock_irqrestore (&tp->lock, flags);
2505 return 0;
2506 }
2507
2508
rtl8139_resume(struct pci_dev * pdev)2509 static int rtl8139_resume (struct pci_dev *pdev)
2510 {
2511 struct net_device *dev = pci_get_drvdata (pdev);
2512 struct rtl8139_private *tp = dev->priv;
2513
2514 pci_restore_state (pdev, tp->pci_state);
2515 if (!netif_running (dev))
2516 return 0;
2517 pci_set_power_state (pdev, 0);
2518 rtl8139_init_ring (dev);
2519 rtl8139_hw_start (dev);
2520 netif_device_attach (dev);
2521 return 0;
2522 }
2523
2524 #endif /* CONFIG_PM */
2525
2526
2527 static struct pci_driver rtl8139_pci_driver = {
2528 .name = DRV_NAME,
2529 .id_table = rtl8139_pci_tbl,
2530 .probe = rtl8139_init_one,
2531 .remove = __devexit_p(rtl8139_remove_one),
2532 #ifdef CONFIG_PM
2533 .suspend = rtl8139_suspend,
2534 .resume = rtl8139_resume,
2535 #endif /* CONFIG_PM */
2536 };
2537
2538
rtl8139_init_module(void)2539 static int __init rtl8139_init_module (void)
2540 {
2541 /* when we're a module, we always print a version message,
2542 * even if no 8139 board is found.
2543 */
2544 #ifdef MODULE
2545 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2546 #endif
2547
2548 return pci_module_init (&rtl8139_pci_driver);
2549 }
2550
2551
rtl8139_cleanup_module(void)2552 static void __exit rtl8139_cleanup_module (void)
2553 {
2554 pci_unregister_driver (&rtl8139_pci_driver);
2555 }
2556
2557
2558 module_init(rtl8139_init_module);
2559 module_exit(rtl8139_cleanup_module);
2560