1 2 #ifndef _IEEE1394_CSR_H 3 #define _IEEE1394_CSR_H 4 5 #ifdef CONFIG_PREEMPT 6 #include <linux/sched.h> 7 #endif 8 9 #define CSR_REGISTER_BASE 0xfffff0000000ULL 10 11 /* register offsets relative to CSR_REGISTER_BASE */ 12 #define CSR_STATE_CLEAR 0x0 13 #define CSR_STATE_SET 0x4 14 #define CSR_NODE_IDS 0x8 15 #define CSR_RESET_START 0xc 16 #define CSR_SPLIT_TIMEOUT_HI 0x18 17 #define CSR_SPLIT_TIMEOUT_LO 0x1c 18 #define CSR_CYCLE_TIME 0x200 19 #define CSR_BUS_TIME 0x204 20 #define CSR_BUSY_TIMEOUT 0x210 21 #define CSR_BUS_MANAGER_ID 0x21c 22 #define CSR_BANDWIDTH_AVAILABLE 0x220 23 #define CSR_CHANNELS_AVAILABLE 0x224 24 #define CSR_CHANNELS_AVAILABLE_HI 0x224 25 #define CSR_CHANNELS_AVAILABLE_LO 0x228 26 #define CSR_BROADCAST_CHANNEL 0x234 27 #define CSR_CONFIG_ROM 0x400 28 #define CSR_CONFIG_ROM_END 0x800 29 #define CSR_FCP_COMMAND 0xB00 30 #define CSR_FCP_RESPONSE 0xD00 31 #define CSR_FCP_END 0xF00 32 #define CSR_TOPOLOGY_MAP 0x1000 33 #define CSR_TOPOLOGY_MAP_END 0x1400 34 #define CSR_SPEED_MAP 0x2000 35 #define CSR_SPEED_MAP_END 0x3000 36 37 38 struct csr_control { 39 spinlock_t lock; 40 41 quadlet_t state; 42 quadlet_t node_ids; 43 quadlet_t split_timeout_hi, split_timeout_lo; 44 unsigned long expire; // Calculated from split_timeout 45 quadlet_t cycle_time; 46 quadlet_t bus_time; 47 quadlet_t bus_manager_id; 48 quadlet_t bandwidth_available; 49 quadlet_t channels_available_hi, channels_available_lo; 50 quadlet_t broadcast_channel; 51 52 quadlet_t *rom; 53 size_t rom_size; 54 unsigned char rom_version; 55 56 57 quadlet_t topology_map[256]; 58 quadlet_t speed_map[1024]; 59 }; 60 61 62 void init_csr(void); 63 void cleanup_csr(void); 64 65 #endif /* _IEEE1394_CSR_H */ 66