1 /*
2 * Version 2.13
3 *
4 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
5 * IDE driver for Linux.
6 *
7 * Copyright (c) 2000-2002 Vojtech Pavlik
8 *
9 * Based on the work of:
10 * Andre Hedrick
11 */
12
13 /*
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published by
16 * the Free Software Foundation.
17 */
18
19 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/ioport.h>
23 #include <linux/blkdev.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/ide.h>
27 #include <asm/io.h>
28
29 #include "ide-timing.h"
30 #include "amd74xx.h"
31
32 #define AMD_IDE_ENABLE (0x00 + amd_config->base)
33 #define AMD_IDE_CONFIG (0x01 + amd_config->base)
34 #define AMD_CABLE_DETECT (0x02 + amd_config->base)
35 #define AMD_DRIVE_TIMING (0x08 + amd_config->base)
36 #define AMD_8BIT_TIMING (0x0e + amd_config->base)
37 #define AMD_ADDRESS_SETUP (0x0c + amd_config->base)
38 #define AMD_UDMA_TIMING (0x10 + amd_config->base)
39
40 #define AMD_UDMA 0x07
41 #define AMD_UDMA_33 0x01
42 #define AMD_UDMA_66 0x02
43 #define AMD_UDMA_100 0x03
44 #define AMD_UDMA_133 0x04
45 #define AMD_CHECK_SWDMA 0x08
46 #define AMD_BAD_SWDMA 0x10
47 #define AMD_BAD_FIFO 0x20
48 #define AMD_CHECK_SERENADE 0x40
49
50 /*
51 * AMD SouthBridge chips.
52 */
53
54 static struct amd_ide_chip {
55 unsigned short id;
56 unsigned long base;
57 unsigned char flags;
58 } amd_ide_chips[] = {
59 { PCI_DEVICE_ID_AMD_COBRA_7401, 0x40, AMD_UDMA_33 | AMD_BAD_SWDMA },
60 { PCI_DEVICE_ID_AMD_VIPER_7409, 0x40, AMD_UDMA_66 | AMD_CHECK_SWDMA },
61 { PCI_DEVICE_ID_AMD_VIPER_7411, 0x40, AMD_UDMA_100 | AMD_BAD_FIFO },
62 { PCI_DEVICE_ID_AMD_OPUS_7441, 0x40, AMD_UDMA_100 },
63 { PCI_DEVICE_ID_AMD_8111_IDE, 0x40, AMD_UDMA_133 | AMD_CHECK_SERENADE },
64 { PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x50, AMD_UDMA_100 },
65 { PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x50, AMD_UDMA_133 },
66 { PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, 0x50, AMD_UDMA_133 },
67 { PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, 0x50, AMD_UDMA_133 },
68 { PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, 0x50, AMD_UDMA_133 },
69 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, 0x50, AMD_UDMA_133 },
70 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, 0x50, AMD_UDMA_133 },
71 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, 0x50, AMD_UDMA_133 },
72 { PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE,0x50, AMD_UDMA_133 },
73 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE,0x50, AMD_UDMA_133 },
74 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE,0x50, AMD_UDMA_133 },
75 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE,0x50, AMD_UDMA_133 },
76 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE,0x50, AMD_UDMA_133 },
77 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE,0x50, AMD_UDMA_133 },
78 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE,0x50, AMD_UDMA_133 },
79 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE,0x50, AMD_UDMA_133 },
80 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE,0x50, AMD_UDMA_133 },
81 { PCI_DEVICE_ID_AMD_CS5536_IDE, 0x40, AMD_UDMA_100 },
82 { 0 }
83 };
84
85 static struct amd_ide_chip *amd_config;
86 static ide_pci_device_t *amd_chipset;
87 static unsigned int amd_80w;
88 static unsigned int amd_clock;
89
90 static char *amd_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
91 static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
92
93 /*
94 * AMD /proc entry.
95 */
96
97 #ifdef CONFIG_PROC_FS
98
99 #include <linux/stat.h>
100 #include <linux/proc_fs.h>
101
102 static unsigned char amd_udma2cyc[] = { 4, 6, 8, 10, 3, 2, 1, 15 };
103 static unsigned long amd_base;
104 static struct pci_dev *bmide_dev;
105 extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
106
107 #define amd_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
108 #define amd_print_drive(name, format, arg...)\
109 p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
110
amd74xx_get_info(char * buffer,char ** addr,off_t offset,int count)111 static int amd74xx_get_info(char *buffer, char **addr, off_t offset, int count)
112 {
113 int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
114 uen[4], udma[4], active8b[4], recover8b[4];
115 struct pci_dev *dev = bmide_dev;
116 unsigned int v, u, i;
117 unsigned short c, w;
118 unsigned char t;
119 char *p = buffer;
120 int len;
121
122 amd_print("----------AMD BusMastering IDE Configuration----------------");
123
124 amd_print("Driver Version: 2.13");
125 amd_print("South Bridge: %s", bmide_dev->name);
126
127 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
128 amd_print("Revision: IDE %#x", t);
129 amd_print("Highest DMA rate: %s", amd_dma[amd_config->flags & AMD_UDMA]);
130
131 amd_print("BM-DMA base: %#lx", amd_base);
132 amd_print("PCI clock: %d.%dMHz", amd_clock / 1000, amd_clock / 100 % 10);
133
134 amd_print("-----------------------Primary IDE-------Secondary IDE------");
135
136 pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
137 amd_print("Prefetch Buffer: %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
138 amd_print("Post Write Buffer: %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
139
140 pci_read_config_byte(dev, AMD_IDE_ENABLE, &t);
141 amd_print("Enabled: %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
142
143 c = inb(amd_base + 0x02) | (inb(amd_base + 0x0a) << 8);
144 amd_print("Simplex only: %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
145
146 amd_print("Cable Type: %10s%20s", (amd_80w & 1) ? "80w" : "40w", (amd_80w & 2) ? "80w" : "40w");
147
148 if (!amd_clock)
149 return p - buffer;
150
151 amd_print("-------------------drive0----drive1----drive2----drive3-----");
152
153 pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
154 pci_read_config_dword(dev, AMD_DRIVE_TIMING, &v);
155 pci_read_config_word(dev, AMD_8BIT_TIMING, &w);
156 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
157
158 for (i = 0; i < 4; i++) {
159 setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
160 recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
161 active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
162 active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
163 recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;
164
165 udma[i] = amd_udma2cyc[((u >> ((3 - i) << 3)) & 0x7)];
166 uen[i] = ((u >> ((3 - i) << 3)) & 0x40) ? 1 : 0;
167 den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
168
169 if (den[i] && uen[i] && udma[i] == 1) {
170 speed[i] = amd_clock * 3;
171 cycle[i] = 666666 / amd_clock;
172 continue;
173 }
174
175 if (den[i] && uen[i] && udma[i] == 15) {
176 speed[i] = amd_clock * 4;
177 cycle[i] = 500000 / amd_clock;
178 continue;
179 }
180
181 speed[i] = 4 * amd_clock / ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2);
182 cycle[i] = 1000000 * ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2) / amd_clock / 2;
183 }
184
185 amd_print_drive("Transfer Mode: ", "%10s", den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
186
187 amd_print_drive("Address Setup: ", "%8dns", 1000000 * setup[i] / amd_clock);
188 amd_print_drive("Cmd Active: ", "%8dns", 1000000 * active8b[i] / amd_clock);
189 amd_print_drive("Cmd Recovery: ", "%8dns", 1000000 * recover8b[i] / amd_clock);
190 amd_print_drive("Data Active: ", "%8dns", 1000000 * active[i] / amd_clock);
191 amd_print_drive("Data Recovery: ", "%8dns", 1000000 * recover[i] / amd_clock);
192 amd_print_drive("Cycle Time: ", "%8dns", cycle[i]);
193 amd_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10);
194
195 /* hoping p - buffer is less than 4K... */
196 len = (p - buffer) - offset;
197 *addr = buffer + offset;
198
199 return len > count ? count : len;
200 }
201
202 #endif
203
204 /*
205 * amd_set_speed() writes timing values to the chipset registers
206 */
207
amd_set_speed(struct pci_dev * dev,unsigned char dn,struct ide_timing * timing)208 static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing)
209 {
210 unsigned char t;
211
212 pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
213 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
214 pci_write_config_byte(dev, AMD_ADDRESS_SETUP, t);
215
216 pci_write_config_byte(dev, AMD_8BIT_TIMING + (1 - (dn >> 1)),
217 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
218
219 pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn),
220 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
221
222 switch (amd_config->flags & AMD_UDMA) {
223 case AMD_UDMA_33: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
224 case AMD_UDMA_66: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
225 case AMD_UDMA_100: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
226 case AMD_UDMA_133: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
227 default: return;
228 }
229
230 pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t);
231 }
232
233 /*
234 * amd_set_drive() computes timing values configures the drive and
235 * the chipset to a desired transfer mode. It also can be called
236 * by upper layers.
237 */
238
amd_set_drive(ide_drive_t * drive,u8 speed)239 static int amd_set_drive(ide_drive_t *drive, u8 speed)
240 {
241 ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
242 struct ide_timing t, p;
243 int T, UT;
244
245 if (speed != XFER_PIO_SLOW && speed != drive->current_speed)
246 if (ide_config_drive_speed(drive, speed))
247 printk(KERN_WARNING "ide%d: Drive %d didn't accept speed setting. Oh, well.\n",
248 drive->dn >> 1, drive->dn & 1);
249
250 T = 1000000000 / amd_clock;
251 UT = T / min_t(int, max_t(int, amd_config->flags & AMD_UDMA, 1), 2);
252
253 ide_timing_compute(drive, speed, &t, T, UT);
254
255 if (peer->present) {
256 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
257 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
258 }
259
260 if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
261 if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
262
263 amd_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
264
265 if (!drive->init_speed)
266 drive->init_speed = speed;
267 drive->current_speed = speed;
268
269 return 0;
270 }
271
272 /*
273 * amd74xx_tune_drive() is a callback from upper layers for
274 * PIO-only tuning.
275 */
276
amd74xx_tune_drive(ide_drive_t * drive,u8 pio)277 static void amd74xx_tune_drive(ide_drive_t *drive, u8 pio)
278 {
279 if (pio == 255) {
280 amd_set_drive(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
281 return;
282 }
283
284 amd_set_drive(drive, XFER_PIO_0 + min_t(byte, pio, 5));
285 }
286
287 /*
288 * amd74xx_dmaproc() is a callback from upper layers that can do
289 * a lot, but we use it for DMA/PIO tuning only, delegating everything
290 * else to the default ide_dmaproc().
291 */
292
amd74xx_ide_dma_check(ide_drive_t * drive)293 static int amd74xx_ide_dma_check(ide_drive_t *drive)
294 {
295 int w80 = HWIF(drive)->udma_four;
296
297 u8 speed = ide_find_best_mode(drive,
298 XFER_PIO | XFER_EPIO | XFER_MWDMA | XFER_UDMA |
299 ((amd_config->flags & AMD_BAD_SWDMA) ? 0 : XFER_SWDMA) |
300 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_66 ? XFER_UDMA_66 : 0) |
301 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_100 ? XFER_UDMA_100 : 0) |
302 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_133 ? XFER_UDMA_133 : 0));
303
304 amd_set_drive(drive, speed);
305
306 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
307 return HWIF(drive)->ide_dma_on(drive);
308 return HWIF(drive)->ide_dma_off_quietly(drive);
309 }
310
311 /*
312 * The initialization callback. Here we determine the IDE chip type
313 * and initialize its drive independent registers.
314 */
315
init_chipset_amd74xx(struct pci_dev * dev,const char * name)316 static unsigned int __init init_chipset_amd74xx(struct pci_dev *dev, const char *name)
317 {
318 unsigned char t;
319 unsigned int u;
320 int i;
321
322 /*
323 * Check for bad SWDMA.
324 */
325
326 if (amd_config->flags & AMD_CHECK_SWDMA) {
327 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
328 if (t <= 7)
329 amd_config->flags |= AMD_BAD_SWDMA;
330 }
331
332 /*
333 * Check 80-wire cable presence.
334 */
335
336 switch (amd_config->flags & AMD_UDMA) {
337
338 case AMD_UDMA_133:
339 case AMD_UDMA_100:
340 pci_read_config_byte(dev, AMD_CABLE_DETECT, &t);
341 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
342 amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
343 for (i = 24; i >= 0; i -= 8)
344 if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
345 printk(KERN_WARNING "%s: BIOS didn't set cable bits correctly. Enabling workaround.\n",
346 amd_chipset->name);
347 amd_80w |= (1 << (1 - (i >> 4)));
348 }
349 break;
350
351 case AMD_UDMA_66:
352 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
353 for (i = 24; i >= 0; i -= 8)
354 if ((u >> i) & 4)
355 amd_80w |= (1 << (1 - (i >> 4)));
356 break;
357 }
358
359 /*
360 * Take care of prefetch & postwrite.
361 */
362
363 pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
364 pci_write_config_byte(dev, AMD_IDE_CONFIG,
365 (amd_config->flags & AMD_BAD_FIFO) ? (t & 0x0f) : (t | 0xf0));
366
367 /*
368 * Take care of incorrectly wired Serenade mainboards.
369 */
370
371 if ((amd_config->flags & AMD_CHECK_SERENADE) &&
372 dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
373 dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
374 amd_config->flags = AMD_UDMA_100;
375
376 /*
377 * Determine the system bus clock.
378 */
379
380 amd_clock = system_bus_clock() * 1000;
381
382 switch (amd_clock) {
383 case 33000: amd_clock = 33333; break;
384 case 37000: amd_clock = 37500; break;
385 case 41000: amd_clock = 41666; break;
386 }
387
388 if (amd_clock < 20000 || amd_clock > 50000) {
389 printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
390 amd_chipset->name, amd_clock);
391 printk(KERN_WARNING "%s: Use ide0=ata66 if you want to assume 80-wire cable\n",
392 amd_chipset->name);
393 amd_clock = 33333;
394 }
395
396 /*
397 * Print the boot message.
398 */
399
400 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
401 printk(KERN_INFO "%s: %s (rev %02x) %s controller\n",
402 amd_chipset->name, pci_name(dev), t, amd_dma[amd_config->flags & AMD_UDMA]);
403
404 /*
405 * Register /proc/ide/amd74xx entry
406 */
407
408 #if defined(DISPLAY_AMD_TIMINGS) && defined(CONFIG_PROC_FS)
409 if (!amd74xx_proc) {
410 amd_base = pci_resource_start(dev, 4);
411 bmide_dev = dev;
412 ide_pci_register_host_proc(&amd74xx_procs[0]);
413 amd74xx_proc = 1;
414 }
415 #endif /* DISPLAY_AMD_TIMINGS && CONFIG_PROC_FS */
416
417 return dev->irq;
418 }
419
init_hwif_amd74xx(ide_hwif_t * hwif)420 static void __init init_hwif_amd74xx(ide_hwif_t *hwif)
421 {
422 int i;
423
424 hwif->autodma = 0;
425
426 hwif->tuneproc = &amd74xx_tune_drive;
427 hwif->speedproc = &amd_set_drive;
428
429 for (i = 0; i < 2; i++) {
430 hwif->drives[i].io_32bit = 1;
431 hwif->drives[i].unmask = 1;
432 hwif->drives[i].autotune = 1;
433 hwif->drives[i].dn = hwif->channel * 2 + i;
434 }
435
436 if (!hwif->dma_base)
437 return;
438
439 hwif->atapi_dma = 1;
440 hwif->ultra_mask = 0x7f;
441 hwif->mwdma_mask = 0x07;
442 hwif->swdma_mask = 0x07;
443
444 if (!hwif->udma_four)
445 hwif->udma_four = (amd_80w >> hwif->channel) & 1;
446 hwif->ide_dma_check = &amd74xx_ide_dma_check;
447 if (!noautodma)
448 hwif->autodma = 1;
449 hwif->drives[0].autodma = hwif->autodma;
450 hwif->drives[1].autodma = hwif->autodma;
451 }
452
amd74xx_probe(struct pci_dev * dev,const struct pci_device_id * id)453 static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
454 {
455 amd_chipset = amd74xx_chipsets + id->driver_data;
456 amd_config = amd_ide_chips + id->driver_data;
457 if (dev->device != amd_chipset->device) BUG();
458 if (dev->device != amd_config->id) BUG();
459 ide_setup_pci_device(dev, amd_chipset);
460 MOD_INC_USE_COUNT;
461 return 0;
462 }
463
464 static struct pci_device_id amd74xx_pci_tbl[] __devinitdata = {
465 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
466 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
467 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
468 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
469 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
470 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
471 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
472 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 },
473 #ifdef CONFIG_BLK_DEV_IDE_SATA
474 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
475 #endif
476 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 },
477 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10 },
478 #ifdef CONFIG_BLK_DEV_IDE_SATA
479 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11 },
480 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12 },
481 #endif
482 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13 },
483 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14 },
484 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15 },
485 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16 },
486 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17 },
487 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18 },
488 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19 },
489 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20 },
490 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21 },
491 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22 },
492 { 0, },
493 };
494
495 static struct pci_driver driver = {
496 .name = "AMD IDE",
497 .id_table = amd74xx_pci_tbl,
498 .probe = amd74xx_probe,
499 };
500
amd74xx_ide_init(void)501 static int amd74xx_ide_init(void)
502 {
503 return ide_pci_register_driver(&driver);
504 }
505
amd74xx_ide_exit(void)506 static void amd74xx_ide_exit(void)
507 {
508 ide_pci_unregister_driver(&driver);
509 }
510
511 module_init(amd74xx_ide_init);
512 module_exit(amd74xx_ide_exit);
513
514 MODULE_AUTHOR("Vojtech Pavlik");
515 MODULE_DESCRIPTION("AMD PCI IDE driver");
516 MODULE_LICENSE("GPL");
517
518 EXPORT_NO_SYMBOLS;
519