1 /*
2 ** DINO manager
3 **
4 ** (c) Copyright 1999 Red Hat Software
5 ** (c) Copyright 1999 SuSE GmbH
6 ** (c) Copyright 1999,2000 Hewlett-Packard Company
7 ** (c) Copyright 2000 Grant Grundler
8 **
9 ** This program is free software; you can redistribute it and/or modify
10 ** it under the terms of the GNU General Public License as published by
11 ** the Free Software Foundation; either version 2 of the License, or
12 ** (at your option) any later version.
13 **
14 ** This module provides access to Dino PCI bus (config/IOport spaces)
15 ** and helps manage Dino IRQ lines.
16 **
17 ** Dino interrupt handling is a bit complicated.
18 ** Dino always writes to the broadcast EIR via irr0 for now.
19 ** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
20 ** Only one processor interrupt is used for the 11 IRQ line
21 ** inputs to dino.
22 **
23 ** The different between Built-in Dino and Card-Mode
24 ** dino is in chip initialization and pci device initialization.
25 **
26 ** Linux drivers can only use Card-Mode Dino if pci devices I/O port
27 ** BARs are configured and used by the driver. Programming MMIO address
28 ** requires substantial knowledge of available Host I/O address ranges
29 ** is currently not supported. Port/Config accessor functions are the
30 ** same. "BIOS" differences are handled within the existing routines.
31 */
32
33 /* Changes :
34 ** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
35 ** - added support for the integrated RS232.
36 */
37
38 /*
39 ** TODO: create a virtual address for each Dino HPA.
40 ** GSC code might be able to do this since IODC data tells us
41 ** how many pages are used. PCI subsystem could (must?) do this
42 ** for PCI drivers devices which implement/use MMIO registers.
43 */
44
45 #include <linux/config.h>
46 #include <linux/delay.h>
47 #include <linux/types.h>
48 #include <linux/kernel.h>
49 #include <linux/pci.h>
50 #include <linux/init.h>
51 #include <linux/ioport.h>
52 #include <linux/slab.h>
53 #include <linux/interrupt.h> /* for struct irqaction */
54 #include <linux/spinlock.h> /* for spinlock_t and prototypes */
55
56 #include <asm/pdc.h>
57 #include <asm/page.h>
58 #include <asm/system.h>
59 #include <asm/io.h>
60 #include <asm/hardware.h>
61
62 #include <asm/irq.h> /* for "gsc" irq functions */
63 #include <asm/gsc.h>
64
65 #undef DINO_DEBUG
66
67 #ifdef DINO_DEBUG
68 #define DBG(x...) printk(x)
69 #else
70 #define DBG(x...)
71 #endif
72
73 /*
74 ** Config accessor functions only pass in the 8-bit bus number
75 ** and not the 8-bit "PCI Segment" number. Each Dino will be
76 ** assigned a PCI bus number based on "when" it's discovered.
77 **
78 ** The "secondary" bus number is set to this before calling
79 ** pci_scan_bus(). If any PPB's are present, the scan will
80 ** discover them and update the "secondary" and "subordinate"
81 ** fields in Dino's pci_bus structure.
82 **
83 ** Changes in the configuration *will* result in a different
84 ** bus number for each dino.
85 */
86
87 #define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA)
88
89 #define DINO_IAR0 0x004
90 #define DINO_IODC_ADDR 0x008
91 #define DINO_IODC_DATA_0 0x008
92 #define DINO_IODC_DATA_1 0x008
93 #define DINO_IRR0 0x00C
94 #define DINO_IAR1 0x010
95 #define DINO_IRR1 0x014
96 #define DINO_IMR 0x018
97 #define DINO_IPR 0x01C
98 #define DINO_TOC_ADDR 0x020
99 #define DINO_ICR 0x024
100 #define DINO_ILR 0x028
101 #define DINO_IO_COMMAND 0x030
102 #define DINO_IO_STATUS 0x034
103 #define DINO_IO_CONTROL 0x038
104 #define DINO_IO_GSC_ERR_RESP 0x040
105 #define DINO_IO_ERR_INFO 0x044
106 #define DINO_IO_PCI_ERR_RESP 0x048
107 #define DINO_IO_FBB_EN 0x05c
108 #define DINO_IO_ADDR_EN 0x060
109 #define DINO_PCI_ADDR 0x064
110 #define DINO_CONFIG_DATA 0x068
111 #define DINO_IO_DATA 0x06c
112 #define DINO_MEM_DATA 0x070 /* Dino 3.x only */
113 #define DINO_GSC2X_CONFIG 0x7b4
114 #define DINO_GMASK 0x800
115 #define DINO_PAMR 0x804
116 #define DINO_PAPR 0x808
117 #define DINO_DAMODE 0x80c
118 #define DINO_PCICMD 0x810
119 #define DINO_PCISTS 0x814
120 #define DINO_MLTIM 0x81c
121 #define DINO_BRDG_FEAT 0x820
122 #define DINO_PCIROR 0x824
123 #define DINO_PCIWOR 0x828
124 #define DINO_TLTIM 0x830
125
126 #define DINO_IRQS 11 /* bits 0-10 are architected */
127 #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */
128
129 #define DINO_MASK_IRQ(x) (1<<(x))
130
131 #define PCIINTA 0x001
132 #define PCIINTB 0x002
133 #define PCIINTC 0x004
134 #define PCIINTD 0x008
135 #define PCIINTE 0x010
136 #define PCIINTF 0x020
137 #define GSCEXTINT 0x040
138 /* #define xxx 0x080 - bit 7 is "default" */
139 /* #define xxx 0x100 - bit 8 not used */
140 /* #define xxx 0x200 - bit 9 not used */
141 #define RS232INT 0x400
142
143 struct dino_device
144 {
145 struct pci_hba_data hba; /* 'C' inheritance - must be first */
146 spinlock_t dinosaur_pen;
147 unsigned long txn_addr; /* EIR addr to generate interrupt */
148 u32 txn_data; /* EIR data assign to each dino */
149 int irq; /* Virtual IRQ dino uses */
150 struct irq_region *dino_region; /* region for this Dino */
151
152 u32 imr; /* IRQ's which are enabled */
153 #ifdef DINO_DEBUG
154 unsigned int dino_irr0; /* save most recent IRQ line stat */
155 #endif
156 };
157
158 /* Looks nice and keeps the compiler happy */
159 #define DINO_DEV(d) ((struct dino_device *) d)
160
161
162
163 /***********************************************
164 **
165 ** Dino Configuration Space Accessor Functions
166 **
167 ************************************************/
168
169 #define le8_to_cpu(x) (x)
170 #define cpu_to_le8(x) (x)
171
172 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
173
174 #define DINO_CFG_RD(type, size, mask) \
175 static int dino_cfg_read##size (struct pci_dev *dev, int pos, u##size *data) \
176 { \
177 struct dino_device *d = DINO_DEV(dev->sysdata); \
178 u32 local_bus = (dev->bus->parent == NULL) ? 0 : dev->bus->secondary; \
179 u32 v = DINO_CFG_TOK(local_bus, dev->devfn, (pos&~3)); \
180 unsigned long flags; \
181 spin_lock_irqsave(&d->dinosaur_pen, flags); \
182 /* tell HW which CFG address */ \
183 gsc_writel(v, d->hba.base_addr + DINO_PCI_ADDR); \
184 /* generate cfg read cycle */ \
185 *data = le##size##_to_cpu(gsc_read##type(d->hba.base_addr+DINO_CONFIG_DATA+(pos&mask))); \
186 spin_unlock_irqrestore(&d->dinosaur_pen, flags); \
187 return 0; \
188 }
189
190 DINO_CFG_RD(b, 8, 3)
191 DINO_CFG_RD(w, 16, 2)
192 DINO_CFG_RD(l, 32, 0)
193
194
195 /*
196 ** Dino address stepping "feature":
197 ** When address stepping, Dino attempts to drive the bus one cycle too soon
198 ** even though the type of cycle (config vs. MMIO) might be different.
199 ** The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
200 */
201 #define DINO_CFG_WR(type, size, mask) \
202 static int dino_cfg_write##size (struct pci_dev *dev, int pos, u##size data) \
203 { \
204 struct dino_device *d = DINO_DEV(dev->sysdata); \
205 u32 local_bus = (dev->bus->parent == NULL) ? 0 : dev->bus->secondary; \
206 u32 v = DINO_CFG_TOK(local_bus, dev->devfn, (pos&~3)); \
207 unsigned long flags; \
208 spin_lock_irqsave(&d->dinosaur_pen, flags); \
209 /* avoid address stepping feature */ \
210 gsc_writel(v & 0xffffff00, d->hba.base_addr + DINO_PCI_ADDR); \
211 (volatile int) gsc_readl(d->hba.base_addr + DINO_CONFIG_DATA); \
212 /* tell HW which CFG address */ \
213 gsc_writel(v, d->hba.base_addr + DINO_PCI_ADDR); \
214 /* generate cfg read cycle */ \
215 gsc_write##type(cpu_to_le##size(data), d->hba.base_addr+DINO_CONFIG_DATA+(pos&mask)); \
216 spin_unlock_irqrestore(&d->dinosaur_pen, flags); \
217 return 0; \
218 }
219
220 DINO_CFG_WR(b, 8, 3)
221 DINO_CFG_WR(w, 16, 2)
222 DINO_CFG_WR(l, 32, 0)
223
224 static struct pci_ops dino_cfg_ops = {
225 read_byte: dino_cfg_read8,
226 read_word: dino_cfg_read16,
227 read_dword: dino_cfg_read32,
228 write_byte: dino_cfg_write8,
229 write_word: dino_cfg_write16,
230 write_dword: dino_cfg_write32
231 };
232
233
234
235 /*******************************************************
236 **
237 ** Dino "I/O Port" Space Accessor Functions
238 **
239 ** Many PCI devices don't require use of I/O port space (eg Tulip,
240 ** NCR720) since they export the same registers to both MMIO and
241 ** I/O port space. Performance is going to stink if drivers use
242 ** I/O port instead of MMIO.
243 **
244 ********************************************************/
245
246
247 #define DINO_PORT_IN(type, size, mask) \
248 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
249 { \
250 u##size v; \
251 unsigned long flags; \
252 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
253 /* tell HW which IO Port address */ \
254 gsc_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
255 /* generate I/O PORT read cycle */ \
256 v = gsc_read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
257 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
258 return le##size##_to_cpu(v); \
259 }
260
261 DINO_PORT_IN(b, 8, 3)
262 DINO_PORT_IN(w, 16, 2)
263 DINO_PORT_IN(l, 32, 0)
264
265 #define DINO_PORT_OUT(type, size, mask) \
266 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
267 { \
268 unsigned long flags; \
269 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
270 /* tell HW which IO port address */ \
271 gsc_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
272 /* generate cfg write cycle */ \
273 gsc_write##type(cpu_to_le##size(val), d->base_addr+DINO_IO_DATA+(addr&mask)); \
274 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
275 }
276
277 DINO_PORT_OUT(b, 8, 3)
278 DINO_PORT_OUT(w, 16, 2)
279 DINO_PORT_OUT(l, 32, 0)
280
281 struct pci_port_ops dino_port_ops = {
282 inb: dino_in8,
283 inw: dino_in16,
284 inl: dino_in32,
285 outb: dino_out8,
286 outw: dino_out16,
287 outl: dino_out32
288 };
289
290 static void
dino_mask_irq(void * irq_dev,int irq)291 dino_mask_irq(void *irq_dev, int irq)
292 {
293 struct dino_device *dino_dev = DINO_DEV(irq_dev);
294
295 DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, irq_dev, irq);
296
297 if (NULL == irq_dev || irq > DINO_IRQS || irq < 0) {
298 printk(KERN_WARNING "%s(0x%lx, %d) - not a dino irq?\n",
299 __FUNCTION__, (long) irq_dev, irq);
300 BUG();
301 } else {
302 /*
303 ** Clear the matching bit in the IMR register
304 */
305 dino_dev->imr &= ~(DINO_MASK_IRQ(irq));
306 gsc_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
307 }
308 }
309
310
311 static void
dino_unmask_irq(void * irq_dev,int irq)312 dino_unmask_irq(void *irq_dev, int irq)
313 {
314 struct dino_device *dino_dev = DINO_DEV(irq_dev);
315 u32 tmp;
316
317 DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, irq_dev, irq);
318
319 if (NULL == irq_dev || irq > DINO_IRQS) {
320 printk(KERN_WARNING "%s(): %d not a dino irq?\n",
321 __FUNCTION__, irq);
322 BUG();
323 return;
324 }
325
326 /* set the matching bit in the IMR register */
327 dino_dev->imr |= DINO_MASK_IRQ(irq); /* used in dino_isr() */
328 gsc_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
329
330 /* Emulate "Level Triggered" Interrupt
331 ** Basically, a driver is blowing it if the IRQ line is asserted
332 ** while the IRQ is disabled. But tulip.c seems to do that....
333 ** Give 'em a kluge award and a nice round of applause!
334 **
335 ** The gsc_write will generate an interrupt which invokes dino_isr().
336 ** dino_isr() will read IPR and find nothing. But then catch this
337 ** when it also checks ILR.
338 */
339 tmp = gsc_readl(dino_dev->hba.base_addr+DINO_ILR);
340 if (tmp & DINO_MASK_IRQ(irq)) {
341 DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
342 __FUNCTION__, tmp);
343 gsc_writel(dino_dev->txn_data, dino_dev->txn_addr);
344 }
345 }
346
347
348
349 static void
dino_enable_irq(void * irq_dev,int irq)350 dino_enable_irq(void *irq_dev, int irq)
351 {
352 struct dino_device *dino_dev = DINO_DEV(irq_dev);
353
354 /*
355 ** clear pending IRQ bits
356 **
357 ** This does NOT change ILR state!
358 ** See comments in dino_unmask_irq() for ILR usage.
359 */
360 gsc_readl(dino_dev->hba.base_addr+DINO_IPR);
361
362 dino_unmask_irq(irq_dev, irq);
363 }
364
365
366 static struct irq_region_ops dino_irq_ops = {
367 disable_irq: dino_mask_irq, /* ??? */
368 enable_irq: dino_enable_irq,
369 mask_irq: dino_mask_irq,
370 unmask_irq: dino_unmask_irq
371 };
372
373
374 /*
375 * Handle a Processor interrupt generated by Dino.
376 *
377 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
378 * wedging the CPU. Could be removed or made optional at some point.
379 */
380 static void
dino_isr(int irq,void * intr_dev,struct pt_regs * regs)381 dino_isr(int irq, void *intr_dev, struct pt_regs *regs)
382 {
383 struct dino_device *dino_dev = DINO_DEV(intr_dev);
384 u32 mask;
385 int ilr_loop = 100;
386 extern void do_irq(struct irqaction *a, int i, struct pt_regs *p);
387
388
389 /* read and acknowledge pending interrupts */
390 #ifdef DINO_DEBUG
391 dino_dev->dino_irr0 =
392 #endif
393 mask = gsc_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
394
395 ilr_again:
396 while (mask)
397 {
398 int irq;
399
400 /*
401 * Perform a binary search on set bits.
402 * `Less than Fatal' and PS2 interupts aren't supported.
403 */
404 if (mask & 0xf) {
405 if (mask & 0x3) {
406 irq = (mask & 0x1) ? 0 : 1; /* PCI INT A, B */
407 } else {
408 irq = (mask & 0x4) ? 2 : 3; /* PCI INT C, D */
409 }
410 } else {
411 if (mask & 0x30) {
412 irq = (mask & 0x10) ? 4 : 5; /* PCI INT E, F */
413 } else {
414 irq = (mask & 0x40) ? 6 : 10; /* GSC, RS232 */
415 }
416 }
417
418 mask &= ~(1<<irq);
419
420 DBG(KERN_WARNING "%s(%x, %p) mask %0x\n",
421 __FUNCTION__, irq, intr_dev, mask);
422 do_irq(&dino_dev->dino_region->action[irq],
423 dino_dev->dino_region->data.irqbase + irq,
424 regs);
425
426 }
427
428 /* Support for level triggered IRQ lines.
429 **
430 ** Dropping this support would make this routine *much* faster.
431 ** But since PCI requires level triggered IRQ line to share lines...
432 ** device drivers may assume lines are level triggered (and not
433 ** edge triggered like EISA/ISA can be).
434 */
435 mask = gsc_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
436 if (mask) {
437 if (--ilr_loop > 0)
438 goto ilr_again;
439 printk("Dino %lx: IRQ base %d, stuck IRQ lines? 0x%x\n", dino_dev->hba.base_addr, dino_dev->dino_region->data.irqbase, mask);
440 }
441 }
442
dino_choose_irq(struct parisc_device * dev)443 static int dino_choose_irq(struct parisc_device *dev)
444 {
445 int irq = -1;
446
447 switch (dev->id.sversion) {
448 case 0x00084: irq = 8; break; /* PS/2 */
449 case 0x0008c: irq = 10; break; /* RS232 */
450 case 0x00096: irq = 8; break; /* PS/2 */
451 }
452
453 return irq;
454 }
455
456 static void __init
dino_bios_init(void)457 dino_bios_init(void)
458 {
459 DBG("dino_bios_init\n");
460 }
461
462 /*
463 * dino_card_setup - Set up the memory space for a Dino in card mode.
464 * @bus: the bus under this dino
465 *
466 * Claim an 8MB chunk of unused IO space and call the generic PCI routines
467 * to set up the addresses of the devices on this bus.
468 */
469 #define _8MB 0x00800000UL
470 static int __init
dino_card_setup(struct pci_bus * bus,unsigned long base_addr)471 dino_card_setup(struct pci_bus *bus, unsigned long base_addr)
472 {
473 int i;
474 struct dino_device *dino_dev = DINO_DEV(bus->sysdata);
475 struct resource *res;
476
477 res = &dino_dev->hba.lmmio_space;
478 res->flags = IORESOURCE_MEM;
479
480 if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB,
481 (unsigned long) 0xfffffffff0000000UL | _8MB,
482 0xffffffffffffffffUL &~ _8MB, _8MB,
483 NULL, NULL) < 0) {
484 printk(KERN_WARNING "Dino: Failed to allocate memory region\n");
485 return -ENODEV;
486 }
487 bus->resource[1] = res;
488 bus->resource[0] = &(dino_dev->hba.io_space);
489
490 /* Now tell dino what range it has */
491 for (i = 1; i < 31; i++) {
492 if (res->start == (0xfffffffff0000000UL | i * _8MB))
493 break;
494 }
495 gsc_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
496
497 pcibios_assign_unassigned_resources(bus);
498 return 0;
499 }
500
501 static void __init
dino_card_fixup(struct pci_dev * dev)502 dino_card_fixup(struct pci_dev *dev)
503 {
504 u8 irq_pin;
505
506 /*
507 ** REVISIT: card-mode PCI-PCI expansion chassis do exist.
508 ** Not sure they were ever productized.
509 ** Die here since we'll die later in dino_inb() anyway.
510 */
511 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
512 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
513 }
514
515 /*
516 ** Set Latency Timer to 0xff (not a shared bus)
517 ** Set CACHELINE_SIZE.
518 */
519 dino_cfg_write16(dev, PCI_CACHE_LINE_SIZE, 0xff00 | L1_CACHE_BYTES/4);
520
521 /*
522 ** Program INT_LINE for card-mode devices.
523 ** The cards are hardwired according to this algorithm.
524 ** And it doesn't matter if PPB's are present or not since
525 ** the IRQ lines bypass the PPB.
526 **
527 ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
528 ** The additional "-1" adjusts for skewing the IRQ<->slot.
529 */
530 dino_cfg_read8(dev, PCI_INTERRUPT_PIN, &irq_pin);
531 dev->irq = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ;
532
533 /* Shouldn't really need to do this but it's in case someone tries
534 ** to bypass PCI services and look at the card themselves.
535 */
536 dino_cfg_write8(dev, PCI_INTERRUPT_LINE, dev->irq);
537 }
538
539
540 static void __init
dino_fixup_bus(struct pci_bus * bus)541 dino_fixup_bus(struct pci_bus *bus)
542 {
543 struct list_head *ln;
544 struct pci_dev *dev;
545 struct dino_device *dino_dev = DINO_DEV(bus->sysdata);
546 int port_base = HBA_PORT_BASE(dino_dev->hba.hba_num);
547
548 DBG(KERN_WARNING "%s(0x%p) bus %d sysdata 0x%p\n",
549 __FUNCTION__, bus, bus->secondary, bus->sysdata);
550
551 /* Firmware doesn't set up card-mode dino, so we have to */
552 if (is_card_dino(&dino_dev->hba.dev->id))
553 dino_card_setup(bus, dino_dev->hba.base_addr);
554
555 /* If this is a PCI-PCI Bridge, read the window registers etc */
556 if (bus->self)
557 pci_read_bridge_bases(bus);
558
559 list_for_each(ln, &bus->devices) {
560 int i;
561
562 dev = pci_dev_b(ln);
563 if (is_card_dino(&dino_dev->hba.dev->id))
564 dino_card_fixup(dev);
565
566 /*
567 ** P2PB's only have 2 BARs, no IRQs.
568 ** I'd like to just ignore them for now.
569 */
570 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
571 continue;
572
573 /* Adjust the I/O Port space addresses */
574 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
575 struct resource *res = &dev->resource[i];
576 if (res->flags & IORESOURCE_IO) {
577 res->start |= port_base;
578 res->end |= port_base;
579 }
580 #ifdef __LP64__
581 /* Sign Extend MMIO addresses */
582 else if (res->flags & IORESOURCE_MEM) {
583 res->start |= 0xffffffff00000000UL;
584 res->end |= 0xffffffff00000000UL;
585 }
586 #endif
587 }
588
589 /* Adjust INT_LINE for that busses region */
590 dev->irq = dino_dev->dino_region->data.irqbase + dev->irq;
591 }
592 }
593
594
595 struct pci_bios_ops dino_bios_ops = {
596 dino_bios_init,
597 dino_fixup_bus /* void dino_fixup_bus(struct pci_bus *bus) */
598 };
599
600
601 /*
602 * Initialise a DINO controller chip
603 */
604 static void __init
dino_card_init(struct dino_device * dino_dev)605 dino_card_init(struct dino_device *dino_dev)
606 {
607 u32 brdg_feat = 0x00784e05;
608
609 gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
610 gsc_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
611 gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
612
613 #if 1
614 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
615 /*
616 ** PCX-L processors don't support XQL like Dino wants it.
617 ** PCX-L2 ignore XQL signal and it doesn't matter.
618 */
619 brdg_feat &= ~0x4; /* UXQL */
620 #endif
621 gsc_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
622
623 /*
624 ** Don't enable address decoding until we know which I/O range
625 ** currently is available from the host. Only affects MMIO
626 ** and not I/O port space.
627 */
628 gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
629
630 gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
631 gsc_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
632 gsc_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
633
634 gsc_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
635 gsc_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
636 gsc_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
637
638 /* Disable PAMR before writing PAPR */
639 gsc_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
640 gsc_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
641 gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
642
643 /*
644 ** Dino ERS encourages enabling FBB (0x6f).
645 ** We can't until we know *all* devices below us can support it.
646 ** (Something in device configuration header tells us).
647 */
648 gsc_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
649
650 /* Somewhere, the PCI spec says give devices 1 second
651 ** to recover from the #RESET being de-asserted.
652 ** Experience shows most devices only need 10ms.
653 ** This short-cut speeds up booting significantly.
654 */
655 mdelay(pci_post_reset_delay);
656 }
657
658 static int __init
dino_bridge_init(struct dino_device * dino_dev,const char * name)659 dino_bridge_init(struct dino_device *dino_dev, const char *name)
660 {
661 unsigned long io_addr, bpos;
662 int result;
663 struct resource *res;
664 /*
665 * Decoding IO_ADDR_EN only works for Built-in Dino
666 * since PDC has already initialized this.
667 */
668
669 io_addr = gsc_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
670 if (io_addr == 0) {
671 printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
672 return -ENODEV;
673 }
674
675 for (bpos = 0; (io_addr & (1 << bpos)) == 0; bpos++)
676 ;
677
678 res = &dino_dev->hba.lmmio_space;
679 res->flags = IORESOURCE_MEM;
680
681 res->start = (unsigned long)(signed int)(0xf0000000 | (bpos << 23));
682 res->end = res->start + 8 * 1024 * 1024 - 1;
683
684 result = ccio_request_resource(dino_dev->hba.dev, res);
685 if (result < 0) {
686 printk(KERN_ERR "%s: failed to claim PCI Bus address space!\n", name);
687 return result;
688 }
689
690 return 0;
691 }
692
dino_common_init(struct parisc_device * dev,struct dino_device * dino_dev,const char * name)693 static int __init dino_common_init(struct parisc_device *dev,
694 struct dino_device *dino_dev, const char *name)
695 {
696 int status;
697 u32 eim;
698 struct gsc_irq gsc_irq;
699 struct resource *res;
700
701 pcibios_register_hba(&dino_dev->hba);
702
703 pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */
704 pci_port = &dino_port_ops;
705
706 /*
707 ** Note: SMP systems can make use of IRR1/IAR1 registers
708 ** But it won't buy much performance except in very
709 ** specific applications/configurations. Note Dino
710 ** still only has 11 IRQ input lines - just map some of them
711 ** to a different processor.
712 */
713 dino_dev->irq = gsc_alloc_irq(&gsc_irq);
714 dino_dev->txn_addr = gsc_irq.txn_addr;
715 dino_dev->txn_data = gsc_irq.txn_data;
716 eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data;
717
718 /*
719 ** Dino needs a PA "IRQ" to get a processor's attention.
720 ** arch/parisc/kernel/irq.c returns an EIRR bit.
721 */
722 if (dino_dev->irq < 0) {
723 printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
724 return 1;
725 }
726
727 status = request_irq(dino_dev->irq, dino_isr, 0, name, dino_dev);
728 if (status) {
729 printk(KERN_WARNING "%s: request_irq() failed with %d\n",
730 name, status);
731 return 1;
732 }
733
734 /*
735 ** Tell generic interrupt support we have 11 bits which need
736 ** be checked in the interrupt handler.
737 */
738 dino_dev->dino_region = alloc_irq_region(DINO_IRQS, &dino_irq_ops,
739 name, dino_dev);
740
741 if (NULL == dino_dev->dino_region) {
742 printk(KERN_WARNING "%s: alloc_irq_region() failed\n", name);
743 return 1;
744 }
745
746 /* Support the serial port which is sometimes attached on built-in
747 * Dino / Cujo chips.
748 */
749
750 fixup_child_irqs(dev, dino_dev->dino_region->data.irqbase,
751 dino_choose_irq);
752
753 /*
754 ** This enables DINO to generate interrupts when it sees
755 ** any of it's inputs *change*. Just asserting an IRQ
756 ** before it's enabled (ie unmasked) isn't good enough.
757 */
758 gsc_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
759
760 /*
761 ** Some platforms don't clear Dino's IRR0 register at boot time.
762 ** Reading will clear it now.
763 */
764 gsc_readl(dino_dev->hba.base_addr+DINO_IRR0);
765
766 /* allocate I/O Port resource region */
767 res = &dino_dev->hba.io_space;
768 if (dev->id.hversion == 0x680 || is_card_dino(&dev->id)) {
769 res->name = "Dino I/O Port";
770 dino_dev->hba.lmmio_space.name = "Dino LMMIO";
771 } else {
772 res->name = "Cujo I/O Port";
773 dino_dev->hba.lmmio_space.name = "Cujo LMMIO";
774 }
775 res->start = HBA_PORT_BASE(dino_dev->hba.hba_num);
776 res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
777 res->flags = IORESOURCE_IO; /* do not mark it busy ! */
778 if (request_resource(&ioport_resource, res) < 0) {
779 printk(KERN_ERR "%s: request I/O Port region failed 0x%lx/%lx (hpa 0x%lx)\n",
780 name, res->start, res->end, dino_dev->hba.base_addr);
781 return 1;
782 }
783
784 return 0;
785 }
786
787 #define CUJO_RAVEN_ADDR 0xfffffffff1000000UL
788 #define CUJO_FIREHAWK_ADDR 0xfffffffff1604000UL
789 #define CUJO_RAVEN_BADPAGE 0x01003000UL
790 #define CUJO_FIREHAWK_BADPAGE 0x01607000UL
791
792 static const char *dino_vers[] = {
793 "2.0",
794 "2.1",
795 "3.0",
796 "3.1"
797 };
798
799 static const char *cujo_vers[] = {
800 "1.0",
801 "2.0"
802 };
803
804 void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
805
806 /*
807 ** Determine if dino should claim this chip (return 0) or not (return 1).
808 ** If so, initialize the chip appropriately (card-mode vs bridge mode).
809 ** Much of the initialization is common though.
810 */
811 static int __init
dino_driver_callback(struct parisc_device * dev)812 dino_driver_callback(struct parisc_device *dev)
813 {
814 struct dino_device *dino_dev; // Dino specific control struct
815 const char *version = "unknown";
816 const char *name = "Dino";
817 int is_cujo = 0;
818
819 if (is_card_dino(&dev->id)) {
820 version = "3.x (card mode)";
821 } else {
822 if(dev->id.hversion == 0x680) {
823 if (dev->id.hversion_rev < 4) {
824 version = dino_vers[dev->id.hversion_rev];
825 }
826 } else {
827 name = "Cujo";
828 is_cujo = 1;
829 if (dev->id.hversion_rev < 2) {
830 version = cujo_vers[dev->id.hversion_rev];
831 }
832 }
833 }
834
835 printk("%s version %s found at 0x%lx\n", name, version, dev->hpa);
836
837 if (!request_mem_region(dev->hpa, PAGE_SIZE, name)) {
838 printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%ld)!\n",
839 dev->hpa);
840 return 1;
841 }
842
843 /* Check for bugs */
844 if (is_cujo && dev->id.hversion_rev == 1) {
845 #ifdef CONFIG_IOMMU_CCIO
846 printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
847 if (dev->hpa == CUJO_RAVEN_ADDR) {
848 ccio_cujo20_fixup(dev->parent, CUJO_RAVEN_BADPAGE);
849 } else if (dev->hpa == CUJO_FIREHAWK_ADDR) {
850 ccio_cujo20_fixup(dev->parent, CUJO_FIREHAWK_BADPAGE);
851 } else {
852 printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", dev->hpa);
853 }
854 #endif
855 } else if (!is_cujo && !is_card_dino(&dev->id) &&
856 dev->id.hversion_rev < 3) {
857 printk(KERN_WARNING
858 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
859 "data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n"
860 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
861 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
862 dev->id.hversion_rev);
863 /* REVISIT: why are C200/C240 listed in the README table but not
864 ** "Models affected"? Could be an omission in the original literature.
865 */
866 }
867
868 dino_dev = kmalloc(sizeof(struct dino_device), GFP_KERNEL);
869 if (!dino_dev) {
870 printk("dino_init_chip - couldn't alloc dino_device\n");
871 return 1;
872 }
873
874 memset(dino_dev, 0, sizeof(struct dino_device));
875
876 dino_dev->hba.dev = dev;
877 dino_dev->hba.base_addr = dev->hpa; /* faster access */
878 dino_dev->hba.lmmio_space_offset = 0; /* CPU addrs == bus addrs */
879 dino_dev->dinosaur_pen = SPIN_LOCK_UNLOCKED;
880 dino_dev->hba.iommu = ccio_get_iommu(dev);
881
882 if (is_card_dino(&dev->id)) {
883 dino_card_init(dino_dev);
884 } else {
885 dino_bridge_init(dino_dev, name);
886 }
887
888 if (dino_common_init(dev, dino_dev, name))
889 return 1;
890
891 /*
892 ** It's not used to avoid chicken/egg problems
893 ** with configuration accessor functions.
894 */
895 dino_dev->hba.hba_bus = pci_scan_bus(dino_dev->hba.hba_num,
896 &dino_cfg_ops, dino_dev);
897
898 return 0;
899 }
900
901 /*
902 * Normally, we would just test sversion. But the Elroy PCI adapter has
903 * the same sversion as Dino, so we have to check hversion as well.
904 * Unfortunately, the J2240 PDC reports the wrong hversion for the first
905 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
906 */
907 static struct parisc_device_id dino_tbl[] = {
908 { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D }, /* Card-mode Dino. */
909 { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x444, 0x08080 }, /* Same card in a 715. Bug? */
910 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */
911 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */
912 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */
913 { 0, }
914 };
915
916 static struct parisc_driver dino_driver = {
917 name: "Dino",
918 id_table: dino_tbl,
919 probe: dino_driver_callback,
920 };
921
922 /*
923 * One time initialization to let the world know Dino is here.
924 * This is the only routine which is NOT static.
925 * Must be called exactly once before pci_init().
926 */
dino_init(void)927 int __init dino_init(void)
928 {
929 register_parisc_driver(&dino_driver);
930 return 0;
931 }
932
933