1 /* $Id: sh-sci.h,v 1.1.1.1.2.5 2003/09/03 08:37:41 kkojima Exp $
2 *
3 * linux/drivers/char/sh-sci.h
4 *
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
9 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
10 *
11 */
12 #include <linux/config.h>
13
14 /* Values for sci_port->type */
15 #define PORT_SCI 0
16 #define PORT_SCIF 1
17 #define PORT_IRDA 1 /* XXX: temporary assignment */
18
19 /* Offsets into the sci_port->irqs array */
20 #define SCIx_ERI_IRQ 0
21 #define SCIx_RXI_IRQ 1
22 #define SCIx_TXI_IRQ 2
23
24 /* ERI, RXI, TXI, BRI */
25 #define SCI_IRQS { 23, 24, 25, 0 }
26 #define SH3_SCIF_IRQS { 56, 57, 59, 58 }
27 #define SH3_IRDA_IRQS { 52, 53, 55, 54 }
28 #define SH4_SCIF_IRQS { 40, 41, 43, 42 }
29 #define STB1_SCIF1_IRQS {23, 24, 26, 25 }
30 #define SH5_SCIF_IRQS { 39, 40, 42 }
31 #define SH7300_SCIF0_IRQS {80, 80, 80, 80 }
32
33 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
34 # define SCI_NPORTS 1
35 # define SCI_INIT { \
36 { {}, PORT_SCI, 0xfffffe80, SCI_IRQS, sci_init_pins_sci } \
37 }
38 # define SCSPTR 0xffffff7c /* 8 bit */
39 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
40 # define SCI_ONLY
41 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
42 # define SCI_NPORTS 1
43 # define SCI_INIT { \
44 { {}, PORT_SCIF, 0xA4430000, SH7300_SCIF0_IRQS, sci_init_pins_scif }, \
45 }
46 # define SCPCR 0xA4050116 /* 16 bit SCIF */
47 # define SCPDR 0xA4050136 /* 16 bit SCIF */
48 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
49 # define SCIF_ONLY
50
51 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
52 # define SCI_NPORTS 3
53 # define SCI_INIT { \
54 { {}, PORT_SCI, 0xfffffe80, SCI_IRQS, sci_init_pins_sci }, \
55 { {}, PORT_SCIF, 0xA4000150, SH3_SCIF_IRQS, sci_init_pins_scif }, \
56 { {}, PORT_SCIF, 0xA4000140, SH3_IRDA_IRQS, sci_init_pins_irda } \
57 }
58 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
59 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
60 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
61 # define SCI_AND_SCIF
62 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
63 # define SCI_NPORTS 2
64 # define SCI_INIT { \
65 { {}, PORT_SCI, 0xffe00000, SCI_IRQS, sci_init_pins_sci }, \
66 { {}, PORT_SCIF, 0xFFE80000, SH4_SCIF_IRQS, sci_init_pins_scif } \
67 }
68 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
69 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
70 # define SCIF_ORER 0x0001 /* overrun error bit */
71 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
72 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
73 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
74 # define SCI_AND_SCIF
75 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
76 # define SCI_NPORTS 1
77 # define SCI_INIT { \
78 { {}, PORT_SCIF, 0xFFE80000, SH4_SCIF_IRQS, sci_init_pins_scif } \
79 }
80 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
81 # define SCIF_ORER 0x0001 /* overrun error bit */
82 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
83 # define SCIF_ONLY
84 #elif defined(CONFIG_CPU_SUBTYPE_ST40)
85 # define SCI_NPORTS 2
86 # define SCI_INIT { \
87 { {}, PORT_SCIF, 0xffe00000, STB1_SCIF1_IRQS, sci_init_pins_scif }, \
88 { {}, PORT_SCIF, 0xffe80000, SH4_SCIF_IRQS, sci_init_pins_scif } \
89 }
90 # define SCSPTR1 0xffe00020 /* 16 bit SCIF */
91 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
92 # define SCIF_ORER 0x0001 /* overrun error bit */
93 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
94 # define SCIF_ONLY
95
96 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
97 # include <asm/hardware.h>
98 # define SCIF_BASE_ADDR 0x01030000
99 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
100 # define SCIF_PTR2_OFFS 0x0000020
101 # define SCIF_LSR2_OFFS 0x0000024
102 # define SCI_NPORTS 1
103 # define SCI_INIT { \
104 { {}, PORT_SCIF, 0, \
105 SH5_SCIF_IRQS, sci_init_pins_scif } \
106 }
107 # define SCSPTR2 (SCIF_ADDR_SH5+SCIF_PTR2_OFFS) /* 16 bit SCIF */
108 # define SCLSR2 (SCIF_ADDR_SH5+SCIF_LSR2_OFFS) /* 16 bit SCIF */
109 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
110 TE=1,RE=1,REIE=1 */
111 # define SCIF_ONLY
112
113
114 #else
115 # error CPU subtype not defined
116 #endif
117
118 /* SCSCR */
119 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
120 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
121 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
122 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
123 /* SCI_CTRL_FLAGS_REIE 0x08 * 7750 SCIF */
124 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
125 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
126 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
127 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
128
129 /* SCxSR SCI */
130 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
131 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
132 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
133 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
134 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
135 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
136 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
137 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
138
139 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
140
141 /* SCxSR SCIF */
142 #define SCIF_ER 0x0080 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
143 #define SCIF_TEND 0x0040 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
144 #define SCIF_TDFE 0x0020 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
145 #define SCIF_BRK 0x0010 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
146 #define SCIF_FER 0x0008 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
147 #define SCIF_PER 0x0004 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
148 #define SCIF_RDF 0x0002 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
149 #define SCIF_DR 0x0001 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
150
151 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
152 #define SCIF_ORER 0x0200
153 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
154 #else
155 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
156 #endif
157
158 #if defined(SCI_ONLY)
159 # define SCxSR_TEND(port) SCI_TEND
160 # define SCxSR_ERRORS(port) SCI_ERRORS
161 # define SCxSR_RDxF(port) SCI_RDRF
162 # define SCxSR_TDxE(port) SCI_TDRE
163 # define SCxSR_ORER(port) SCI_ORER
164 # define SCxSR_FER(port) SCI_FER
165 # define SCxSR_PER(port) SCI_PER
166 # define SCxSR_BRK(port) 0x00
167 # define SCxSR_RDxF_CLEAR(port) 0xbc
168 # define SCxSR_ERROR_CLEAR(port) 0xc4
169 # define SCxSR_TDxE_CLEAR(port) 0x78
170 # define SCxSR_BREAK_CLEAR(port) 0xc4
171 #elif defined(SCIF_ONLY)
172 # define SCxSR_TEND(port) SCIF_TEND
173 # define SCxSR_ERRORS(port) SCIF_ERRORS
174 # define SCxSR_RDxF(port) SCIF_RDF
175 # define SCxSR_TDxE(port) SCIF_TDFE
176 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
177 # define SCxSR_ORER(port) SCIF_ORER
178 #else
179 # define SCxSR_ORER(port) 0x0000
180 #endif
181 # define SCxSR_FER(port) SCIF_FER
182 # define SCxSR_PER(port) SCIF_PER
183 # define SCxSR_BRK(port) SCIF_BRK
184 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
185 # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
186 # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
187 # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
188 # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
189 #else
190 # define SCxSR_RDxF_CLEAR(port) 0x00fc
191 # define SCxSR_ERROR_CLEAR(port) 0x0073
192 # define SCxSR_TDxE_CLEAR(port) 0x00df
193 # define SCxSR_BREAK_CLEAR(port) 0x00e3
194 #endif
195 #else
196 # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
197 # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
198 # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
199 # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
200 # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
201 # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
202 # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
203 # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
204 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
205 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
206 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
207 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
208 #endif
209
210 /* SCFCR */
211 #define SCFCR_RFRST 0x0002
212 #define SCFCR_TFRST 0x0004
213 #define SCFCR_TCRST 0x4000
214 #define SCFCR_MCE 0x0008
215
216 #define SCI_MAJOR 204
217 #define SCI_MINOR_START 8
218
219 /* Generic serial flags */
220 #define SCI_RX_THROTTLE 0x0000001
221
222 #define SCI_MAGIC 0xbabeface
223
224 /*
225 * Events are used to schedule things to happen at timer-interrupt
226 * time, instead of at rs interrupt time.
227 */
228 #define SCI_EVENT_WRITE_WAKEUP 0
229
230 struct sci_port {
231 struct gs_port gs;
232 int type;
233 unsigned int base;
234 unsigned char irqs[4]; /* ERI, RXI, TXI, BRI */
235 void (*init_pins)(struct sci_port* port, unsigned int cflag);
236 unsigned int old_cflag;
237 struct async_icount icount;
238 struct tq_struct tqueue;
239 unsigned long event;
240 int break_flag;
241 };
242
243 #define SCI_IN(size, offset) \
244 unsigned int addr = port->base + (offset); \
245 if ((size) == 8) { \
246 return ctrl_inb(addr); \
247 } else { \
248 return ctrl_inw(addr); \
249 }
250 #define SCI_OUT(size, offset, value) \
251 unsigned int addr = port->base + (offset); \
252 if ((size) == 8) { \
253 ctrl_outb(value, addr); \
254 } else { \
255 ctrl_outw(value, addr); \
256 }
257
258 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
259 static inline unsigned int sci_##name##_in(struct sci_port* port) \
260 { \
261 if (port->type == PORT_SCI) { \
262 SCI_IN(sci_size, sci_offset) \
263 } else { \
264 SCI_IN(scif_size, scif_offset); \
265 } \
266 } \
267 static inline void sci_##name##_out(struct sci_port* port, unsigned int value) \
268 { \
269 if (port->type == PORT_SCI) { \
270 SCI_OUT(sci_size, sci_offset, value) \
271 } else { \
272 SCI_OUT(scif_size, scif_offset, value); \
273 } \
274 }
275
276 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
277 static inline unsigned int sci_##name##_in(struct sci_port* port) \
278 { \
279 SCI_IN(scif_size, scif_offset); \
280 } \
281 static inline void sci_##name##_out(struct sci_port* port, unsigned int value) \
282 { \
283 SCI_OUT(scif_size, scif_offset, value); \
284 }
285
286 #ifdef __sh3__
287 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
288 #define SCIF_FNS(name, scif_offset, scif_size) \
289 CPU_SCIF_FNS(name, scif_offset, scif_size)
290 #else
291 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
292 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
293 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
294 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
295 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
296 #endif
297 #else
298 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
299 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
300 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
301 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
302 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
303 #endif
304
305 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
306 SCIF_FNS(SCSMR, 0x00, 16)
307 SCIF_FNS(SCBRR, 0x04, 8)
308 SCIF_FNS(SCSCR, 0x08, 16)
309 SCIF_FNS(SCTDSR, 0x0c, 8)
310 SCIF_FNS(SCFER, 0x10, 16)
311 SCIF_FNS(SCxSR, 0x14, 16)
312 SCIF_FNS(SCFCR, 0x18, 16)
313 SCIF_FNS(SCFDR, 0x1c, 16)
314 SCIF_FNS(SCxTDR, 0x20, 8)
315 SCIF_FNS(SCxRDR, 0x24, 8)
316 #else
317 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 */
318 /* name off sz off sz off sz off sz */
319 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16)
320 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8)
321 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16)
322 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8)
323 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16)
324 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8)
325 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
326 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
327 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
328 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
329 #endif
330
331 #define sci_in(port, reg) sci_##reg##_in(port)
332 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
333
334 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
sci_rxd_in(struct sci_port * port)335 static inline int sci_rxd_in(struct sci_port *port)
336 {
337 if (port->base == 0xfffffe80)
338 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
339 return 1;
340 }
341 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
342 static inline int sci_rxd_in(struct sci_port *port)
343 {
344 if (port->base == 0xa4430000)
345 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
346 return 1;
347 }
348 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
349 static inline int sci_rxd_in(struct sci_port *port)
350 {
351 if (port->base == 0xfffffe80)
352 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
353 if (port->base == 0xa4000150)
354 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
355 if (port->base == 0xa4000140)
356 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
357 return 1;
358 }
359 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
360 static inline int sci_rxd_in(struct sci_port *port)
361 {
362 #ifndef SCIF_ONLY
363 if (port->base == 0xffe00000)
364 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
365 #endif
366 #ifndef SCI_ONLY
367 if (port->base == 0xffe80000)
368 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
369 #endif
370 return 1;
371 }
372 #elif defined(CONFIG_CPU_SUBTYPE_ST40)
373 static inline int sci_rxd_in(struct sci_port *port)
374 {
375 if (port->base == 0xffe00000)
376 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
377 else
378 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
379
380 }
381 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
382 static inline int sci_rxd_in(struct sci_port *port)
383 {
384 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
385 }
386
387 #endif
388
389 /*
390 * Values for the BitRate Register (SCBRR)
391 *
392 * The values are actually divisors for a frequency which can
393 * be internal to the SH3 (14.7456MHz) or derived from an external
394 * clock source. This driver assumes the internal clock is used;
395 * to support using an external clock source, config options or
396 * possibly command-line options would need to be added.
397 *
398 * Also, to support speeds below 2400 (why?) the lower 2 bits of
399 * the SCSMR register would also need to be set to non-zero values.
400 *
401 * -- Greg Banks 27Feb2000
402 *
403 * Answer: The SCBRR register is only eight bits, and the value in
404 * it gets larger with lower baud rates. At around 2400 (depending on
405 * the peripherial module clock) you run out of bits. However the
406 * lower two bits of SCSMR allow the module clock to be divided down,
407 * scaling the value which is needed in SCBRR.
408 *
409 * -- Stuart Menefy - 23 May 2000
410 *
411 * I meant, why would anyone bother with bitrates below 2400.
412 *
413 * -- Greg Banks - 7Jul2000
414 *
415 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
416 * tape reader as a console!
417 *
418 * -- Mitch Davis - 15 Jul 2000
419 */
420
421 #define PCLK (current_cpu_data.module_clock)
422
423 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
424 #define SCBRR_VALUE(bps) ((PCLK+16*bps)/(16*bps)-1)
425 #else
426 #define SCBRR_VALUE(bps) ((PCLK+16*bps)/(32*bps)-1)
427 #endif
428 #define BPS_2400 SCBRR_VALUE(2400)
429 #define BPS_4800 SCBRR_VALUE(4800)
430 #define BPS_9600 SCBRR_VALUE(9600)
431 #define BPS_19200 SCBRR_VALUE(19200)
432 #define BPS_38400 SCBRR_VALUE(38400)
433 #define BPS_57600 SCBRR_VALUE(57600)
434 #define BPS_115200 SCBRR_VALUE(115200)
435 #define BPS_230400 SCBRR_VALUE(230400)
436
437