1 /* sgiserial.h: Definitions for the SGI Zilog85C30 serial driver.
2 *
3 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
4 */
5 #ifndef _SGI_SERIAL_H
6 #define _SGI_SERIAL_H
7
8 /* Just one channel */
9 struct sgi_zschannel {
10 #ifdef __MIPSEB__
11 volatile unsigned char unused0[3];
12 volatile unsigned char control;
13 volatile unsigned char unused1[3];
14 volatile unsigned char data;
15 #else /* __MIPSEL__ */
16 volatile unsigned char control;
17 volatile unsigned char unused0[3];
18 volatile unsigned char data;
19 volatile unsigned char unused1[3];
20 #endif
21 };
22
23 /* The address space layout for each zs chip. Yes they are
24 * backwards.
25 */
26 struct sgi_zslayout {
27 struct sgi_zschannel channelB;
28 struct sgi_zschannel channelA;
29 };
30
31 #define NUM_ZSREGS 16
32
33 struct serial_struct {
34 int type;
35 int line;
36 unsigned int port;
37 int irq;
38 int flags;
39 int xmit_fifo_size;
40 int custom_divisor;
41 int baud_base;
42 unsigned short close_delay;
43 char reserved_char[2];
44 int hub6;
45 unsigned short closing_wait; /* time to wait before closing */
46 unsigned short closing_wait2; /* no longer used... */
47 int reserved[4];
48 };
49
50 /*
51 * For the close wait times, 0 means wait forever for serial port to
52 * flush its output. 65535 means don't wait at all.
53 */
54 #define ZILOG_CLOSING_WAIT_INF 0
55 #define ZILOG_CLOSING_WAIT_NONE 65535
56
57 /*
58 * Definitions for ZILOG_struct (and serial_struct) flags field
59 */
60 #define ZILOG_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes
61 on the callout port */
62 #define ZILOG_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */
63 #define ZILOG_SAK 0x0004 /* Secure Attention Key (Orange book) */
64 #define ZILOG_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */
65
66 #define ZILOG_SPD_MASK 0x0030
67 #define ZILOG_SPD_HI 0x0010 /* Use 56000 instead of 38400 bps */
68
69 #define ZILOG_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */
70 #define ZILOG_SPD_CUST 0x0030 /* Use user-specified divisor */
71
72 #define ZILOG_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */
73 #define ZILOG_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */
74 #define ZILOG_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */
75 #define ZILOG_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */
76 #define ZILOG_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */
77
78 #define ZILOG_FLAGS 0x0FFF /* Possible legal ZILOG flags */
79 #define ZILOG_USR_MASK 0x0430 /* Legal flags that non-privileged
80 * users can set or reset */
81
82 /* Internal flags used only by kernel/chr_drv/serial.c */
83 #define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */
84 #define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */
85 #define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
86 #define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
87 #define ZILOG_CLOSING 0x08000000 /* Serial port is closing */
88 #define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */
89 #define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */
90
91 /* Software state per channel */
92
93 #ifdef __KERNEL__
94 /*
95 * This is our internal structure for each serial port's state.
96 *
97 * Many fields are paralleled by the structure used by the serial_struct
98 * structure.
99 *
100 * For definitions of the flags field, see tty.h
101 */
102
103 struct sgi_serial {
104 struct sgi_serial *zs_next; /* For IRQ servicing chain */
105 struct sgi_zschannel *zs_channel; /* Channel registers */
106 unsigned char read_reg_zero;
107
108 char soft_carrier; /* Use soft carrier on this channel */
109 char cons_keyb; /* Channel runs the keyboard */
110 char cons_mouse; /* Channel runs the mouse */
111 char break_abort; /* Is serial console in, so process brk/abrt */
112 char kgdb_channel; /* Kgdb is running on this channel */
113 char is_cons; /* Is this our console. */
114
115 /* We need to know the current clock divisor
116 * to read the bps rate the chip has currently
117 * loaded.
118 */
119 unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */
120 int zs_baud;
121
122 /* Current write register values */
123 unsigned char curregs[NUM_ZSREGS];
124
125 char change_needed;
126
127 int magic;
128 int baud_base;
129 unsigned int port;
130 int irq;
131 int flags; /* defined in tty.h */
132 int type; /* UART type */
133 struct tty_struct *tty;
134 int read_status_mask;
135 int ignore_status_mask;
136 int timeout;
137 int xmit_fifo_size;
138 int custom_divisor;
139 int x_char; /* xon/xoff character */
140 int close_delay;
141 unsigned short closing_wait;
142 unsigned short closing_wait2;
143 unsigned long event;
144 unsigned long last_active;
145 int line;
146 int count; /* # of fd on device */
147 int blocked_open; /* # of blocked opens */
148 long session; /* Session of opening process */
149 long pgrp; /* pgrp of opening process */
150 unsigned char *xmit_buf;
151 int xmit_head;
152 int xmit_tail;
153 int xmit_cnt;
154 struct tq_struct tqueue;
155 struct tq_struct tqueue_hangup;
156 struct termios normal_termios;
157 struct termios callout_termios;
158 wait_queue_head_t open_wait;
159 wait_queue_head_t close_wait;
160 };
161
162
163 #define SERIAL_MAGIC 0x5301
164
165 /*
166 * The size of the serial xmit buffer is 1 page.
167 */
168 #define SERIAL_XMIT_SIZE PAGE_SIZE
169
170 /*
171 * Events are used to schedule things to happen at timer-interrupt
172 * time, instead of at rs interrupt time.
173 */
174 #define RS_EVENT_WRITE_WAKEUP 0
175
176 #endif /* __KERNEL__ */
177
178 /* Conversion routines to/from brg time constants from/to bits
179 * per second.
180 */
181 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
182 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
183
184 /* The Zilog register set */
185
186 #define FLAG 0x7e
187
188 /* Write Register 0 */
189 #define R0 0 /* Register selects */
190 #define R1 1
191 #define R2 2
192 #define R3 3
193 #define R4 4
194 #define R5 5
195 #define R6 6
196 #define R7 7
197 #define R8 8
198 #define R9 9
199 #define R10 10
200 #define R11 11
201 #define R12 12
202 #define R13 13
203 #define R14 14
204 #define R15 15
205
206 #define NULLCODE 0 /* Null Code */
207 #define POINT_HIGH 0x8 /* Select upper half of registers */
208 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
209 #define SEND_ABORT 0x18 /* HDLC Abort */
210 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
211 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
212 #define ERR_RES 0x30 /* Error Reset */
213 #define RES_H_IUS 0x38 /* Reset highest IUS */
214
215 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
216 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
217 #define RES_EOM_L 0xC0 /* Reset EOM latch */
218
219 /* Write Register 1 */
220
221 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
222 #define TxINT_ENAB 0x2 /* Tx Int Enable */
223 #define PAR_SPEC 0x4 /* Parity is special condition */
224
225 #define RxINT_DISAB 0 /* Rx Int Disable */
226 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
227 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
228 #define INT_ERR_Rx 0x18 /* Int on error only */
229
230 #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
231 #define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
232 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
233
234 /* Write Register #2 (Interrupt Vector) */
235
236 /* Write Register 3 */
237
238 #define RxENABLE 0x1 /* Rx Enable */
239 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
240 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
241 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
242 #define ENT_HM 0x10 /* Enter Hunt Mode */
243 #define AUTO_ENAB 0x20 /* Auto Enables */
244 #define Rx5 0x0 /* Rx 5 Bits/Character */
245 #define Rx7 0x40 /* Rx 7 Bits/Character */
246 #define Rx6 0x80 /* Rx 6 Bits/Character */
247 #define Rx8 0xc0 /* Rx 8 Bits/Character */
248
249 /* Write Register 4 */
250
251 #define PAR_ENA 0x1 /* Parity Enable */
252 #define PAR_EVEN 0x2 /* Parity Even/Odd* */
253
254 #define SYNC_ENAB 0 /* Sync Modes Enable */
255 #define SB1 0x4 /* 1 stop bit/char */
256 #define SB15 0x8 /* 1.5 stop bits/char */
257 #define SB2 0xc /* 2 stop bits/char */
258
259 #define MONSYNC 0 /* 8 Bit Sync character */
260 #define BISYNC 0x10 /* 16 bit sync character */
261 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
262 #define EXTSYNC 0x30 /* External Sync Mode */
263
264 #define X1CLK 0x0 /* x1 clock mode */
265 #define X16CLK 0x40 /* x16 clock mode */
266 #define X32CLK 0x80 /* x32 clock mode */
267 #define X64CLK 0xC0 /* x64 clock mode */
268
269 /* Write Register 5 */
270
271 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
272 #define RTS 0x2 /* RTS */
273 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
274 #define TxENAB 0x8 /* Tx Enable */
275 #define SND_BRK 0x10 /* Send Break */
276 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
277 #define Tx7 0x20 /* Tx 7 bits/character */
278 #define Tx6 0x40 /* Tx 6 bits/character */
279 #define Tx8 0x60 /* Tx 8 bits/character */
280 #define DTR 0x80 /* DTR */
281
282 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
283
284 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
285
286 /* Write Register 8 (transmit buffer) */
287
288 /* Write Register 9 (Master interrupt control) */
289 #define VIS 1 /* Vector Includes Status */
290 #define NV 2 /* No Vector */
291 #define DLC 4 /* Disable Lower Chain */
292 #define MIE 8 /* Master Interrupt Enable */
293 #define STATHI 0x10 /* Status high */
294 #define NORESET 0 /* No reset on write to R9 */
295 #define CHRB 0x40 /* Reset channel B */
296 #define CHRA 0x80 /* Reset channel A */
297 #define FHWRES 0xc0 /* Force hardware reset */
298
299 /* Write Register 10 (misc control bits) */
300 #define BIT6 1 /* 6 bit/8bit sync */
301 #define LOOPMODE 2 /* SDLC Loop mode */
302 #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
303 #define MARKIDLE 8 /* Mark/flag on idle */
304 #define GAOP 0x10 /* Go active on poll */
305 #define NRZ 0 /* NRZ mode */
306 #define NRZI 0x20 /* NRZI mode */
307 #define FM1 0x40 /* FM1 (transition = 1) */
308 #define FM0 0x60 /* FM0 (transition = 0) */
309 #define CRCPS 0x80 /* CRC Preset I/O */
310
311 /* Write Register 11 (Clock Mode control) */
312 #define TRxCXT 0 /* TRxC = Xtal output */
313 #define TRxCTC 1 /* TRxC = Transmit clock */
314 #define TRxCBR 2 /* TRxC = BR Generator Output */
315 #define TRxCDP 3 /* TRxC = DPLL output */
316 #define TRxCOI 4 /* TRxC O/I */
317 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
318 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
319 #define TCBR 0x10 /* Transmit clock = BR Generator output */
320 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
321 #define RCRTxCP 0 /* Receive clock = RTxC pin */
322 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
323 #define RCBR 0x40 /* Receive clock = BR Generator output */
324 #define RCDPLL 0x60 /* Receive clock = DPLL output */
325 #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
326
327 /* Write Register 12 (lower byte of baud rate generator time constant) */
328
329 /* Write Register 13 (upper byte of baud rate generator time constant) */
330
331 /* Write Register 14 (Misc control bits) */
332 #define BRENABL 1 /* Baud rate generator enable */
333 #define BRSRC 2 /* Baud rate generator source */
334 #define DTRREQ 4 /* DTR/Request function */
335 #define AUTOECHO 8 /* Auto Echo */
336 #define LOOPBAK 0x10 /* Local loopback */
337 #define SEARCH 0x20 /* Enter search mode */
338 #define RMC 0x40 /* Reset missing clock */
339 #define DISDPLL 0x60 /* Disable DPLL */
340 #define SSBR 0x80 /* Set DPLL source = BR generator */
341 #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
342 #define SFMM 0xc0 /* Set FM mode */
343 #define SNRZI 0xe0 /* Set NRZI mode */
344
345 /* Write Register 15 (external/status interrupt control) */
346 #define ZCIE 2 /* Zero count IE */
347 #define DCDIE 8 /* DCD IE */
348 #define SYNCIE 0x10 /* Sync/hunt IE */
349 #define CTSIE 0x20 /* CTS IE */
350 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
351 #define BRKIE 0x80 /* Break/Abort IE */
352
353
354 /* Read Register 0 */
355 #define Rx_CH_AV 0x1 /* Rx Character Available */
356 #define ZCOUNT 0x2 /* Zero count */
357 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
358 #define DCD 0x8 /* DCD */
359 #define SYNC 0x10 /* Sync/hunt */
360 #define CTS 0x20 /* CTS */
361 #define TxEOM 0x40 /* Tx underrun */
362 #define BRK_ABRT 0x80 /* Break/Abort */
363
364 /* Read Register 1 */
365 #define ALL_SNT 0x1 /* All sent */
366 /* Residue Data for 8 Rx bits/char programmed */
367 #define RES3 0x8 /* 0/3 */
368 #define RES4 0x4 /* 0/4 */
369 #define RES5 0xc /* 0/5 */
370 #define RES6 0x2 /* 0/6 */
371 #define RES7 0xa /* 0/7 */
372 #define RES8 0x6 /* 0/8 */
373 #define RES18 0xe /* 1/8 */
374 #define RES28 0x0 /* 2/8 */
375 /* Special Rx Condition Interrupts */
376 #define PAR_ERR 0x10 /* Parity error */
377 #define Rx_OVR 0x20 /* Rx Overrun Error */
378 #define CRC_ERR 0x40 /* CRC/Framing Error */
379 #define END_FR 0x80 /* End of Frame (SDLC) */
380
381 /* Read Register 2 (channel b only) - Interrupt vector */
382
383 /* Read Register 3 (interrupt pending register) ch a only */
384 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
385 #define CHBTxIP 0x2 /* Channel B Tx IP */
386 #define CHBRxIP 0x4 /* Channel B Rx IP */
387 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
388 #define CHATxIP 0x10 /* Channel A Tx IP */
389 #define CHARxIP 0x20 /* Channel A Rx IP */
390
391 /* Read Register 8 (receive data register) */
392
393 /* Read Register 10 (misc status bits) */
394 #define ONLOOP 2 /* On loop */
395 #define LOOPSEND 0x10 /* Loop sending */
396 #define CLK2MIS 0x40 /* Two clocks missing */
397 #define CLK1MIS 0x80 /* One clock missing */
398
399 /* Read Register 12 (lower byte of baud rate generator constant) */
400
401 /* Read Register 13 (upper byte of baud rate generator constant) */
402
403 /* Read Register 15 (value of WR 15) */
404
405 /* Misc inlines */
ZS_CLEARERR(struct sgi_zschannel * channel)406 static inline void ZS_CLEARERR(struct sgi_zschannel *channel)
407 {
408 volatile unsigned char junk;
409
410 udelay(2);
411 channel->control = ERR_RES;
412 junk = sgint->istat0;
413 }
414
ZS_CLEARFIFO(struct sgi_zschannel * channel)415 static inline void ZS_CLEARFIFO(struct sgi_zschannel *channel)
416 {
417 volatile unsigned char junk;
418
419 udelay(2);
420 junk = channel->data;
421 udelay(2);
422 junk = sgint->istat0;
423 junk = channel->data;
424 udelay(2);
425 junk = sgint->istat0;
426 junk = channel->data;
427 udelay(2);
428 junk = sgint->istat0;
429 }
430
431 #if 0
432
433 #define ZS_CLEARERR(channel) (channel->control = ERR_RES)
434 #define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \
435 garbage = channel->data; \
436 udelay(2); \
437 garbage = channel->data; \
438 udelay(2); \
439 garbage = channel->data; \
440 udelay(2); } while(0)
441
442 #endif
443
444 #endif /* !(_SGI_SERIAL_H) */
445