1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31 #ifndef __RADEON_DRV_H__ 32 #define __RADEON_DRV_H__ 33 34 #define GET_RING_HEAD(ring) readl( (volatile u32 *) (ring)->head ) 35 #define SET_RING_HEAD(ring,val) writel( (val), (volatile u32 *) (ring)->head ) 36 37 typedef struct drm_radeon_freelist { 38 unsigned int age; 39 drm_buf_t *buf; 40 struct drm_radeon_freelist *next; 41 struct drm_radeon_freelist *prev; 42 } drm_radeon_freelist_t; 43 44 typedef struct drm_radeon_ring_buffer { 45 u32 *start; 46 u32 *end; 47 int size; 48 int size_l2qw; 49 50 volatile u32 *head; 51 u32 tail; 52 u32 tail_mask; 53 int space; 54 55 int high_mark; 56 } drm_radeon_ring_buffer_t; 57 58 typedef struct drm_radeon_depth_clear_t { 59 u32 rb3d_cntl; 60 u32 rb3d_zstencilcntl; 61 u32 se_cntl; 62 } drm_radeon_depth_clear_t; 63 64 65 struct mem_block { 66 struct mem_block *next; 67 struct mem_block *prev; 68 int start; 69 int size; 70 int pid; /* 0: free, -1: heap, other: real pids */ 71 }; 72 73 typedef struct drm_radeon_private { 74 drm_radeon_ring_buffer_t ring; 75 drm_radeon_sarea_t *sarea_priv; 76 77 int agp_size; 78 u32 agp_vm_start; 79 unsigned long agp_buffers_offset; 80 81 int cp_mode; 82 int cp_running; 83 84 drm_radeon_freelist_t *head; 85 drm_radeon_freelist_t *tail; 86 int last_buf; 87 volatile u32 *scratch; 88 int writeback_works; 89 90 int usec_timeout; 91 92 int is_r200; 93 94 int is_pci; 95 unsigned long phys_pci_gart; 96 dma_addr_t bus_pci_gart; 97 98 struct { 99 u32 boxes; 100 int freelist_timeouts; 101 int freelist_loops; 102 int requested_bufs; 103 int last_frame_reads; 104 int last_clear_reads; 105 int clears; 106 int texture_uploads; 107 } stats; 108 109 int do_boxes; 110 int page_flipping; 111 int current_page; 112 113 u32 color_fmt; 114 unsigned int front_offset; 115 unsigned int front_pitch; 116 unsigned int back_offset; 117 unsigned int back_pitch; 118 119 u32 depth_fmt; 120 unsigned int depth_offset; 121 unsigned int depth_pitch; 122 123 u32 front_pitch_offset; 124 u32 back_pitch_offset; 125 u32 depth_pitch_offset; 126 127 drm_radeon_depth_clear_t depth_clear; 128 129 drm_map_t *sarea; 130 drm_map_t *fb; 131 drm_map_t *mmio; 132 drm_map_t *cp_ring; 133 drm_map_t *ring_rptr; 134 drm_map_t *buffers; 135 drm_map_t *agp_textures; 136 137 struct mem_block *agp_heap; 138 struct mem_block *fb_heap; 139 140 /* SW interrupt */ 141 wait_queue_head_t swi_queue; 142 atomic_t swi_emitted; 143 144 } drm_radeon_private_t; 145 146 typedef struct drm_radeon_buf_priv { 147 u32 age; 148 } drm_radeon_buf_priv_t; 149 150 /* radeon_cp.c */ 151 extern int radeon_cp_init( struct inode *inode, struct file *filp, 152 unsigned int cmd, unsigned long arg ); 153 extern int radeon_cp_start( struct inode *inode, struct file *filp, 154 unsigned int cmd, unsigned long arg ); 155 extern int radeon_cp_stop( struct inode *inode, struct file *filp, 156 unsigned int cmd, unsigned long arg ); 157 extern int radeon_cp_reset( struct inode *inode, struct file *filp, 158 unsigned int cmd, unsigned long arg ); 159 extern int radeon_cp_idle( struct inode *inode, struct file *filp, 160 unsigned int cmd, unsigned long arg ); 161 extern int radeon_engine_reset( struct inode *inode, struct file *filp, 162 unsigned int cmd, unsigned long arg ); 163 extern int radeon_fullscreen( struct inode *inode, struct file *filp, 164 unsigned int cmd, unsigned long arg ); 165 extern int radeon_cp_buffers( struct inode *inode, struct file *filp, 166 unsigned int cmd, unsigned long arg ); 167 168 extern void radeon_freelist_reset( drm_device_t *dev ); 169 extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); 170 171 extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); 172 173 extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ); 174 extern int radeon_do_cleanup_cp( drm_device_t *dev ); 175 extern int radeon_do_cleanup_pageflip( drm_device_t *dev ); 176 177 /* radeon_state.c */ 178 extern int radeon_cp_clear( struct inode *inode, struct file *filp, 179 unsigned int cmd, unsigned long arg ); 180 extern int radeon_cp_swap( struct inode *inode, struct file *filp, 181 unsigned int cmd, unsigned long arg ); 182 extern int radeon_cp_vertex( struct inode *inode, struct file *filp, 183 unsigned int cmd, unsigned long arg ); 184 extern int radeon_cp_indices( struct inode *inode, struct file *filp, 185 unsigned int cmd, unsigned long arg ); 186 extern int radeon_cp_texture( struct inode *inode, struct file *filp, 187 unsigned int cmd, unsigned long arg ); 188 extern int radeon_cp_stipple( struct inode *inode, struct file *filp, 189 unsigned int cmd, unsigned long arg ); 190 extern int radeon_cp_indirect( struct inode *inode, struct file *filp, 191 unsigned int cmd, unsigned long arg ); 192 extern int radeon_cp_vertex2(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); 193 extern int radeon_cp_cmdbuf(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); 194 extern int radeon_cp_getparam(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); 195 extern int radeon_cp_flip(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); 196 197 extern int radeon_mem_alloc(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); 198 extern int radeon_mem_free(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); 199 extern int radeon_mem_init_heap(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); 200 extern void radeon_mem_takedown( struct mem_block **heap ); 201 extern void radeon_mem_release( struct mem_block *heap ); 202 203 /* radeon_irq.c */ 204 extern int radeon_irq_emit(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); 205 extern int radeon_irq_wait(struct inode *inode, struct file *filp,unsigned int cmd, unsigned long arg ); 206 207 extern int radeon_emit_and_wait_irq(drm_device_t *dev); 208 extern int radeon_wait_irq(drm_device_t *dev, int swi_nr); 209 extern int radeon_emit_irq(drm_device_t *dev); 210 211 212 /* Flags for stats.boxes 213 */ 214 #define RADEON_BOX_DMA_IDLE 0x1 215 #define RADEON_BOX_RING_FULL 0x2 216 #define RADEON_BOX_FLIP 0x4 217 #define RADEON_BOX_WAIT_IDLE 0x8 218 #define RADEON_BOX_TEXTURE_LOAD 0x10 219 220 221 222 /* Register definitions, register access macros and drmAddMap constants 223 * for Radeon kernel driver. 224 */ 225 226 #define RADEON_AGP_COMMAND 0x0f60 227 #define RADEON_AUX_SCISSOR_CNTL 0x26f0 228 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 229 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 230 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 231 # define RADEON_SCISSOR_0_ENABLE (1 << 28) 232 # define RADEON_SCISSOR_1_ENABLE (1 << 29) 233 # define RADEON_SCISSOR_2_ENABLE (1 << 30) 234 235 #define RADEON_BUS_CNTL 0x0030 236 # define RADEON_BUS_MASTER_DIS (1 << 6) 237 238 #define RADEON_CLOCK_CNTL_DATA 0x000c 239 # define RADEON_PLL_WR_EN (1 << 7) 240 #define RADEON_CLOCK_CNTL_INDEX 0x0008 241 #define RADEON_CONFIG_APER_SIZE 0x0108 242 #define RADEON_CRTC_OFFSET 0x0224 243 #define RADEON_CRTC_OFFSET_CNTL 0x0228 244 # define RADEON_CRTC_TILE_EN (1 << 15) 245 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 246 #define RADEON_CRTC2_OFFSET 0x0324 247 #define RADEON_CRTC2_OFFSET_CNTL 0x0328 248 249 #define RADEON_RB3D_COLORPITCH 0x1c48 250 251 #define RADEON_DP_GUI_MASTER_CNTL 0x146c 252 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 253 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 254 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 255 # define RADEON_GMC_BRUSH_NONE (15 << 4) 256 # define RADEON_GMC_DST_16BPP (4 << 8) 257 # define RADEON_GMC_DST_24BPP (5 << 8) 258 # define RADEON_GMC_DST_32BPP (6 << 8) 259 # define RADEON_GMC_DST_DATATYPE_SHIFT 8 260 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 261 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 262 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 263 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 264 # define RADEON_GMC_WR_MSK_DIS (1 << 30) 265 # define RADEON_ROP3_S 0x00cc0000 266 # define RADEON_ROP3_P 0x00f00000 267 #define RADEON_DP_WRITE_MASK 0x16cc 268 #define RADEON_DST_PITCH_OFFSET 0x142c 269 #define RADEON_DST_PITCH_OFFSET_C 0x1c80 270 # define RADEON_DST_TILE_LINEAR (0 << 30) 271 # define RADEON_DST_TILE_MACRO (1 << 30) 272 # define RADEON_DST_TILE_MICRO (2 << 30) 273 # define RADEON_DST_TILE_BOTH (3 << 30) 274 275 #define RADEON_SCRATCH_REG0 0x15e0 276 #define RADEON_SCRATCH_REG1 0x15e4 277 #define RADEON_SCRATCH_REG2 0x15e8 278 #define RADEON_SCRATCH_REG3 0x15ec 279 #define RADEON_SCRATCH_REG4 0x15f0 280 #define RADEON_SCRATCH_REG5 0x15f4 281 #define RADEON_SCRATCH_UMSK 0x0770 282 #define RADEON_SCRATCH_ADDR 0x0774 283 284 #define GET_SCRATCH( x ) (dev_priv->writeback_works \ 285 ? readl( &dev_priv->scratch[(x)] ) \ 286 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 287 288 289 #define RADEON_GEN_INT_CNTL 0x0040 290 # define RADEON_CRTC_VBLANK_MASK (1 << 0) 291 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 292 # define RADEON_SW_INT_ENABLE (1 << 25) 293 294 #define RADEON_GEN_INT_STATUS 0x0044 295 # define RADEON_CRTC_VBLANK_STAT (1 << 0) 296 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 297 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 298 # define RADEON_SW_INT_TEST (1 << 25) 299 # define RADEON_SW_INT_TEST_ACK (1 << 25) 300 # define RADEON_SW_INT_FIRE (1 << 26) 301 302 #define RADEON_HOST_PATH_CNTL 0x0130 303 # define RADEON_HDP_SOFT_RESET (1 << 26) 304 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 305 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 306 307 #define RADEON_ISYNC_CNTL 0x1724 308 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 309 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 310 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 311 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 312 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 313 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 314 315 #define RADEON_RBBM_GUICNTL 0x172c 316 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 317 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 318 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 319 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 320 321 #define RADEON_MC_AGP_LOCATION 0x014c 322 #define RADEON_MC_FB_LOCATION 0x0148 323 #define RADEON_MCLK_CNTL 0x0012 324 # define RADEON_FORCEON_MCLKA (1 << 16) 325 # define RADEON_FORCEON_MCLKB (1 << 17) 326 # define RADEON_FORCEON_YCLKA (1 << 18) 327 # define RADEON_FORCEON_YCLKB (1 << 19) 328 # define RADEON_FORCEON_MC (1 << 20) 329 # define RADEON_FORCEON_AIC (1 << 21) 330 331 #define RADEON_PP_BORDER_COLOR_0 0x1d40 332 #define RADEON_PP_BORDER_COLOR_1 0x1d44 333 #define RADEON_PP_BORDER_COLOR_2 0x1d48 334 #define RADEON_PP_CNTL 0x1c38 335 # define RADEON_SCISSOR_ENABLE (1 << 1) 336 #define RADEON_PP_LUM_MATRIX 0x1d00 337 #define RADEON_PP_MISC 0x1c14 338 #define RADEON_PP_ROT_MATRIX_0 0x1d58 339 #define RADEON_PP_TXFILTER_0 0x1c54 340 #define RADEON_PP_TXFILTER_1 0x1c6c 341 #define RADEON_PP_TXFILTER_2 0x1c84 342 343 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 344 # define RADEON_RB2D_DC_FLUSH (3 << 0) 345 # define RADEON_RB2D_DC_FREE (3 << 2) 346 # define RADEON_RB2D_DC_FLUSH_ALL 0xf 347 # define RADEON_RB2D_DC_BUSY (1 << 31) 348 #define RADEON_RB3D_CNTL 0x1c3c 349 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 350 # define RADEON_PLANE_MASK_ENABLE (1 << 1) 351 # define RADEON_DITHER_ENABLE (1 << 2) 352 # define RADEON_ROUND_ENABLE (1 << 3) 353 # define RADEON_SCALE_DITHER_ENABLE (1 << 4) 354 # define RADEON_DITHER_INIT (1 << 5) 355 # define RADEON_ROP_ENABLE (1 << 6) 356 # define RADEON_STENCIL_ENABLE (1 << 7) 357 # define RADEON_Z_ENABLE (1 << 8) 358 #define RADEON_RB3D_DEPTHOFFSET 0x1c24 359 #define RADEON_RB3D_DEPTHPITCH 0x1c28 360 #define RADEON_RB3D_PLANEMASK 0x1d84 361 #define RADEON_RB3D_STENCILREFMASK 0x1d7c 362 #define RADEON_RB3D_ZCACHE_MODE 0x3250 363 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 364 # define RADEON_RB3D_ZC_FLUSH (1 << 0) 365 # define RADEON_RB3D_ZC_FREE (1 << 2) 366 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 367 # define RADEON_RB3D_ZC_BUSY (1 << 31) 368 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 369 # define RADEON_Z_TEST_MASK (7 << 4) 370 # define RADEON_Z_TEST_ALWAYS (7 << 4) 371 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 372 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 373 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 374 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 375 # define RADEON_Z_WRITE_ENABLE (1 << 30) 376 #define RADEON_RBBM_SOFT_RESET 0x00f0 377 # define RADEON_SOFT_RESET_CP (1 << 0) 378 # define RADEON_SOFT_RESET_HI (1 << 1) 379 # define RADEON_SOFT_RESET_SE (1 << 2) 380 # define RADEON_SOFT_RESET_RE (1 << 3) 381 # define RADEON_SOFT_RESET_PP (1 << 4) 382 # define RADEON_SOFT_RESET_E2 (1 << 5) 383 # define RADEON_SOFT_RESET_RB (1 << 6) 384 # define RADEON_SOFT_RESET_HDP (1 << 7) 385 #define RADEON_RBBM_STATUS 0x0e40 386 # define RADEON_RBBM_FIFOCNT_MASK 0x007f 387 # define RADEON_RBBM_ACTIVE (1 << 31) 388 #define RADEON_RE_LINE_PATTERN 0x1cd0 389 #define RADEON_RE_MISC 0x26c4 390 #define RADEON_RE_TOP_LEFT 0x26c0 391 #define RADEON_RE_WIDTH_HEIGHT 0x1c44 392 #define RADEON_RE_STIPPLE_ADDR 0x1cc8 393 #define RADEON_RE_STIPPLE_DATA 0x1ccc 394 395 #define RADEON_SCISSOR_TL_0 0x1cd8 396 #define RADEON_SCISSOR_BR_0 0x1cdc 397 #define RADEON_SCISSOR_TL_1 0x1ce0 398 #define RADEON_SCISSOR_BR_1 0x1ce4 399 #define RADEON_SCISSOR_TL_2 0x1ce8 400 #define RADEON_SCISSOR_BR_2 0x1cec 401 #define RADEON_SE_COORD_FMT 0x1c50 402 #define RADEON_SE_CNTL 0x1c4c 403 # define RADEON_FFACE_CULL_CW (0 << 0) 404 # define RADEON_BFACE_SOLID (3 << 1) 405 # define RADEON_FFACE_SOLID (3 << 3) 406 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 407 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 408 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 409 # define RADEON_ALPHA_SHADE_FLAT (1 << 10) 410 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 411 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 412 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 413 # define RADEON_FOG_SHADE_FLAT (1 << 14) 414 # define RADEON_FOG_SHADE_GOURAUD (2 << 14) 415 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 416 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 417 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 418 # define RADEON_ROUND_MODE_TRUNC (0 << 28) 419 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 420 #define RADEON_SE_CNTL_STATUS 0x2140 421 #define RADEON_SE_LINE_WIDTH 0x1db8 422 #define RADEON_SE_VPORT_XSCALE 0x1d98 423 #define RADEON_SE_ZBIAS_FACTOR 0x1db0 424 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 425 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 426 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 427 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 428 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 429 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 430 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 431 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 432 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 433 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 434 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc 435 #define RADEON_SURFACE_CNTL 0x0b00 436 # define RADEON_SURF_TRANSLATION_DIS (1 << 8) 437 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 438 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 439 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 440 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 441 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 442 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 443 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 444 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 445 #define RADEON_SURFACE0_INFO 0x0b0c 446 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 447 # define RADEON_SURF_TILE_MODE_MASK (3 << 16) 448 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 449 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 450 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 451 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 452 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 453 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 454 #define RADEON_SURFACE1_INFO 0x0b1c 455 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 456 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 457 #define RADEON_SURFACE2_INFO 0x0b2c 458 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 459 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 460 #define RADEON_SURFACE3_INFO 0x0b3c 461 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 462 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 463 #define RADEON_SURFACE4_INFO 0x0b4c 464 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 465 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 466 #define RADEON_SURFACE5_INFO 0x0b5c 467 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 468 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 469 #define RADEON_SURFACE6_INFO 0x0b6c 470 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 471 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 472 #define RADEON_SURFACE7_INFO 0x0b7c 473 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 474 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 475 #define RADEON_SW_SEMAPHORE 0x013c 476 477 #define RADEON_WAIT_UNTIL 0x1720 478 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) 479 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 480 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 481 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 482 483 #define RADEON_RB3D_ZMASKOFFSET 0x1c34 484 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 485 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 486 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 487 488 489 /* CP registers */ 490 #define RADEON_CP_ME_RAM_ADDR 0x07d4 491 #define RADEON_CP_ME_RAM_RADDR 0x07d8 492 #define RADEON_CP_ME_RAM_DATAH 0x07dc 493 #define RADEON_CP_ME_RAM_DATAL 0x07e0 494 495 #define RADEON_CP_RB_BASE 0x0700 496 #define RADEON_CP_RB_CNTL 0x0704 497 # define RADEON_BUF_SWAP_32BIT (2 << 16) 498 #define RADEON_CP_RB_RPTR_ADDR 0x070c 499 #define RADEON_CP_RB_RPTR 0x0710 500 #define RADEON_CP_RB_WPTR 0x0714 501 502 #define RADEON_CP_RB_WPTR_DELAY 0x0718 503 # define RADEON_PRE_WRITE_TIMER_SHIFT 0 504 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 505 506 #define RADEON_CP_IB_BASE 0x0738 507 508 #define RADEON_CP_CSQ_CNTL 0x0740 509 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 510 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 511 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 512 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 513 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 514 # define RADEON_CSQ_PRIBM_INDBM (4 << 28) 515 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 516 517 #define RADEON_AIC_CNTL 0x01d0 518 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 519 #define RADEON_AIC_STAT 0x01d4 520 #define RADEON_AIC_PT_BASE 0x01d8 521 #define RADEON_AIC_LO_ADDR 0x01dc 522 #define RADEON_AIC_HI_ADDR 0x01e0 523 #define RADEON_AIC_TLB_ADDR 0x01e4 524 #define RADEON_AIC_TLB_DATA 0x01e8 525 526 /* CP command packets */ 527 #define RADEON_CP_PACKET0 0x00000000 528 # define RADEON_ONE_REG_WR (1 << 15) 529 #define RADEON_CP_PACKET1 0x40000000 530 #define RADEON_CP_PACKET2 0x80000000 531 #define RADEON_CP_PACKET3 0xC0000000 532 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 533 # define RADEON_WAIT_FOR_IDLE 0x00002600 534 # define RADEON_3D_DRAW_VBUF 0x00002800 535 # define RADEON_3D_DRAW_IMMD 0x00002900 536 # define RADEON_3D_DRAW_INDX 0x00002A00 537 # define RADEON_3D_LOAD_VBPNTR 0x00002F00 538 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 539 # define RADEON_CNTL_PAINT_MULTI 0x00009A00 540 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 541 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00 542 543 #define RADEON_CP_PACKET_MASK 0xC0000000 544 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 545 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff 546 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 547 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 548 549 #define RADEON_VTX_Z_PRESENT (1 << 31) 550 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 551 552 #define RADEON_PRIM_TYPE_NONE (0 << 0) 553 #define RADEON_PRIM_TYPE_POINT (1 << 0) 554 #define RADEON_PRIM_TYPE_LINE (2 << 0) 555 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 556 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 557 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 558 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 559 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 560 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 561 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 562 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 563 #define RADEON_PRIM_TYPE_MASK 0xf 564 #define RADEON_PRIM_WALK_IND (1 << 4) 565 #define RADEON_PRIM_WALK_LIST (2 << 4) 566 #define RADEON_PRIM_WALK_RING (3 << 4) 567 #define RADEON_COLOR_ORDER_BGRA (0 << 6) 568 #define RADEON_COLOR_ORDER_RGBA (1 << 6) 569 #define RADEON_MAOS_ENABLE (1 << 7) 570 #define RADEON_VTX_FMT_R128_MODE (0 << 8) 571 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 572 #define RADEON_NUM_VERTICES_SHIFT 16 573 574 #define RADEON_COLOR_FORMAT_CI8 2 575 #define RADEON_COLOR_FORMAT_ARGB1555 3 576 #define RADEON_COLOR_FORMAT_RGB565 4 577 #define RADEON_COLOR_FORMAT_ARGB8888 6 578 #define RADEON_COLOR_FORMAT_RGB332 7 579 #define RADEON_COLOR_FORMAT_RGB8 9 580 #define RADEON_COLOR_FORMAT_ARGB4444 15 581 582 #define RADEON_TXFORMAT_I8 0 583 #define RADEON_TXFORMAT_AI88 1 584 #define RADEON_TXFORMAT_RGB332 2 585 #define RADEON_TXFORMAT_ARGB1555 3 586 #define RADEON_TXFORMAT_RGB565 4 587 #define RADEON_TXFORMAT_ARGB4444 5 588 #define RADEON_TXFORMAT_ARGB8888 6 589 #define RADEON_TXFORMAT_RGBA8888 7 590 #define RADEON_TXFORMAT_VYUY422 10 591 #define RADEON_TXFORMAT_YVYU422 11 592 #define RADEON_TXFORMAT_DXT1 12 593 #define RADEON_TXFORMAT_DXT23 14 594 #define RADEON_TXFORMAT_DXT45 15 595 596 #define R200_PP_TXCBLEND_0 0x2f00 597 #define R200_PP_TXCBLEND_1 0x2f10 598 #define R200_PP_TXCBLEND_2 0x2f20 599 #define R200_PP_TXCBLEND_3 0x2f30 600 #define R200_PP_TXCBLEND_4 0x2f40 601 #define R200_PP_TXCBLEND_5 0x2f50 602 #define R200_PP_TXCBLEND_6 0x2f60 603 #define R200_PP_TXCBLEND_7 0x2f70 604 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 605 #define R200_PP_TFACTOR_0 0x2ee0 606 #define R200_SE_VTX_FMT_0 0x2088 607 #define R200_SE_VAP_CNTL 0x2080 608 #define R200_SE_TCL_MATRIX_SEL_0 0x2230 609 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 610 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 611 #define R200_PP_TXFILTER_5 0x2ca0 612 #define R200_PP_TXFILTER_4 0x2c80 613 #define R200_PP_TXFILTER_3 0x2c60 614 #define R200_PP_TXFILTER_2 0x2c40 615 #define R200_PP_TXFILTER_1 0x2c20 616 #define R200_PP_TXFILTER_0 0x2c00 617 #define R200_PP_TXOFFSET_5 0x2d78 618 #define R200_PP_TXOFFSET_4 0x2d60 619 #define R200_PP_TXOFFSET_3 0x2d48 620 #define R200_PP_TXOFFSET_2 0x2d30 621 #define R200_PP_TXOFFSET_1 0x2d18 622 #define R200_PP_TXOFFSET_0 0x2d00 623 624 #define R200_PP_CUBIC_FACES_0 0x2c18 625 #define R200_PP_CUBIC_FACES_1 0x2c38 626 #define R200_PP_CUBIC_FACES_2 0x2c58 627 #define R200_PP_CUBIC_FACES_3 0x2c78 628 #define R200_PP_CUBIC_FACES_4 0x2c98 629 #define R200_PP_CUBIC_FACES_5 0x2cb8 630 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 631 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 632 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 633 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 634 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 635 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 636 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 637 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 638 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 639 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 640 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 641 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 642 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 643 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 644 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 645 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 646 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 647 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 648 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 649 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 650 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 651 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 652 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 653 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 654 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 655 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 656 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 657 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 658 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 659 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 660 661 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 662 #define R200_SE_VTE_CNTL 0x20b0 663 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 664 #define R200_PP_TAM_DEBUG3 0x2d9c 665 #define R200_PP_CNTL_X 0x2cc4 666 #define R200_SE_VAP_CNTL_STATUS 0x2140 667 #define R200_RE_SCISSOR_TL_0 0x1cd8 668 #define R200_RE_SCISSOR_TL_1 0x1ce0 669 #define R200_RE_SCISSOR_TL_2 0x1ce8 670 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60 671 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 672 #define R200_SE_VTX_STATE_CNTL 0x2180 673 #define R200_RE_POINTSIZE 0x2648 674 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 675 676 677 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 678 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 679 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 680 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 681 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 682 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 683 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 684 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 685 #define R200_3D_DRAW_IMMD_2 0xC0003500 686 #define R200_SE_VTX_FMT_1 0x208c 687 #define R200_RE_CNTL 0x1c50 688 689 690 /* Constants */ 691 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 692 693 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 694 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 695 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 696 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 697 #define RADEON_LAST_DISPATCH 1 698 699 #define RADEON_MAX_VB_AGE 0x7fffffff 700 #define RADEON_MAX_VB_VERTS (0xffff) 701 702 #define RADEON_RING_HIGH_MARK 128 703 704 705 #define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) 706 #define RADEON_ADDR(reg) (RADEON_BASE( reg ) + reg) 707 708 #define RADEON_READ(reg) readl( (volatile u32 *) RADEON_ADDR(reg) ) 709 #define RADEON_WRITE(reg,val) writel( (val), (volatile u32 *) RADEON_ADDR(reg)) 710 711 #define RADEON_READ8(reg) readb( (volatile u8 *) RADEON_ADDR(reg) ) 712 #define RADEON_WRITE8(reg,val) writeb( (val), (volatile u8 *) RADEON_ADDR(reg)) 713 714 #define RADEON_WRITE_PLL( addr, val ) \ 715 do { \ 716 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 717 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 718 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 719 } while (0) 720 721 extern int RADEON_READ_PLL( drm_device_t *dev, int addr ); 722 723 724 #define CP_PACKET0( reg, n ) \ 725 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 726 #define CP_PACKET0_TABLE( reg, n ) \ 727 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 728 #define CP_PACKET1( reg0, reg1 ) \ 729 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 730 #define CP_PACKET2() \ 731 (RADEON_CP_PACKET2) 732 #define CP_PACKET3( pkt, n ) \ 733 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 734 735 736 /* ================================================================ 737 * Engine control helper macros 738 */ 739 740 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 741 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 742 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 743 RADEON_WAIT_HOST_IDLECLEAN) ); \ 744 } while (0) 745 746 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 747 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 748 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 749 RADEON_WAIT_HOST_IDLECLEAN) ); \ 750 } while (0) 751 752 #define RADEON_WAIT_UNTIL_IDLE() do { \ 753 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 754 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 755 RADEON_WAIT_3D_IDLECLEAN | \ 756 RADEON_WAIT_HOST_IDLECLEAN) ); \ 757 } while (0) 758 759 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 760 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 761 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 762 } while (0) 763 764 #define RADEON_FLUSH_CACHE() do { \ 765 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 766 OUT_RING( RADEON_RB2D_DC_FLUSH ); \ 767 } while (0) 768 769 #define RADEON_PURGE_CACHE() do { \ 770 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 771 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ 772 } while (0) 773 774 #define RADEON_FLUSH_ZCACHE() do { \ 775 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 776 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 777 } while (0) 778 779 #define RADEON_PURGE_ZCACHE() do { \ 780 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 781 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 782 } while (0) 783 784 785 /* ================================================================ 786 * Misc helper macros 787 */ 788 789 #define LOCK_TEST_WITH_RETURN( dev ) \ 790 do { \ 791 if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \ 792 dev->lock.pid != current->pid ) { \ 793 DRM_ERROR( "%s called without lock held\n", \ 794 __FUNCTION__ ); \ 795 return -EINVAL; \ 796 } \ 797 } while (0) 798 799 800 /* Perfbox functionality only. 801 */ 802 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 803 do { \ 804 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 805 u32 head = GET_RING_HEAD(&dev_priv->ring); \ 806 if (head == dev_priv->ring.tail) \ 807 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 808 } \ 809 } while (0) 810 811 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 812 do { \ 813 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 814 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 815 int __ret = radeon_do_cp_idle( dev_priv ); \ 816 if ( __ret ) return __ret; \ 817 sarea_priv->last_dispatch = 0; \ 818 radeon_freelist_reset( dev ); \ 819 } \ 820 } while (0) 821 822 #define RADEON_DISPATCH_AGE( age ) do { \ 823 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 824 OUT_RING( age ); \ 825 } while (0) 826 827 #define RADEON_FRAME_AGE( age ) do { \ 828 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 829 OUT_RING( age ); \ 830 } while (0) 831 832 #define RADEON_CLEAR_AGE( age ) do { \ 833 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 834 OUT_RING( age ); \ 835 } while (0) 836 837 838 /* ================================================================ 839 * Ring control 840 */ 841 842 #define RADEON_VERBOSE 0 843 844 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; 845 846 #define BEGIN_RING( n ) do { \ 847 if ( RADEON_VERBOSE ) { \ 848 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ 849 n, __FUNCTION__ ); \ 850 } \ 851 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 852 COMMIT_RING(); \ 853 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 854 } \ 855 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 856 ring = dev_priv->ring.start; \ 857 write = dev_priv->ring.tail; \ 858 mask = dev_priv->ring.tail_mask; \ 859 } while (0) 860 861 #define ADVANCE_RING() do { \ 862 if ( RADEON_VERBOSE ) { \ 863 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 864 write, dev_priv->ring.tail ); \ 865 } \ 866 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 867 DRM_ERROR( \ 868 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 869 ((dev_priv->ring.tail + _nr) & mask), \ 870 write, __LINE__); \ 871 } else \ 872 dev_priv->ring.tail = write; \ 873 } while (0) 874 875 #define COMMIT_RING() do { \ 876 /* Flush writes to ring */ \ 877 rmb(); \ 878 GET_RING_HEAD( &dev_priv->ring ); \ 879 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ 880 /* read from PCI bus to ensure correct posting */ \ 881 RADEON_READ( RADEON_CP_RB_RPTR ); \ 882 } while (0) 883 884 #define OUT_RING( x ) do { \ 885 if ( RADEON_VERBOSE ) { \ 886 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 887 (unsigned int)(x), write ); \ 888 } \ 889 ring[write++] = (x); \ 890 write &= mask; \ 891 } while (0) 892 893 #define OUT_RING_REG( reg, val ) do { \ 894 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 895 OUT_RING( val ); \ 896 } while (0) 897 898 899 #define OUT_RING_USER_TABLE( tab, sz ) do { \ 900 int _size = (sz); \ 901 int *_tab = (tab); \ 902 \ 903 if (write + _size > mask) { \ 904 int i = (mask+1) - write; \ 905 if (__copy_from_user( (int *)(ring+write), \ 906 _tab, i*4 )) \ 907 return -EFAULT; \ 908 write = 0; \ 909 _size -= i; \ 910 _tab += i; \ 911 } \ 912 \ 913 if (_size && __copy_from_user( (int *)(ring+write), \ 914 _tab, _size*4 )) \ 915 return -EFAULT; \ 916 \ 917 write += _size; \ 918 write &= mask; \ 919 } while (0) 920 921 922 #endif /* __RADEON_DRV_H__ */ 923