1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Rickard E. (Rik) Faith <faith@valinux.com> 28 * Kevin E. Martin <martin@valinux.com> 29 * Gareth Hughes <gareth@valinux.com> 30 * 31 */ 32 33 #ifndef __RADEON_DRV_H__ 34 #define __RADEON_DRV_H__ 35 36 typedef struct drm_radeon_freelist { 37 unsigned int age; 38 drm_buf_t *buf; 39 struct drm_radeon_freelist *next; 40 struct drm_radeon_freelist *prev; 41 } drm_radeon_freelist_t; 42 43 typedef struct drm_radeon_ring_buffer { 44 u32 *start; 45 u32 *end; 46 int size; 47 int size_l2qw; 48 49 volatile u32 *head; 50 u32 tail; 51 u32 tail_mask; 52 int space; 53 } drm_radeon_ring_buffer_t; 54 55 typedef struct drm_radeon_depth_clear_t { 56 u32 rb3d_cntl; 57 u32 rb3d_zstencilcntl; 58 u32 se_cntl; 59 } drm_radeon_depth_clear_t; 60 61 typedef struct drm_radeon_private { 62 drm_radeon_ring_buffer_t ring; 63 drm_radeon_sarea_t *sarea_priv; 64 65 int agp_size; 66 u32 agp_vm_start; 67 u32 agp_buffers_offset; 68 69 int cp_mode; 70 int cp_running; 71 72 drm_radeon_freelist_t *head; 73 drm_radeon_freelist_t *tail; 74 /* FIXME: ROTATE_BUFS is a hask to cycle through bufs until freelist 75 code is used. Note this hides a problem with the scratch register 76 (used to keep track of last buffer completed) being written to before 77 the last buffer has actually completed rendering. */ 78 #define ROTATE_BUFS 1 79 #if ROTATE_BUFS 80 int last_buf; 81 #endif 82 volatile u32 *scratch; 83 84 int usec_timeout; 85 int is_pci; 86 87 atomic_t idle_count; 88 89 int page_flipping; 90 int current_page; 91 u32 crtc_offset; 92 u32 crtc_offset_cntl; 93 94 unsigned int color_fmt; 95 unsigned int front_offset; 96 unsigned int front_pitch; 97 unsigned int back_offset; 98 unsigned int back_pitch; 99 100 unsigned int depth_fmt; 101 unsigned int depth_offset; 102 unsigned int depth_pitch; 103 104 u32 front_pitch_offset; 105 u32 back_pitch_offset; 106 u32 depth_pitch_offset; 107 108 drm_radeon_depth_clear_t depth_clear; 109 110 drm_map_t *sarea; 111 drm_map_t *fb; 112 drm_map_t *mmio; 113 drm_map_t *cp_ring; 114 drm_map_t *ring_rptr; 115 drm_map_t *buffers; 116 drm_map_t *agp_textures; 117 } drm_radeon_private_t; 118 119 typedef struct drm_radeon_buf_priv { 120 u32 age; 121 int prim; 122 int discard; 123 int dispatched; 124 drm_radeon_freelist_t *list_entry; 125 } drm_radeon_buf_priv_t; 126 127 /* radeon_drv.c */ 128 extern int radeon_version( struct inode *inode, struct file *filp, 129 unsigned int cmd, unsigned long arg ); 130 extern int radeon_open( struct inode *inode, struct file *filp ); 131 extern int radeon_release( struct inode *inode, struct file *filp ); 132 extern int radeon_ioctl( struct inode *inode, struct file *filp, 133 unsigned int cmd, unsigned long arg ); 134 extern int radeon_lock( struct inode *inode, struct file *filp, 135 unsigned int cmd, unsigned long arg ); 136 extern int radeon_unlock( struct inode *inode, struct file *filp, 137 unsigned int cmd, unsigned long arg ); 138 139 /* radeon_cp.c */ 140 extern int radeon_cp_init( struct inode *inode, struct file *filp, 141 unsigned int cmd, unsigned long arg ); 142 extern int radeon_cp_start( struct inode *inode, struct file *filp, 143 unsigned int cmd, unsigned long arg ); 144 extern int radeon_cp_stop( struct inode *inode, struct file *filp, 145 unsigned int cmd, unsigned long arg ); 146 extern int radeon_cp_reset( struct inode *inode, struct file *filp, 147 unsigned int cmd, unsigned long arg ); 148 extern int radeon_cp_idle( struct inode *inode, struct file *filp, 149 unsigned int cmd, unsigned long arg ); 150 extern int radeon_engine_reset( struct inode *inode, struct file *filp, 151 unsigned int cmd, unsigned long arg ); 152 extern int radeon_fullscreen( struct inode *inode, struct file *filp, 153 unsigned int cmd, unsigned long arg ); 154 extern int radeon_cp_buffers( struct inode *inode, struct file *filp, 155 unsigned int cmd, unsigned long arg ); 156 157 extern void radeon_freelist_reset( drm_device_t *dev ); 158 extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); 159 160 extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); 161 extern void radeon_update_ring_snapshot( drm_radeon_private_t *dev_priv ); 162 163 extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ); 164 extern int radeon_do_cleanup_pageflip( drm_device_t *dev ); 165 166 /* radeon_state.c */ 167 extern int radeon_cp_clear( struct inode *inode, struct file *filp, 168 unsigned int cmd, unsigned long arg ); 169 extern int radeon_cp_swap( struct inode *inode, struct file *filp, 170 unsigned int cmd, unsigned long arg ); 171 extern int radeon_cp_vertex( struct inode *inode, struct file *filp, 172 unsigned int cmd, unsigned long arg ); 173 extern int radeon_cp_indices( struct inode *inode, struct file *filp, 174 unsigned int cmd, unsigned long arg ); 175 extern int radeon_cp_blit( struct inode *inode, struct file *filp, 176 unsigned int cmd, unsigned long arg ); 177 extern int radeon_cp_stipple( struct inode *inode, struct file *filp, 178 unsigned int cmd, unsigned long arg ); 179 extern int radeon_cp_indirect( struct inode *inode, struct file *filp, 180 unsigned int cmd, unsigned long arg ); 181 182 /* radeon_bufs.c */ 183 extern int radeon_addbufs(struct inode *inode, struct file *filp, 184 unsigned int cmd, unsigned long arg); 185 extern int radeon_mapbufs(struct inode *inode, struct file *filp, 186 unsigned int cmd, unsigned long arg); 187 188 /* radeon_context.c */ 189 extern int radeon_resctx(struct inode *inode, struct file *filp, 190 unsigned int cmd, unsigned long arg); 191 extern int radeon_addctx(struct inode *inode, struct file *filp, 192 unsigned int cmd, unsigned long arg); 193 extern int radeon_modctx(struct inode *inode, struct file *filp, 194 unsigned int cmd, unsigned long arg); 195 extern int radeon_getctx(struct inode *inode, struct file *filp, 196 unsigned int cmd, unsigned long arg); 197 extern int radeon_switchctx(struct inode *inode, struct file *filp, 198 unsigned int cmd, unsigned long arg); 199 extern int radeon_newctx(struct inode *inode, struct file *filp, 200 unsigned int cmd, unsigned long arg); 201 extern int radeon_rmctx(struct inode *inode, struct file *filp, 202 unsigned int cmd, unsigned long arg); 203 204 extern int radeon_context_switch(drm_device_t *dev, int old, int new); 205 extern int radeon_context_switch_complete(drm_device_t *dev, int new); 206 207 208 /* Register definitions, register access macros and drmAddMap constants 209 * for Radeon kernel driver. 210 */ 211 212 #define RADEON_AUX_SCISSOR_CNTL 0x26f0 213 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 214 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 215 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 216 # define RADEON_SCISSOR_0_ENABLE (1 << 28) 217 # define RADEON_SCISSOR_1_ENABLE (1 << 29) 218 # define RADEON_SCISSOR_2_ENABLE (1 << 30) 219 220 #define RADEON_BUS_CNTL 0x0030 221 # define RADEON_BUS_MASTER_DIS (1 << 6) 222 223 #define RADEON_CLOCK_CNTL_DATA 0x000c 224 # define RADEON_PLL_WR_EN (1 << 7) 225 #define RADEON_CLOCK_CNTL_INDEX 0x0008 226 #define RADEON_CONFIG_APER_SIZE 0x0108 227 #define RADEON_CRTC_OFFSET 0x0224 228 #define RADEON_CRTC_OFFSET_CNTL 0x0228 229 # define RADEON_CRTC_TILE_EN (1 << 15) 230 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 231 232 #define RADEON_RB3D_COLORPITCH 0x1c48 233 #define RADEON_RB3D_DEPTHCLEARVALUE 0x1c30 234 #define RADEON_RB3D_DEPTHXY_OFFSET 0x1c60 235 236 #define RADEON_DP_GUI_MASTER_CNTL 0x146c 237 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 238 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 239 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 240 # define RADEON_GMC_BRUSH_NONE (15 << 4) 241 # define RADEON_GMC_DST_16BPP (4 << 8) 242 # define RADEON_GMC_DST_24BPP (5 << 8) 243 # define RADEON_GMC_DST_32BPP (6 << 8) 244 # define RADEON_GMC_DST_DATATYPE_SHIFT 8 245 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 246 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 247 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 248 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 249 # define RADEON_GMC_WR_MSK_DIS (1 << 30) 250 # define RADEON_ROP3_S 0x00cc0000 251 # define RADEON_ROP3_P 0x00f00000 252 #define RADEON_DP_WRITE_MASK 0x16cc 253 #define RADEON_DST_PITCH_OFFSET 0x142c 254 #define RADEON_DST_PITCH_OFFSET_C 0x1c80 255 # define RADEON_DST_TILE_LINEAR (0 << 30) 256 # define RADEON_DST_TILE_MACRO (1 << 30) 257 # define RADEON_DST_TILE_MICRO (2 << 30) 258 # define RADEON_DST_TILE_BOTH (3 << 30) 259 260 #define RADEON_SCRATCH_REG0 0x15e0 261 #define RADEON_SCRATCH_REG1 0x15e4 262 #define RADEON_SCRATCH_REG2 0x15e8 263 #define RADEON_SCRATCH_REG3 0x15ec 264 #define RADEON_SCRATCH_REG4 0x15f0 265 #define RADEON_SCRATCH_REG5 0x15f4 266 #define RADEON_SCRATCH_UMSK 0x0770 267 #define RADEON_SCRATCH_ADDR 0x0774 268 269 #define RADEON_HOST_PATH_CNTL 0x0130 270 # define RADEON_HDP_SOFT_RESET (1 << 26) 271 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 272 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 273 274 #define RADEON_ISYNC_CNTL 0x1724 275 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 276 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 277 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 278 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 279 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 280 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 281 282 #define RADEON_MC_AGP_LOCATION 0x014c 283 #define RADEON_MC_FB_LOCATION 0x0148 284 #define RADEON_MCLK_CNTL 0x0012 285 286 #define RADEON_PP_BORDER_COLOR_0 0x1d40 287 #define RADEON_PP_BORDER_COLOR_1 0x1d44 288 #define RADEON_PP_BORDER_COLOR_2 0x1d48 289 #define RADEON_PP_CNTL 0x1c38 290 # define RADEON_SCISSOR_ENABLE (1 << 1) 291 #define RADEON_PP_LUM_MATRIX 0x1d00 292 #define RADEON_PP_MISC 0x1c14 293 #define RADEON_PP_ROT_MATRIX_0 0x1d58 294 #define RADEON_PP_TXFILTER_0 0x1c54 295 #define RADEON_PP_TXFILTER_1 0x1c6c 296 #define RADEON_PP_TXFILTER_2 0x1c84 297 298 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 299 # define RADEON_RB2D_DC_FLUSH (3 << 0) 300 # define RADEON_RB2D_DC_FREE (3 << 2) 301 # define RADEON_RB2D_DC_FLUSH_ALL 0xf 302 # define RADEON_RB2D_DC_BUSY (1 << 31) 303 #define RADEON_RB3D_CNTL 0x1c3c 304 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 305 # define RADEON_PLANE_MASK_ENABLE (1 << 1) 306 # define RADEON_DITHER_ENABLE (1 << 2) 307 # define RADEON_ROUND_ENABLE (1 << 3) 308 # define RADEON_SCALE_DITHER_ENABLE (1 << 4) 309 # define RADEON_DITHER_INIT (1 << 5) 310 # define RADEON_ROP_ENABLE (1 << 6) 311 # define RADEON_STENCIL_ENABLE (1 << 7) 312 # define RADEON_Z_ENABLE (1 << 8) 313 # define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) 314 # define RADEON_ZBLOCK8 (0 << 15) 315 # define RADEON_ZBLOCK16 (1 << 15) 316 #define RADEON_RB3D_DEPTHOFFSET 0x1c24 317 #define RADEON_RB3D_PLANEMASK 0x1d84 318 #define RADEON_RB3D_STENCILREFMASK 0x1d7c 319 #define RADEON_RB3D_ZCACHE_MODE 0x3250 320 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 321 # define RADEON_RB3D_ZC_FLUSH (1 << 0) 322 # define RADEON_RB3D_ZC_FREE (1 << 2) 323 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 324 # define RADEON_RB3D_ZC_BUSY (1 << 31) 325 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 326 # define RADEON_Z_TEST_MASK (7 << 4) 327 # define RADEON_Z_TEST_ALWAYS (7 << 4) 328 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 329 # define RADEON_STENCIL_S_FAIL_KEEP (0 << 16) 330 # define RADEON_STENCIL_ZPASS_KEEP (0 << 20) 331 # define RADEON_STENCIL_ZFAIL_KEEP (0 << 20) 332 # define RADEON_Z_WRITE_ENABLE (1 << 30) 333 #define RADEON_RBBM_SOFT_RESET 0x00f0 334 # define RADEON_SOFT_RESET_CP (1 << 0) 335 # define RADEON_SOFT_RESET_HI (1 << 1) 336 # define RADEON_SOFT_RESET_SE (1 << 2) 337 # define RADEON_SOFT_RESET_RE (1 << 3) 338 # define RADEON_SOFT_RESET_PP (1 << 4) 339 # define RADEON_SOFT_RESET_E2 (1 << 5) 340 # define RADEON_SOFT_RESET_RB (1 << 6) 341 # define RADEON_SOFT_RESET_HDP (1 << 7) 342 #define RADEON_RBBM_STATUS 0x0e40 343 # define RADEON_RBBM_FIFOCNT_MASK 0x007f 344 # define RADEON_RBBM_ACTIVE (1 << 31) 345 #define RADEON_RE_LINE_PATTERN 0x1cd0 346 #define RADEON_RE_MISC 0x26c4 347 #define RADEON_RE_TOP_LEFT 0x26c0 348 #define RADEON_RE_WIDTH_HEIGHT 0x1c44 349 #define RADEON_RE_STIPPLE_ADDR 0x1cc8 350 #define RADEON_RE_STIPPLE_DATA 0x1ccc 351 352 #define RADEON_SCISSOR_TL_0 0x1cd8 353 #define RADEON_SCISSOR_BR_0 0x1cdc 354 #define RADEON_SCISSOR_TL_1 0x1ce0 355 #define RADEON_SCISSOR_BR_1 0x1ce4 356 #define RADEON_SCISSOR_TL_2 0x1ce8 357 #define RADEON_SCISSOR_BR_2 0x1cec 358 #define RADEON_SE_COORD_FMT 0x1c50 359 #define RADEON_SE_CNTL 0x1c4c 360 # define RADEON_FFACE_CULL_CW (0 << 0) 361 # define RADEON_BFACE_SOLID (3 << 1) 362 # define RADEON_FFACE_SOLID (3 << 3) 363 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 364 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 365 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 366 # define RADEON_ALPHA_SHADE_FLAT (1 << 10) 367 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 368 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 369 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 370 # define RADEON_FOG_SHADE_FLAT (1 << 14) 371 # define RADEON_FOG_SHADE_GOURAUD (2 << 14) 372 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 373 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 374 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 375 # define RADEON_ROUND_MODE_TRUNC (0 << 28) 376 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 377 #define RADEON_SE_CNTL_STATUS 0x2140 378 #define RADEON_SE_LINE_WIDTH 0x1db8 379 #define RADEON_SE_VPORT_XSCALE 0x1d98 380 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 381 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc 382 #define RADEON_SURFACE_CNTL 0x0b00 383 # define RADEON_SURF_TRANSLATION_DIS (1 << 8) 384 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 385 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 386 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 387 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 388 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 389 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 390 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 391 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 392 #define RADEON_SURFACE0_INFO 0x0b0c 393 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 394 # define RADEON_SURF_TILE_MODE_MASK (3 << 16) 395 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 396 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 397 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 398 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 399 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 400 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 401 #define RADEON_SURFACE1_INFO 0x0b1c 402 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 403 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 404 #define RADEON_SURFACE2_INFO 0x0b2c 405 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 406 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 407 #define RADEON_SURFACE3_INFO 0x0b3c 408 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 409 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 410 #define RADEON_SURFACE4_INFO 0x0b4c 411 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 412 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 413 #define RADEON_SURFACE5_INFO 0x0b5c 414 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 415 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 416 #define RADEON_SURFACE6_INFO 0x0b6c 417 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 418 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 419 #define RADEON_SURFACE7_INFO 0x0b7c 420 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 421 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 422 #define RADEON_SW_SEMAPHORE 0x013c 423 424 #define RADEON_WAIT_UNTIL 0x1720 425 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) 426 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 427 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 428 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 429 430 #define RADEON_RB3D_ZMASKOFFSET 0x1c34 431 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 432 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 433 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 434 435 436 /* CP registers */ 437 #define RADEON_CP_ME_RAM_ADDR 0x07d4 438 #define RADEON_CP_ME_RAM_RADDR 0x07d8 439 #define RADEON_CP_ME_RAM_DATAH 0x07dc 440 #define RADEON_CP_ME_RAM_DATAL 0x07e0 441 442 #define RADEON_CP_RB_BASE 0x0700 443 #define RADEON_CP_RB_CNTL 0x0704 444 #define RADEON_CP_RB_RPTR_ADDR 0x070c 445 #define RADEON_CP_RB_RPTR 0x0710 446 #define RADEON_CP_RB_WPTR 0x0714 447 448 #define RADEON_CP_RB_WPTR_DELAY 0x0718 449 # define RADEON_PRE_WRITE_TIMER_SHIFT 0 450 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 451 452 #define RADEON_CP_IB_BASE 0x0738 453 454 #define RADEON_CP_CSQ_CNTL 0x0740 455 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 456 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 457 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 458 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 459 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 460 # define RADEON_CSQ_PRIBM_INDBM (4 << 28) 461 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 462 463 #define RADEON_AIC_CNTL 0x01d0 464 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 465 466 /* CP command packets */ 467 #define RADEON_CP_PACKET0 0x00000000 468 # define RADEON_ONE_REG_WR (1 << 15) 469 #define RADEON_CP_PACKET1 0x40000000 470 #define RADEON_CP_PACKET2 0x80000000 471 #define RADEON_CP_PACKET3 0xC0000000 472 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 473 # define RADEON_WAIT_FOR_IDLE 0x00002600 474 # define RADEON_3D_DRAW_IMMD 0x00002900 475 # define RADEON_3D_CLEAR_ZMASK 0x00003200 476 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 477 # define RADEON_CNTL_PAINT_MULTI 0x00009A00 478 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 479 480 #define RADEON_CP_PACKET_MASK 0xC0000000 481 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 482 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff 483 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 484 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 485 486 #define RADEON_VTX_Z_PRESENT (1 << 31) 487 488 #define RADEON_PRIM_TYPE_NONE (0 << 0) 489 #define RADEON_PRIM_TYPE_POINT (1 << 0) 490 #define RADEON_PRIM_TYPE_LINE (2 << 0) 491 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 492 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 493 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 494 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 495 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 496 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 497 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 498 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 499 #define RADEON_PRIM_WALK_IND (1 << 4) 500 #define RADEON_PRIM_WALK_LIST (2 << 4) 501 #define RADEON_PRIM_WALK_RING (3 << 4) 502 #define RADEON_COLOR_ORDER_BGRA (0 << 6) 503 #define RADEON_COLOR_ORDER_RGBA (1 << 6) 504 #define RADEON_MAOS_ENABLE (1 << 7) 505 #define RADEON_VTX_FMT_R128_MODE (0 << 8) 506 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 507 #define RADEON_NUM_VERTICES_SHIFT 16 508 509 #define RADEON_COLOR_FORMAT_CI8 2 510 #define RADEON_COLOR_FORMAT_ARGB1555 3 511 #define RADEON_COLOR_FORMAT_RGB565 4 512 #define RADEON_COLOR_FORMAT_ARGB8888 6 513 #define RADEON_COLOR_FORMAT_RGB332 7 514 #define RADEON_COLOR_FORMAT_RGB8 9 515 #define RADEON_COLOR_FORMAT_ARGB4444 15 516 517 #define RADEON_TXF_8BPP_I 0 518 #define RADEON_TXF_16BPP_AI88 1 519 #define RADEON_TXF_8BPP_RGB332 2 520 #define RADEON_TXF_16BPP_ARGB1555 3 521 #define RADEON_TXF_16BPP_RGB565 4 522 #define RADEON_TXF_16BPP_ARGB4444 5 523 #define RADEON_TXF_32BPP_ARGB8888 6 524 #define RADEON_TXF_32BPP_RGBA8888 7 525 526 /* Constants */ 527 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 528 529 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 530 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 531 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 532 #define RADEON_LAST_DISPATCH 1 533 534 #define RADEON_MAX_VB_AGE 0x7fffffff 535 #define RADEON_MAX_VB_VERTS (0xffff) 536 537 538 #define RADEON_BASE(reg) ((u32)(dev_priv->mmio->handle)) 539 #define RADEON_ADDR(reg) (RADEON_BASE(reg) + reg) 540 541 #define RADEON_DEREF(reg) *(__volatile__ u32 *)RADEON_ADDR(reg) 542 #define RADEON_READ(reg) RADEON_DEREF(reg) 543 #define RADEON_WRITE(reg,val) do { RADEON_DEREF(reg) = val; } while (0) 544 545 #define RADEON_DEREF8(reg) *(__volatile__ u8 *)RADEON_ADDR(reg) 546 #define RADEON_READ8(reg) RADEON_DEREF8(reg) 547 #define RADEON_WRITE8(reg,val) do { RADEON_DEREF8(reg) = val; } while (0) 548 549 #define RADEON_WRITE_PLL(addr,val) \ 550 do { \ 551 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ 552 ((addr) & 0x1f) | RADEON_PLL_WR_EN); \ 553 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ 554 } while (0) 555 556 extern int RADEON_READ_PLL(drm_device_t *dev, int addr); 557 558 559 560 #define CP_PACKET0( reg, n ) \ 561 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 562 #define CP_PACKET0_TABLE( reg, n ) \ 563 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 564 #define CP_PACKET1( reg0, reg1 ) \ 565 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 566 #define CP_PACKET2() \ 567 (RADEON_CP_PACKET2) 568 #define CP_PACKET3( pkt, n ) \ 569 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 570 571 572 /* ================================================================ 573 * Engine control helper macros 574 */ 575 576 #define RADEON_WAIT_UNTIL_2D_IDLE() \ 577 do { \ 578 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 579 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 580 RADEON_WAIT_HOST_IDLECLEAN) ); \ 581 } while (0) 582 583 #define RADEON_WAIT_UNTIL_3D_IDLE() \ 584 do { \ 585 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 586 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 587 RADEON_WAIT_HOST_IDLECLEAN) ); \ 588 } while (0) 589 590 #define RADEON_WAIT_UNTIL_IDLE() \ 591 do { \ 592 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 593 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 594 RADEON_WAIT_3D_IDLECLEAN | \ 595 RADEON_WAIT_HOST_IDLECLEAN) ); \ 596 } while (0) 597 598 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() \ 599 do { \ 600 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 601 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 602 } while (0) 603 604 #define RADEON_FLUSH_CACHE() \ 605 do { \ 606 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 607 OUT_RING( RADEON_RB2D_DC_FLUSH ); \ 608 } while (0) 609 610 #define RADEON_PURGE_CACHE() \ 611 do { \ 612 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 613 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ 614 } while (0) 615 616 #define RADEON_FLUSH_ZCACHE() \ 617 do { \ 618 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 619 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 620 } while (0) 621 622 #define RADEON_PURGE_ZCACHE() \ 623 do { \ 624 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 625 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 626 } while (0) 627 628 629 /* ================================================================ 630 * Misc helper macros 631 */ 632 633 #define VB_AGE_CHECK_WITH_RET( dev_priv ) \ 634 do { \ 635 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 636 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 637 int __ret = radeon_do_cp_idle( dev_priv ); \ 638 if ( __ret < 0 ) return __ret; \ 639 sarea_priv->last_dispatch = 0; \ 640 radeon_freelist_reset( dev ); \ 641 } \ 642 } while (0) 643 644 #define RADEON_DISPATCH_AGE( age ) \ 645 do { \ 646 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 647 OUT_RING( age ); \ 648 } while (0) 649 650 #define RADEON_FRAME_AGE( age ) \ 651 do { \ 652 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 653 OUT_RING( age ); \ 654 } while (0) 655 656 #define RADEON_CLEAR_AGE( age ) \ 657 do { \ 658 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 659 OUT_RING( age ); \ 660 } while (0) 661 662 663 /* ================================================================ 664 * Ring control 665 */ 666 667 #define radeon_flush_write_combine() mb() 668 669 670 #define RADEON_VERBOSE 0 671 672 #define RING_LOCALS int write; unsigned int mask; volatile u32 *ring; 673 674 #define BEGIN_RING( n ) do { \ 675 if ( RADEON_VERBOSE ) { \ 676 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ 677 n, __FUNCTION__ ); \ 678 } \ 679 if ( dev_priv->ring.space < (n) * sizeof(u32) ) { \ 680 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 681 } \ 682 dev_priv->ring.space -= (n) * sizeof(u32); \ 683 ring = dev_priv->ring.start; \ 684 write = dev_priv->ring.tail; \ 685 mask = dev_priv->ring.tail_mask; \ 686 } while (0) 687 688 #define ADVANCE_RING() do { \ 689 if ( RADEON_VERBOSE ) { \ 690 DRM_INFO( "ADVANCE_RING() tail=0x%06x wr=0x%06x\n", \ 691 write, dev_priv->ring.tail ); \ 692 } \ 693 radeon_flush_write_combine(); \ 694 dev_priv->ring.tail = write; \ 695 RADEON_WRITE( RADEON_CP_RB_WPTR, write ); \ 696 } while (0) 697 698 #define OUT_RING( x ) do { \ 699 if ( RADEON_VERBOSE ) { \ 700 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 701 (unsigned int)(x), write ); \ 702 } \ 703 ring[write++] = (x); \ 704 write &= mask; \ 705 } while (0) 706 707 #define RADEON_PERFORMANCE_BOXES 0 708 709 #endif /* __RADEON_DRV_H__ */ 710