1 /* 2 * AGPGART module version 0.99 3 * Copyright (C) 1999 Jeff Hartmann 4 * Copyright (C) 1999 Precision Insight, Inc. 5 * Copyright (C) 1999 Xi Graphics, Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included 15 * in all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, 21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE 23 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _AGP_BACKEND_PRIV_H 28 #define _AGP_BACKEND_PRIV_H 1 29 30 enum aper_size_type { 31 U8_APER_SIZE, 32 U16_APER_SIZE, 33 U32_APER_SIZE, 34 LVL2_APER_SIZE, 35 FIXED_APER_SIZE 36 }; 37 38 typedef struct _gatt_mask { 39 unsigned long mask; 40 u32 type; 41 /* totally device specific, for integrated chipsets that 42 * might have different types of memory masks. For other 43 * devices this will probably be ignored */ 44 } gatt_mask; 45 46 typedef struct _aper_size_info_8 { 47 int size; 48 int num_entries; 49 int page_order; 50 u8 size_value; 51 } aper_size_info_8; 52 53 typedef struct _aper_size_info_16 { 54 int size; 55 int num_entries; 56 int page_order; 57 u16 size_value; 58 } aper_size_info_16; 59 60 typedef struct _aper_size_info_32 { 61 int size; 62 int num_entries; 63 int page_order; 64 u32 size_value; 65 } aper_size_info_32; 66 67 typedef struct _aper_size_info_lvl2 { 68 int size; 69 int num_entries; 70 u32 size_value; 71 } aper_size_info_lvl2; 72 73 typedef struct _aper_size_info_fixed { 74 int size; 75 int num_entries; 76 int page_order; 77 } aper_size_info_fixed; 78 79 struct agp_bridge_data { 80 agp_version *version; 81 void *aperture_sizes; 82 void *previous_size; 83 void *current_size; 84 void *dev_private_data; 85 struct pci_dev *dev; 86 gatt_mask *masks; 87 u32 *gatt_table; 88 u32 *gatt_table_real; 89 unsigned long scratch_page; 90 unsigned long scratch_page_real; 91 unsigned long gart_bus_addr; 92 unsigned long gatt_bus_addr; 93 u32 mode; 94 enum chipset_type type; 95 enum aper_size_type size_type; 96 unsigned long *key_list; 97 atomic_t current_memory_agp; 98 atomic_t agp_in_use; 99 int max_memory_agp; /* in number of pages */ 100 int needs_scratch_page; 101 int aperture_size_idx; 102 int num_aperture_sizes; 103 int capndx; 104 int cant_use_aperture; 105 106 /* Links to driver specific functions */ 107 108 int (*fetch_size) (void); 109 int (*configure) (void); 110 void (*agp_enable) (u32); 111 void (*cleanup) (void); 112 void (*tlb_flush) (agp_memory *); 113 unsigned long (*mask_memory) (unsigned long, int); 114 void (*cache_flush) (void); 115 int (*create_gatt_table) (void); 116 int (*free_gatt_table) (void); 117 int (*insert_memory) (agp_memory *, off_t, int); 118 int (*remove_memory) (agp_memory *, off_t, int); 119 agp_memory *(*alloc_by_type) (size_t, int); 120 void (*free_by_type) (agp_memory *); 121 unsigned long (*agp_alloc_page) (void); 122 void (*agp_destroy_page) (unsigned long); 123 int (*suspend)(void); 124 void (*resume)(void); 125 126 }; 127 128 #define OUTREG64(mmap, addr, val) __raw_writeq((val), (mmap)+(addr)) 129 #define OUTREG32(mmap, addr, val) __raw_writel((val), (mmap)+(addr)) 130 #define OUTREG16(mmap, addr, val) __raw_writew((val), (mmap)+(addr)) 131 #define OUTREG8(mmap, addr, val) __raw_writeb((val), (mmap)+(addr)) 132 133 #define INREG64(mmap, addr) __raw_readq((mmap)+(addr)) 134 #define INREG32(mmap, addr) __raw_readl((mmap)+(addr)) 135 #define INREG16(mmap, addr) __raw_readw((mmap)+(addr)) 136 #define INREG8(mmap, addr) __raw_readb((mmap)+(addr)) 137 138 #define KB(x) ((x) * 1024) 139 #define MB(x) (KB (KB (x))) 140 #define GB(x) (MB (KB (x))) 141 142 #define CACHE_FLUSH agp_bridge.cache_flush 143 #define A_SIZE_8(x) ((aper_size_info_8 *) x) 144 #define A_SIZE_16(x) ((aper_size_info_16 *) x) 145 #define A_SIZE_32(x) ((aper_size_info_32 *) x) 146 #define A_SIZE_LVL2(x) ((aper_size_info_lvl2 *) x) 147 #define A_SIZE_FIX(x) ((aper_size_info_fixed *) x) 148 #define A_IDX8() (A_SIZE_8(agp_bridge.aperture_sizes) + i) 149 #define A_IDX16() (A_SIZE_16(agp_bridge.aperture_sizes) + i) 150 #define A_IDX32() (A_SIZE_32(agp_bridge.aperture_sizes) + i) 151 #define A_IDXLVL2() (A_SIZE_LVL2(agp_bridge.aperture_sizes) + i) 152 #define A_IDXFIX() (A_SIZE_FIX(agp_bridge.aperture_sizes) + i) 153 #define MAXKEY (4096 * 32) 154 155 #define AGPGART_MODULE_NAME "agpgart" 156 #define PFX AGPGART_MODULE_NAME ": " 157 158 #define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge.scratch_page) 159 160 #ifndef PCI_DEVICE_ID_VIA_82C691_0 161 #define PCI_DEVICE_ID_VIA_82C691_0 0x0691 162 #endif 163 #ifndef PCI_DEVICE_ID_VIA_8371_0 164 #define PCI_DEVICE_ID_VIA_8371_0 0x0391 165 #endif 166 #ifndef PCI_DEVICE_ID_VIA_8363_0 167 #define PCI_DEVICE_ID_VIA_8363_0 0x0305 168 #endif 169 #ifndef PCI_DEVICE_ID_VIA_8601_0 170 #define PCI_DEVICE_ID_VIA_8601_0 0x0601 171 #endif 172 #ifndef PCI_DEVICE_ID_VIA_82C694X_0 173 #define PCI_DEVICE_ID_VIA_82C694X_0 0x0605 174 #endif 175 #ifndef PCI_DEVICE_ID_VIA_8380_0 176 #define PCI_DEVICE_ID_VIA_8380_0 0x0204 177 #endif 178 #ifndef PCI_DEVICE_ID_VIA_8385_0 179 #define PCI_DEVICE_ID_VIA_8385_0 0x3188 180 #endif 181 #ifndef PCI_DEVICE_ID_INTEL_810_0 182 #define PCI_DEVICE_ID_INTEL_810_0 0x7120 183 #endif 184 #ifndef PCI_DEVICE_ID_INTEL_845_G_0 185 #define PCI_DEVICE_ID_INTEL_845_G_0 0x2560 186 #endif 187 #ifndef PCI_DEVICE_ID_INTEL_845_G_1 188 #define PCI_DEVICE_ID_INTEL_845_G_1 0x2562 189 #endif 190 #ifndef PCI_DEVICE_ID_INTEL_830_M_0 191 #define PCI_DEVICE_ID_INTEL_830_M_0 0x3575 192 #endif 193 #ifndef PCI_DEVICE_ID_INTEL_830_M_1 194 #define PCI_DEVICE_ID_INTEL_830_M_1 0x3577 195 #endif 196 #ifndef PCI_DEVICE_ID_INTEL_855_GM_0 197 #define PCI_DEVICE_ID_INTEL_855_GM_0 0x3580 198 #endif 199 #ifndef PCI_DEVICE_ID_INTEL_855_GM_1 200 #define PCI_DEVICE_ID_INTEL_855_GM_1 0x3582 201 #endif 202 #ifndef PCI_DEVICE_ID_INTEL_855_PM_0 203 #define PCI_DEVICE_ID_INTEL_855_PM_0 0x3340 204 #endif 205 #ifndef PCI_DEVICE_ID_INTEL_855_PM_1 206 #define PCI_DEVICE_ID_INTEL_855_PM_1 0x3342 207 #endif 208 #ifndef PCI_DEVICE_ID_INTEL_865_G_0 209 #define PCI_DEVICE_ID_INTEL_865_G_0 0x2570 210 #endif 211 #ifndef PCI_DEVICE_ID_INTEL_865_G_1 212 #define PCI_DEVICE_ID_INTEL_865_G_1 0x2572 213 #endif 214 #ifndef PCI_DEVICE_ID_INTEL_915_G_0 215 #define PCI_DEVICE_ID_INTEL_915_G_0 0x2580 216 #endif 217 #ifndef PCI_DEVICE_ID_INTEL_915_G_1 218 #define PCI_DEVICE_ID_INTEL_915_G_1 0x2582 219 #endif 220 #ifndef PCI_DEVICE_ID_INTEL_915_GM_0 221 #define PCI_DEVICE_ID_INTEL_915_GM_0 0x2590 222 #endif 223 #ifndef PCI_DEVICE_ID_INTEL_915_GM_1 224 #define PCI_DEVICE_ID_INTEL_915_GM_1 0x2592 225 #endif 226 #ifndef PCI_DEVICE_ID_INTEL_820_0 227 #define PCI_DEVICE_ID_INTEL_820_0 0x2500 228 #endif 229 #ifndef PCI_DEVICE_ID_INTEL_820_UP_0 230 #define PCI_DEVICE_ID_INTEL_820_UP_0 0x2501 231 #endif 232 #ifndef PCI_DEVICE_ID_INTEL_840_0 233 #define PCI_DEVICE_ID_INTEL_840_0 0x1a21 234 #endif 235 #ifndef PCI_DEVICE_ID_INTEL_845_0 236 #define PCI_DEVICE_ID_INTEL_845_0 0x1a30 237 #endif 238 #ifndef PCI_DEVICE_ID_INTEL_850_0 239 #define PCI_DEVICE_ID_INTEL_850_0 0x2530 240 #endif 241 #ifndef PCI_DEVICE_ID_INTEL_860_0 242 #define PCI_DEVICE_ID_INTEL_860_0 0x2531 243 #endif 244 #ifndef PCI_DEVICE_ID_INTEL_7205_0 245 #define PCI_DEVICE_ID_INTEL_7205_0 0x255d 246 #endif 247 #ifndef PCI_DEVICE_ID_INTEL_7505_0 248 #define PCI_DEVICE_ID_INTEL_7505_0 0x2550 249 #endif 250 #ifndef PCI_DEVICE_ID_INTEL_810_DC100_0 251 #define PCI_DEVICE_ID_INTEL_810_DC100_0 0x7122 252 #endif 253 #ifndef PCI_DEVICE_ID_INTEL_810_E_0 254 #define PCI_DEVICE_ID_INTEL_810_E_0 0x7124 255 #endif 256 #ifndef PCI_DEVICE_ID_INTEL_82443GX_0 257 #define PCI_DEVICE_ID_INTEL_82443GX_0 0x71a0 258 #endif 259 #ifndef PCI_DEVICE_ID_INTEL_810_1 260 #define PCI_DEVICE_ID_INTEL_810_1 0x7121 261 #endif 262 #ifndef PCI_DEVICE_ID_INTEL_810_DC100_1 263 #define PCI_DEVICE_ID_INTEL_810_DC100_1 0x7123 264 #endif 265 #ifndef PCI_DEVICE_ID_INTEL_810_E_1 266 #define PCI_DEVICE_ID_INTEL_810_E_1 0x7125 267 #endif 268 #ifndef PCI_DEVICE_ID_INTEL_815_0 269 #define PCI_DEVICE_ID_INTEL_815_0 0x1130 270 #endif 271 #ifndef PCI_DEVICE_ID_INTEL_815_1 272 #define PCI_DEVICE_ID_INTEL_815_1 0x1132 273 #endif 274 #ifndef PCI_DEVICE_ID_INTEL_82443GX_1 275 #define PCI_DEVICE_ID_INTEL_82443GX_1 0x71a1 276 #endif 277 #ifndef PCI_DEVICE_ID_INTEL_460GX 278 #define PCI_DEVICE_ID_INTEL_460GX 0x84ea 279 #endif 280 #ifndef PCI_DEVICE_ID_AMD_IRONGATE_0 281 #define PCI_DEVICE_ID_AMD_IRONGATE_0 0x7006 282 #endif 283 #ifndef PCI_DEVICE_ID_AMD_761_0 284 #define PCI_DEVICE_ID_AMD_761_0 0x700e 285 #endif 286 #ifndef PCI_DEVICE_ID_AMD_762_0 287 #define PCI_DEVICE_ID_AMD_762_0 0x700C 288 #endif 289 #ifndef PCI_DEVICE_ID_AMD_8151_0 290 #define PCI_DEVICE_ID_AMD_8151_0 0x7454 291 #endif 292 #ifndef PCI_VENDOR_ID_AL 293 #define PCI_VENDOR_ID_AL 0x10b9 294 #endif 295 #ifndef PCI_DEVICE_ID_AL_M1541_0 296 #define PCI_DEVICE_ID_AL_M1541_0 0x1541 297 #endif 298 #ifndef PCI_DEVICE_ID_AL_M1621_0 299 #define PCI_DEVICE_ID_AL_M1621_0 0x1621 300 #endif 301 #ifndef PCI_DEVICE_ID_AL_M1631_0 302 #define PCI_DEVICE_ID_AL_M1631_0 0x1631 303 #endif 304 #ifndef PCI_DEVICE_ID_AL_M1632_0 305 #define PCI_DEVICE_ID_AL_M1632_0 0x1632 306 #endif 307 #ifndef PCI_DEVICE_ID_AL_M1641_0 308 #define PCI_DEVICE_ID_AL_M1641_0 0x1641 309 #endif 310 #ifndef PCI_DEVICE_ID_AL_M1644_0 311 #define PCI_DEVICE_ID_AL_M1644_0 0x1644 312 #endif 313 #ifndef PCI_DEVICE_ID_AL_M1647_0 314 #define PCI_DEVICE_ID_AL_M1647_0 0x1647 315 #endif 316 #ifndef PCI_DEVICE_ID_AL_M1651_0 317 #define PCI_DEVICE_ID_AL_M1651_0 0x1651 318 #endif 319 #ifndef PCI_DEVICE_ID_AL_M1671_0 320 #define PCI_DEVICE_ID_AL_M1671_0 0x1671 321 #endif 322 #ifndef PCI_VENDOR_ID_ATI 323 #define PCI_VENDOR_ID_ATI 0x1002 324 #endif 325 #ifndef PCI_DEVICE_ID_ATI_RS100 326 #define PCI_DEVICE_ID_ATI_RS100 0xcab0 327 #endif 328 #ifndef PCI_DEVICE_ID_ATI_RS200 329 #define PCI_DEVICE_ID_ATI_RS200 0xcab2 330 #endif 331 #ifndef PCI_DEVICE_ID_ATI_RS200_REV2 332 #define PCI_DEVICE_ID_ATI_RS200_REV2 0xcbb2 333 #endif 334 #ifndef PCI_DEVICE_ID_ATI_RS250 335 #define PCI_DEVICE_ID_ATI_RS250 0xcab3 336 #endif 337 #ifndef PCI_DEVICE_ID_ATI_RS200_B 338 #define PCI_DEVICE_ID_ATI_RS200_B 0xcbb3 339 #endif 340 #ifndef PCI_DEVICE_ID_ATI_RS300_100 341 #define PCI_DEVICE_ID_ATI_RS300_100 0x5830 342 #endif 343 #ifndef PCI_DEVICE_ID_ATI_RS300_133 344 #define PCI_DEVICE_ID_ATI_RS300_133 0x5831 345 #endif 346 #ifndef PCI_DEVICE_ID_ATI_RS300_166 347 #define PCI_DEVICE_ID_ATI_RS300_166 0x5832 348 #endif 349 #ifndef PCI_DEVICE_ID_ATI_RS300_200 350 #define PCI_DEVICE_ID_ATI_RS300_200 0x5833 351 #endif 352 353 /* intel register */ 354 #define INTEL_APBASE 0x10 355 #define INTEL_APSIZE 0xb4 356 #define INTEL_ATTBASE 0xb8 357 #define INTEL_AGPCTRL 0xb0 358 #define INTEL_NBXCFG 0x50 359 #define INTEL_ERRSTS 0x91 360 361 /* Intel 460GX Registers */ 362 #define INTEL_I460_APBASE 0x10 363 #define INTEL_I460_BAPBASE 0x98 364 #define INTEL_I460_GXBCTL 0xa0 365 #define INTEL_I460_AGPSIZ 0xa2 366 #define INTEL_I460_ATTBASE 0xfe200000 367 #define INTEL_I460_GATT_VALID (1UL << 24) 368 #define INTEL_I460_GATT_COHERENT (1UL << 25) 369 /* Intel 855GM/852GM registers */ 370 #define I855_GMCH_CTRL 0x52 371 #define I855_GMCH_ENABLED 0x4 372 #define I855_GMCH_GMS_MASK (0x7 << 4) 373 #define I855_GMCH_GMS_STOLEN_0M 0x0 374 #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) 375 #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) 376 #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) 377 #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) 378 #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) 379 #define I85X_CAPID 0x44 380 #define I85X_VARIANT_MASK 0x7 381 #define I85X_VARIANT_SHIFT 5 382 #define I855_GME 0x0 383 #define I855_GM 0x4 384 #define I852_GME 0x2 385 #define I852_GM 0x5 386 #define I855_PME 0x0 387 #define I855_PM 0x4 388 #define I852_PME 0x2 389 #define I852_PM 0x5 390 391 /* intel i830 registers */ 392 #define I830_GMCH_CTRL 0x52 393 #define I830_GMCH_ENABLED 0x4 394 #define I830_GMCH_MEM_MASK 0x1 395 #define I830_GMCH_MEM_64M 0x1 396 #define I830_GMCH_MEM_128M 0 397 #define I830_GMCH_GMS_MASK 0x70 398 #define I830_GMCH_GMS_DISABLED 0x00 399 #define I830_GMCH_GMS_LOCAL 0x10 400 #define I830_GMCH_GMS_STOLEN_512 0x20 401 #define I830_GMCH_GMS_STOLEN_1024 0x30 402 #define I830_GMCH_GMS_STOLEN_8192 0x40 403 #define I830_RDRAM_CHANNEL_TYPE 0x03010 404 #define I830_RDRAM_ND(x) (((x) & 0x20) >> 5) 405 #define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3) 406 407 /* This one is for I830MP w. an external graphic card */ 408 #define INTEL_I830_ERRSTS 0x92 409 410 /* intel 815 register */ 411 #define INTEL_815_APCONT 0x51 412 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 413 414 /* intel i820 registers */ 415 #define INTEL_I820_RDCR 0x51 416 #define INTEL_I820_ERRSTS 0xc8 417 418 /* intel i840 registers */ 419 #define INTEL_I840_MCHCFG 0x50 420 #define INTEL_I840_ERRSTS 0xc8 421 422 /* intel i845 registers */ 423 #define INTEL_I845_AGPM 0x51 424 #define INTEL_I845_ERRSTS 0xc8 425 426 /* intel i850 registers */ 427 #define INTEL_I850_MCHCFG 0x50 428 #define INTEL_I850_ERRSTS 0xc8 429 430 /* intel i860 registers */ 431 #define INTEL_I860_MCHCFG 0x50 432 #define INTEL_I860_ERRSTS 0xc8 433 434 /* intel i7505 registers */ 435 #define INTEL_I7505_MCHCFG 0x50 436 #define INTEL_I7505_ERRSTS 0x42 437 438 /* intel i810 registers */ 439 #define I810_GMADDR 0x10 440 #define I810_MMADDR 0x14 441 #define I810_PTE_BASE 0x10000 442 #define I810_PTE_MAIN_UNCACHED 0x00000000 443 #define I810_PTE_LOCAL 0x00000002 444 #define I810_PTE_VALID 0x00000001 445 #define I810_SMRAM_MISCC 0x70 446 #define I810_GFX_MEM_WIN_SIZE 0x00010000 447 #define I810_GFX_MEM_WIN_32M 0x00010000 448 #define I810_GMS 0x000000c0 449 #define I810_GMS_DISABLE 0x00000000 450 #define I810_PGETBL_CTL 0x2020 451 #define I810_PGETBL_ENABLED 0x00000001 452 #define I810_DRAM_CTL 0x3000 453 #define I810_DRAM_ROW_0 0x00000001 454 #define I810_DRAM_ROW_0_SDRAM 0x00000001 455 456 /* intel I915 registers */ 457 #define I915_GMADDR 0x18 458 #define I915_MMADDR 0x10 459 #define I915_PTEADDR 0x1C 460 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 461 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 462 463 464 /* VIA register */ 465 #define VIA_APBASE 0x10 466 #define VIA_GARTCTRL 0x80 467 #define VIA_APSIZE 0x84 468 #define VIA_ATTBASE 0x88 469 470 /* SiS registers */ 471 #define SIS_APBASE 0x10 472 #define SIS_ATTBASE 0x90 473 #define SIS_APSIZE 0x94 474 #define SIS_TLBCNTRL 0x97 475 #define SIS_TLBFLUSH 0x98 476 477 /* AMD registers */ 478 #define AMD_APBASE 0x10 479 #define AMD_MMBASE 0x14 480 #define AMD_APSIZE 0xac 481 #define AMD_MODECNTL 0xb0 482 #define AMD_MODECNTL2 0xb2 483 #define AMD_GARTENABLE 0x02 /* In mmio region (16-bit register) */ 484 #define AMD_ATTBASE 0x04 /* In mmio region (32-bit register) */ 485 #define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */ 486 #define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */ 487 488 #define AMD_8151_APSIZE 0xb4 489 #define AMD_8151_GARTBLOCK 0xb8 490 491 #define AMD_X86_64_GARTAPERTURECTL 0x90 492 #define AMD_X86_64_GARTAPERTUREBASE 0x94 493 #define AMD_X86_64_GARTTABLEBASE 0x98 494 #define AMD_X86_64_GARTCACHECTL 0x9c 495 #define AMD_X86_64_GARTEN 1<<0 496 497 #define AMD_8151_VMAPERTURE 0x10 498 #define AMD_8151_AGP_CTL 0xb0 499 #define AMD_8151_APERTURESIZE 0xb4 500 #define AMD_8151_GARTPTR 0xb8 501 #define AMD_8151_GTLBEN 1<<7 502 #define AMD_8151_APEREN 1<<8 503 504 /* ALi registers */ 505 #define ALI_APBASE 0x10 506 #define ALI_AGPCTRL 0xb8 507 #define ALI_ATTBASE 0xbc 508 #define ALI_TLBCTRL 0xc0 509 #define ALI_TAGCTRL 0xc4 510 #define ALI_CACHE_FLUSH_CTRL 0xD0 511 #define ALI_CACHE_FLUSH_ADDR_MASK 0xFFFFF000 512 #define ALI_CACHE_FLUSH_EN 0x100 513 514 /* Serverworks Registers */ 515 #define SVWRKS_APSIZE 0x10 516 #define SVWRKS_SIZE_MASK 0xfe000000 517 518 #define SVWRKS_MMBASE 0x14 519 #define SVWRKS_CACHING 0x4b 520 #define SVWRKS_FEATURE 0x68 521 522 /* func 1 registers */ 523 #define SVWRKS_AGP_ENABLE 0x60 524 #define SVWRKS_COMMAND 0x04 525 526 /* Memory mapped registers */ 527 #define SVWRKS_GART_CACHE 0x02 528 #define SVWRKS_GATTBASE 0x04 529 #define SVWRKS_TLBFLUSH 0x10 530 #define SVWRKS_POSTFLUSH 0x14 531 #define SVWRKS_DIRFLUSH 0x0c 532 533 /* NVIDIA registers */ 534 #define NVIDIA_0_APBASE 0x10 535 #define NVIDIA_0_APSIZE 0x80 536 #define NVIDIA_1_WBC 0xf0 537 #define NVIDIA_2_GARTCTRL 0xd0 538 #define NVIDIA_2_APBASE 0xd8 539 #define NVIDIA_2_APLIMIT 0xdc 540 #define NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4) 541 #define NVIDIA_3_APBASE 0x50 542 #define NVIDIA_3_APLIMIT 0x54 543 544 /* NVIDIA x86-64 registers */ 545 #define NVIDIA_X86_64_0_APBASE 0x10 546 #define NVIDIA_X86_64_1_APBASE1 0x50 547 #define NVIDIA_X86_64_1_APLIMIT1 0x54 548 #define NVIDIA_X86_64_1_APSIZE 0xa8 549 #define NVIDIA_X86_64_1_APBASE2 0xd8 550 #define NVIDIA_X86_64_1_APLIMIT2 0xdc 551 552 /* HP ZX1 IOC registers */ 553 #define HP_ZX1_IBASE 0x300 554 #define HP_ZX1_IMASK 0x308 555 #define HP_ZX1_PCOM 0x310 556 #define HP_ZX1_TCNFG 0x318 557 #define HP_ZX1_PDIR_BASE 0x320 558 559 /* HP ZX1 LBA registers */ 560 #define HP_ZX1_AGP_STATUS 0x64 561 #define HP_ZX1_AGP_COMMAND 0x68 562 563 /* ATI register */ 564 #define ATI_APBASE 0x10 565 #define ATI_GART_MMBASE_ADDR 0x14 566 #define ATI_RS100_APSIZE 0xac 567 #define ATI_RS300_APSIZE 0xf8 568 #define ATI_RS100_IG_AGPMODE 0xb0 569 #define ATI_RS300_IG_AGPMODE 0xfc 570 571 #define ATI_GART_FEATURE_ID 0x00 572 #define ATI_GART_BASE 0x04 573 #define ATI_GART_CACHE_SZBASE 0x08 574 #define ATI_GART_CACHE_CNTRL 0x0c 575 #define ATI_GART_CACHE_ENTRY_CNTRL 0x10 576 577 #endif /* _AGP_BACKEND_PRIV_H */ 578