1 /* 2 * linux/drivers/acorn/net/ether3.h 3 * 4 * Copyright (C) 1995-2000 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * network driver for Acorn/ANT Ether3 cards 11 */ 12 13 #ifndef _LINUX_ether3_H 14 #define _LINUX_ether3_H 15 16 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */ 17 #define DEBUG_TX 2 18 #define DEBUG_RX 4 19 #define DEBUG_INT 8 20 #define DEBUG_IC 16 21 #ifndef NET_DEBUG 22 #define NET_DEBUG 0 23 #endif 24 25 /* Command register definitions & bits */ 26 #define REG_COMMAND (dev->base_addr + 0x00) 27 #define CMD_ENINTDMA 0x0001 28 #define CMD_ENINTRX 0x0002 29 #define CMD_ENINTTX 0x0004 30 #define CMD_ENINTBUFWIN 0x0008 31 #define CMD_ACKINTDMA 0x0010 32 #define CMD_ACKINTRX 0x0020 33 #define CMD_ACKINTTX 0x0040 34 #define CMD_ACKINTBUFWIN 0x0080 35 #define CMD_DMAON 0x0100 36 #define CMD_RXON 0x0200 37 #define CMD_TXON 0x0400 38 #define CMD_DMAOFF 0x0800 39 #define CMD_RXOFF 0x1000 40 #define CMD_TXOFF 0x2000 41 #define CMD_FIFOREAD 0x4000 42 #define CMD_FIFOWRITE 0x8000 43 44 /* status register */ 45 #define REG_STATUS (dev->base_addr + 0x00) 46 #define STAT_ENINTSTAT 0x0001 47 #define STAT_ENINTRX 0x0002 48 #define STAT_ENINTTX 0x0004 49 #define STAT_ENINTBUFWIN 0x0008 50 #define STAT_INTDMA 0x0010 51 #define STAT_INTRX 0x0020 52 #define STAT_INTTX 0x0040 53 #define STAT_INTBUFWIN 0x0080 54 #define STAT_DMAON 0x0100 55 #define STAT_RXON 0x0200 56 #define STAT_TXON 0x0400 57 #define STAT_FIFOFULL 0x2000 58 #define STAT_FIFOEMPTY 0x4000 59 #define STAT_FIFODIR 0x8000 60 61 /* configuration register 1 */ 62 #define REG_CONFIG1 (dev->base_addr + 0x10) 63 #define CFG1_BUFSELSTAT0 0x0000 64 #define CFG1_BUFSELSTAT1 0x0001 65 #define CFG1_BUFSELSTAT2 0x0002 66 #define CFG1_BUFSELSTAT3 0x0003 67 #define CFG1_BUFSELSTAT4 0x0004 68 #define CFG1_BUFSELSTAT5 0x0005 69 #define CFG1_ADDRPROM 0x0006 70 #define CFG1_TRANSEND 0x0007 71 #define CFG1_LOCBUFMEM 0x0008 72 #define CFG1_INTVECTOR 0x0009 73 #define CFG1_RECVSPECONLY 0x0000 74 #define CFG1_RECVSPECBROAD 0x4000 75 #define CFG1_RECVSPECBRMULTI 0x8000 76 #define CFG1_RECVPROMISC 0xC000 77 78 /* The following aren't in 8004 */ 79 #define CFG1_DMABURSTCONT 0x0000 80 #define CFG1_DMABURST800NS 0x0010 81 #define CFG1_DMABURST1600NS 0x0020 82 #define CFG1_DMABURST3200NS 0x0030 83 #define CFG1_DMABURST1 0x0000 84 #define CFG1_DMABURST4 0x0040 85 #define CFG1_DMABURST8 0x0080 86 #define CFG1_DMABURST16 0x00C0 87 #define CFG1_RECVCOMPSTAT0 0x0100 88 #define CFG1_RECVCOMPSTAT1 0x0200 89 #define CFG1_RECVCOMPSTAT2 0x0400 90 #define CFG1_RECVCOMPSTAT3 0x0800 91 #define CFG1_RECVCOMPSTAT4 0x1000 92 #define CFG1_RECVCOMPSTAT5 0x2000 93 94 /* configuration register 2 */ 95 #define REG_CONFIG2 (dev->base_addr + 0x20) 96 #define CFG2_BYTESWAP 0x0001 97 #define CFG2_ERRENCRC 0x0008 98 #define CFG2_ERRENDRIBBLE 0x0010 99 #define CFG2_ERRSHORTFRAME 0x0020 100 #define CFG2_SLOTSELECT 0x0040 101 #define CFG2_PREAMSELECT 0x0080 102 #define CFG2_ADDRLENGTH 0x0100 103 #define CFG2_RECVCRC 0x0200 104 #define CFG2_XMITNOCRC 0x0400 105 #define CFG2_LOOPBACK 0x0800 106 #define CFG2_CTRLO 0x1000 107 #define CFG2_RESET 0x8000 108 109 #define REG_RECVEND (dev->base_addr + 0x30) 110 111 #define REG_BUFWIN (dev->base_addr + 0x40) 112 113 #define REG_RECVPTR (dev->base_addr + 0x50) 114 115 #define REG_TRANSMITPTR (dev->base_addr + 0x60) 116 117 #define REG_DMAADDR (dev->base_addr + 0x70) 118 119 /* 120 * Cards transmit/receive headers 121 */ 122 #define TX_NEXT (0xffff) 123 #define TXHDR_ENBABBLEINT (1 << 16) 124 #define TXHDR_ENCOLLISIONINT (1 << 17) 125 #define TXHDR_EN16COLLISION (1 << 18) 126 #define TXHDR_ENSUCCESS (1 << 19) 127 #define TXHDR_DATAFOLLOWS (1 << 21) 128 #define TXHDR_CHAINCONTINUE (1 << 22) 129 #define TXHDR_TRANSMIT (1 << 23) 130 #define TXSTAT_BABBLED (1 << 24) 131 #define TXSTAT_COLLISION (1 << 25) 132 #define TXSTAT_16COLLISIONS (1 << 26) 133 #define TXSTAT_DONE (1 << 31) 134 135 #define RX_NEXT (0xffff) 136 #define RXHDR_CHAINCONTINUE (1 << 6) 137 #define RXHDR_RECEIVE (1 << 7) 138 #define RXSTAT_OVERSIZE (1 << 8) 139 #define RXSTAT_CRCERROR (1 << 9) 140 #define RXSTAT_DRIBBLEERROR (1 << 10) 141 #define RXSTAT_SHORTPACKET (1 << 11) 142 #define RXSTAT_DONE (1 << 15) 143 144 145 #define TX_START 0x0000 146 #define TX_END 0x6000 147 #define RX_START 0x6000 148 #define RX_LEN 0xA000 149 #define RX_END 0x10000 150 /* must be a power of 2 and greater than MAX_TX_BUFFERED */ 151 #define MAX_TXED 16 152 #define MAX_TX_BUFFERED 10 153 154 struct dev_priv { 155 struct { 156 unsigned int command; 157 unsigned int config1; 158 unsigned int config2; 159 } regs; 160 unsigned char tx_head; /* buffer nr to insert next packet */ 161 unsigned char tx_tail; /* buffer nr of transmitting packet */ 162 unsigned int rx_head; /* address to fetch next packet from */ 163 struct net_device_stats stats; 164 struct timer_list timer; 165 int broken; /* 0 = ok, 1 = something went wrong */ 166 }; 167 168 #endif 169