1 /*
2 * Intel Multiprocessor Specificiation 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/irq.h>
18 #include <linux/init.h>
19 #include <linux/acpi.h>
20 #include <linux/delay.h>
21 #include <linux/config.h>
22 #include <linux/bootmem.h>
23 #include <linux/smp_lock.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/mc146818rtc.h>
26
27 #include <asm/smp.h>
28 #include <asm/acpi.h>
29 #include <asm/mtrr.h>
30 #include <asm/mpspec.h>
31 #include <asm/pgalloc.h>
32 #include <asm/e820.h>
33 #include <asm/proto.h>
34 #include <asm/io_apic.h>
35
36 /* Have we found an MP table */
37 int smp_found_config = 0;
38 #ifdef CONFIG_SMP
39 extern unsigned int max_cpus;
40 #endif
41
42 /*
43 * Various Linux-internal data structures created from the
44 * MP-table.
45 */
46 int apic_version [MAX_APICS];
47 int mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
48 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
49 int mp_current_pci_id = 0;
50 /* I/O APIC entries */
51 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
52
53 /* # of MP IRQ source entries */
54 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
55
56 /* MP IRQ source entries */
57 int mp_irq_entries;
58
59 int nr_ioapics;
60 int pic_mode;
61 unsigned long mp_lapic_addr = 0;
62
63
64
65 /* Processor that is doing the boot up */
66 unsigned int boot_cpu_id = -1U;
67 /* Internal processor count */
68 static unsigned int num_processors = 0;
69
70 /* Bitmask of physically existing CPUs */
71 unsigned long phys_cpu_present_map = 0;
72
73 /*
74 * Intel MP BIOS table parsing routines:
75 */
76
77 /*
78 * Checksum an MP configuration block.
79 */
80
mpf_checksum(unsigned char * mp,int len)81 static int __init mpf_checksum(unsigned char *mp, int len)
82 {
83 int sum = 0;
84
85 while (len--)
86 sum += *mp++;
87
88 return sum & 0xFF;
89 }
90
MP_processor_info(struct mpc_config_processor * m)91 static void __init MP_processor_info (struct mpc_config_processor *m)
92 {
93 int ver;
94
95 if (!(m->mpc_cpuflag & CPU_ENABLED))
96 return;
97
98 printk("Processor #%d %d:%d APIC version %d\n",
99 m->mpc_apicid,
100 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
101 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
102 m->mpc_apicver);
103
104 if (m->mpc_featureflag&(1<<0))
105 Dprintk(" Floating point unit present.\n");
106 if (m->mpc_featureflag&(1<<7))
107 Dprintk(" Machine Exception supported.\n");
108 if (m->mpc_featureflag&(1<<8))
109 Dprintk(" 64 bit compare & exchange supported.\n");
110 if (m->mpc_featureflag&(1<<9))
111 Dprintk(" Internal APIC present.\n");
112
113 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
114 Dprintk(" Bootup CPU\n");
115 boot_cpu_id = m->mpc_apicid;
116 }
117
118 #ifdef CONFIG_SMP
119 if (num_processors >= NR_CPUS) {
120 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
121 " Processor ignored.\n", NR_CPUS);
122 return;
123 }
124 if (num_processors >= max_cpus) {
125 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
126 " Processor ignored.\n", max_cpus);
127 return;
128 }
129 #endif
130
131 num_processors++;
132
133 if (m->mpc_apicid > MAX_APICS) {
134 printk("Processor #%d INVALID. (Max ID: %d).\n",
135 m->mpc_apicid, MAX_APICS);
136 return;
137 }
138 ver = m->mpc_apicver;
139
140 phys_cpu_present_map |= 1 << m->mpc_apicid;
141 /*
142 * Validate version
143 */
144 if (ver == 0x0) {
145 printk("BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
146 ver = 0x10;
147 }
148 apic_version[m->mpc_apicid] = ver;
149 }
150
MP_bus_info(struct mpc_config_bus * m)151 static void __init MP_bus_info (struct mpc_config_bus *m)
152 {
153 char str[7];
154
155 memcpy(str, m->mpc_bustype, 6);
156 str[6] = 0;
157 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
158
159 #if MAX_MP_BUSSES < 256
160 if ((long)m->mpc_busid >= MAX_MP_BUSSES) {
161 printk(KERN_ERR "MAX_MP_BUSSES ERROR mpc_busid %d, max %d\n", m->mpc_busid, MAX_MP_BUSSES);
162 } else
163 #endif
164 if (strncmp(str, "ISA", 3) == 0) {
165 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
166 } else if (strncmp(str, "EISA", 4) == 0) {
167 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
168 } else if (strncmp(str, "PCI", 3) == 0) {
169 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
170 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
171 mp_current_pci_id++;
172 } else if (strncmp(str, "MCA", 3) == 0) {
173 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
174 } else {
175 printk("Unknown bustype %s\n", str);
176 panic("cannot handle bus - mail to linux-smp@vger.kernel.org");
177 }
178 }
179
MP_ioapic_info(struct mpc_config_ioapic * m)180 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
181 {
182 if (!(m->mpc_flags & MPC_APIC_USABLE))
183 return;
184
185 printk("I/O APIC #%d Version %d at 0x%X.\n",
186 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
187 if (nr_ioapics >= MAX_IO_APICS) {
188 printk("Max # of I/O APICs (%d) exceeded (found %d).\n",
189 MAX_IO_APICS, nr_ioapics);
190 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
191 }
192 if (!m->mpc_apicaddr) {
193 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
194 " found in MP table, skipping!\n");
195 return;
196 }
197 mp_ioapics[nr_ioapics] = *m;
198 nr_ioapics++;
199 }
200
MP_intsrc_info(struct mpc_config_intsrc * m)201 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
202 {
203 mp_irqs [mp_irq_entries] = *m;
204 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
205 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
206 m->mpc_irqtype, m->mpc_irqflag & 3,
207 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
208 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
209 if (++mp_irq_entries == MAX_IRQ_SOURCES)
210 panic("Max # of irq sources exceeded!!\n");
211 }
212
MP_lintsrc_info(struct mpc_config_lintsrc * m)213 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
214 {
215 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
216 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
217 m->mpc_irqtype, m->mpc_irqflag & 3,
218 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
219 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
220 /*
221 * Well it seems all SMP boards in existence
222 * use ExtINT/LVT1 == LINT0 and
223 * NMI/LVT2 == LINT1 - the following check
224 * will show us if this assumptions is false.
225 * Until then we do not have to add baggage.
226 */
227 if ((m->mpc_irqtype == mp_ExtINT) &&
228 (m->mpc_destapiclint != 0))
229 BUG();
230 if ((m->mpc_irqtype == mp_NMI) &&
231 (m->mpc_destapiclint != 1))
232 BUG();
233 }
234
235 /*
236 * Read/parse the MPC
237 */
238
smp_read_mpc(struct mp_config_table * mpc)239 static int __init smp_read_mpc(struct mp_config_table *mpc)
240 {
241 char str[16];
242 int count=sizeof(*mpc);
243 unsigned char *mpt=((unsigned char *)mpc)+count;
244
245 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
246 panic("SMP mptable: bad signature [%c%c%c%c]!\n",
247 mpc->mpc_signature[0],
248 mpc->mpc_signature[1],
249 mpc->mpc_signature[2],
250 mpc->mpc_signature[3]);
251 return 0;
252 }
253 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
254 panic("SMP mptable: checksum error!\n");
255 return 0;
256 }
257 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
258 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
259 mpc->mpc_spec);
260 return 0;
261 }
262 if (!mpc->mpc_lapic) {
263 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
264 return 0;
265 }
266 memcpy(str,mpc->mpc_oem,8);
267 str[8]=0;
268 printk("OEM ID: %s ",str);
269
270 memcpy(str,mpc->mpc_productid,12);
271 str[12]=0;
272 printk("Product ID: %s ",str);
273
274 printk("APIC at: 0x%X\n",mpc->mpc_lapic);
275
276 /*
277 * Save the local APIC address (it might be non-default) -- but only
278 * if we're not using ACPI.
279 */
280 if (!acpi_lapic)
281 mp_lapic_addr = mpc->mpc_lapic;
282
283 /*
284 * Now process the configuration blocks.
285 */
286 while (count < mpc->mpc_length) {
287 switch(*mpt) {
288 case MP_PROCESSOR:
289 {
290 struct mpc_config_processor *m=
291 (struct mpc_config_processor *)mpt;
292 /* ACPI may have already provided this data */
293 if (!acpi_lapic)
294 MP_processor_info(m);
295 mpt += sizeof(*m);
296 count += sizeof(*m);
297 break;
298 }
299 case MP_BUS:
300 {
301 struct mpc_config_bus *m=
302 (struct mpc_config_bus *)mpt;
303 MP_bus_info(m);
304 mpt += sizeof(*m);
305 count += sizeof(*m);
306 break;
307 }
308 case MP_IOAPIC:
309 {
310 struct mpc_config_ioapic *m=
311 (struct mpc_config_ioapic *)mpt;
312 MP_ioapic_info(m);
313 mpt+=sizeof(*m);
314 count+=sizeof(*m);
315 break;
316 }
317 case MP_INTSRC:
318 {
319 struct mpc_config_intsrc *m=
320 (struct mpc_config_intsrc *)mpt;
321
322 MP_intsrc_info(m);
323 mpt+=sizeof(*m);
324 count+=sizeof(*m);
325 break;
326 }
327 case MP_LINTSRC:
328 {
329 struct mpc_config_lintsrc *m=
330 (struct mpc_config_lintsrc *)mpt;
331 MP_lintsrc_info(m);
332 mpt+=sizeof(*m);
333 count+=sizeof(*m);
334 break;
335 }
336 }
337 }
338 if (!num_processors)
339 printk(KERN_ERR "SMP mptable: no processors registered!\n");
340 return num_processors;
341 }
342
ELCR_trigger(unsigned int irq)343 static int __init ELCR_trigger(unsigned int irq)
344 {
345 unsigned int port;
346
347 port = 0x4d0 + (irq >> 3);
348 return (inb(port) >> (irq & 7)) & 1;
349 }
350
construct_default_ioirq_mptable(int mpc_default_type)351 static void __init construct_default_ioirq_mptable(int mpc_default_type)
352 {
353 struct mpc_config_intsrc intsrc;
354 int i;
355 int ELCR_fallback = 0;
356
357 intsrc.mpc_type = MP_INTSRC;
358 intsrc.mpc_irqflag = 0; /* conforming */
359 intsrc.mpc_srcbus = 0;
360 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
361
362 intsrc.mpc_irqtype = mp_INT;
363
364 /*
365 * If true, we have an ISA/PCI system with no IRQ entries
366 * in the MP table. To prevent the PCI interrupts from being set up
367 * incorrectly, we try to use the ELCR. The sanity check to see if
368 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
369 * never be level sensitive, so we simply see if the ELCR agrees.
370 * If it does, we assume it's valid.
371 */
372 if (mpc_default_type == 5) {
373 printk("ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
374
375 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
376 printk("ELCR contains invalid data... not using ELCR\n");
377 else {
378 printk("Using ELCR to identify PCI interrupts\n");
379 ELCR_fallback = 1;
380 }
381 }
382
383 for (i = 0; i < 16; i++) {
384 switch (mpc_default_type) {
385 case 2:
386 if (i == 0 || i == 13)
387 continue; /* IRQ0 & IRQ13 not connected */
388 /* fall through */
389 default:
390 if (i == 2)
391 continue; /* IRQ2 is never connected */
392 }
393
394 if (ELCR_fallback) {
395 /*
396 * If the ELCR indicates a level-sensitive interrupt, we
397 * copy that information over to the MP table in the
398 * irqflag field (level sensitive, active high polarity).
399 */
400 if (ELCR_trigger(i))
401 intsrc.mpc_irqflag = 13;
402 else
403 intsrc.mpc_irqflag = 0;
404 }
405
406 intsrc.mpc_srcbusirq = i;
407 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
408 MP_intsrc_info(&intsrc);
409 }
410
411 intsrc.mpc_irqtype = mp_ExtINT;
412 intsrc.mpc_srcbusirq = 0;
413 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
414 MP_intsrc_info(&intsrc);
415 }
416
construct_default_ISA_mptable(int mpc_default_type)417 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
418 {
419 struct mpc_config_processor processor;
420 struct mpc_config_bus bus;
421 struct mpc_config_ioapic ioapic;
422 struct mpc_config_lintsrc lintsrc;
423 int linttypes[2] = { mp_ExtINT, mp_NMI };
424 int i;
425
426 /*
427 * local APIC has default address
428 */
429 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
430
431 /*
432 * 2 CPUs, numbered 0 & 1.
433 */
434 processor.mpc_type = MP_PROCESSOR;
435 /* Either an integrated APIC or a discrete 82489DX. */
436 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
437 processor.mpc_cpuflag = CPU_ENABLED;
438 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
439 (boot_cpu_data.x86_model << 4) |
440 boot_cpu_data.x86_mask;
441 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
442 processor.mpc_reserved[0] = 0;
443 processor.mpc_reserved[1] = 0;
444 for (i = 0; i < 2; i++) {
445 processor.mpc_apicid = i;
446 MP_processor_info(&processor);
447 }
448
449 bus.mpc_type = MP_BUS;
450 bus.mpc_busid = 0;
451 switch (mpc_default_type) {
452 default:
453 printk("???\nUnknown standard configuration %d\n",
454 mpc_default_type);
455 /* fall through */
456 case 1:
457 case 5:
458 memcpy(bus.mpc_bustype, "ISA ", 6);
459 break;
460 case 2:
461 case 6:
462 case 3:
463 memcpy(bus.mpc_bustype, "EISA ", 6);
464 break;
465 case 4:
466 case 7:
467 memcpy(bus.mpc_bustype, "MCA ", 6);
468 }
469 MP_bus_info(&bus);
470 if (mpc_default_type > 4) {
471 bus.mpc_busid = 1;
472 memcpy(bus.mpc_bustype, "PCI ", 6);
473 MP_bus_info(&bus);
474 }
475
476 ioapic.mpc_type = MP_IOAPIC;
477 ioapic.mpc_apicid = 2;
478 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
479 ioapic.mpc_flags = MPC_APIC_USABLE;
480 ioapic.mpc_apicaddr = 0xFEC00000;
481 MP_ioapic_info(&ioapic);
482
483 /*
484 * We set up most of the low 16 IO-APIC pins according to MPS rules.
485 */
486 construct_default_ioirq_mptable(mpc_default_type);
487
488 lintsrc.mpc_type = MP_LINTSRC;
489 lintsrc.mpc_irqflag = 0; /* conforming */
490 lintsrc.mpc_srcbusid = 0;
491 lintsrc.mpc_srcbusirq = 0;
492 lintsrc.mpc_destapic = MP_APIC_ALL;
493 for (i = 0; i < 2; i++) {
494 lintsrc.mpc_irqtype = linttypes[i];
495 lintsrc.mpc_destapiclint = i;
496 MP_lintsrc_info(&lintsrc);
497 }
498 }
499
500 static struct intel_mp_floating *mpf_found;
501
502 /*
503 * Scan the memory blocks for an SMP configuration block.
504 */
get_smp_config(void)505 void __init get_smp_config (void)
506 {
507 struct intel_mp_floating *mpf = mpf_found;
508 /*
509 * ACPI may be used to obtain the entire SMP configuration or just to
510 * enumerate/configure processors (CONFIG_ACPI_HT_ONLY). Note that
511 * ACPI supports both logical (e.g. Hyper-Threading) and physical
512 * processors, where MPS only supports physical.
513 */
514 if (acpi_lapic && acpi_ioapic) {
515 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
516 return;
517 }
518 else if (acpi_lapic)
519 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
520
521 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
522 if (mpf->mpf_feature2 & (1<<7)) {
523 printk(" IMCR and PIC compatibility mode.\n");
524 pic_mode = 1;
525 } else {
526 printk(" Virtual Wire compatibility mode.\n");
527 pic_mode = 0;
528 }
529
530 /*
531 * Now see if we need to read further.
532 */
533 if (mpf->mpf_feature1 != 0) {
534
535 printk("Default MP configuration #%d\n", mpf->mpf_feature1);
536 construct_default_ISA_mptable(mpf->mpf_feature1);
537
538 } else if (mpf->mpf_physptr) {
539 /*
540 * Read the physical hardware table. Anything here will
541 * override the defaults.
542 */
543 if (!smp_read_mpc(__va(mpf->mpf_physptr))) {
544 smp_found_config = 0;
545 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
546 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
547 return;
548 }
549 /*
550 * If there are no explicit MP IRQ entries, then we are
551 * broken. We set up most of the low 16 IO-APIC pins to
552 * ISA defaults and hope it will work.
553 */
554 if (!mp_irq_entries) {
555 struct mpc_config_bus bus;
556
557 printk("BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
558
559 bus.mpc_type = MP_BUS;
560 bus.mpc_busid = 0;
561 memcpy(bus.mpc_bustype, "ISA ", 6);
562 MP_bus_info(&bus);
563
564 construct_default_ioirq_mptable(0);
565 }
566
567 } else
568 BUG();
569
570 printk("Processors: %d\n", num_processors);
571 /*
572 * Only use the first configuration found.
573 */
574 }
575
smp_scan_config(unsigned long base,unsigned long length)576 static int __init smp_scan_config (unsigned long base, unsigned long length)
577 {
578 unsigned int *bp = phys_to_virt(base);
579 struct intel_mp_floating *mpf;
580
581 printk("Scan SMP from %p for %ld bytes.\n", bp,length);
582 if (sizeof(*mpf) != 16)
583 printk("Error: MPF size\n");
584
585 while (length > 0) {
586 mpf = (struct intel_mp_floating *)bp;
587 if ((*bp == SMP_MAGIC_IDENT) &&
588 (mpf->mpf_length == 1) &&
589 !mpf_checksum((unsigned char *)bp, 16) &&
590 ((mpf->mpf_specification == 1)
591 || (mpf->mpf_specification == 4)) ) {
592
593 smp_found_config = 1;
594 printk(KERN_INFO "found SMP MP-table at %016lx\n",
595 virt_to_phys(mpf));
596 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
597 if (mpf->mpf_physptr)
598 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
599 mpf_found = mpf;
600 return 1;
601 }
602 bp += 4;
603 length -= 16;
604 }
605 return 0;
606 }
607
find_intel_smp(void)608 void __init find_intel_smp (void)
609 {
610 unsigned long address;
611
612 /*
613 * FIXME: Linux assumes you have 640K of base ram..
614 * this continues the error...
615 *
616 * 1) Scan the bottom 1K for a signature
617 * 2) Scan the top 1K of base RAM
618 * 3) Scan the 64K of bios
619 */
620 if (smp_scan_config(0x0,0x400) ||
621 smp_scan_config(639*0x400,0x400) ||
622 smp_scan_config(0xF0000,0x10000))
623 return;
624 printk("ok\n");
625
626 /*
627 * If it is an SMP machine we should know now, unless the
628 * configuration is in an EISA/MCA bus machine with an
629 * extended bios data area.
630 *
631 * there is a real-mode segmented pointer pointing to the
632 * 4K EBDA area at 0x40E, calculate and scan it here.
633 *
634 * NOTE! There are Linux loaders that will corrupt the EBDA
635 * area, and as such this kind of SMP config may be less
636 * trustworthy, simply because the SMP table may have been
637 * stomped on during early boot. These loaders are buggy and
638 * should be fixed.
639 *
640 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
641 */
642
643 address = *(unsigned short *)phys_to_virt(0x40E);
644 address <<= 4;
645 smp_scan_config(address, 0x400);
646 if (smp_found_config)
647 printk(KERN_WARNING "WARNING: MP table in the EBDA can be UNSAFE, contact linux-smp@vger.kernel.org if you experience SMP problems!\n");
648 }
649
650 /*
651 * - Intel MP Configuration Table
652 */
find_smp_config(void)653 void __init find_smp_config (void)
654 {
655 #ifdef CONFIG_X86_LOCAL_APIC
656 find_intel_smp();
657 #endif
658 }
659
660
661 /* --------------------------------------------------------------------------
662 ACPI-based MP Configuration
663 -------------------------------------------------------------------------- */
664
665 #ifdef CONFIG_ACPI_BOOT
666
mp_register_lapic_address(u64 address)667 void __init mp_register_lapic_address (
668 u64 address)
669 {
670 mp_lapic_addr = (unsigned long) address;
671
672 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
673
674 if (boot_cpu_id == -1U)
675 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
676
677 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
678 }
679
680
mp_register_lapic(u8 id,u8 enabled)681 void __init mp_register_lapic (
682 u8 id,
683 u8 enabled)
684 {
685 struct mpc_config_processor processor;
686 int boot_cpu = 0;
687
688 if (id >= MAX_APICS) {
689 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
690 id, MAX_APICS);
691 return;
692 }
693
694 if (id == boot_cpu_physical_apicid)
695 boot_cpu = 1;
696
697 processor.mpc_type = MP_PROCESSOR;
698 processor.mpc_apicid = id;
699 processor.mpc_apicver = 0x10; /* TBD: lapic version */
700 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
701 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
702 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
703 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
704 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
705 processor.mpc_reserved[0] = 0;
706 processor.mpc_reserved[1] = 0;
707
708 MP_processor_info(&processor);
709 }
710
711 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_ACPI_INTERPRETER)
712
713 #define MP_ISA_BUS 0
714 #define MP_MAX_IOAPIC_PIN 127
715
716 struct mp_ioapic_routing {
717 int apic_id;
718 int irq_start;
719 int irq_end;
720 u32 pin_programmed[4];
721 } mp_ioapic_routing[MAX_IO_APICS];
722
723
mp_find_ioapic(int irq)724 static int __init mp_find_ioapic (
725 int irq)
726 {
727 int i = 0;
728
729 /* Find the IOAPIC that manages this IRQ. */
730 for (i = 0; i < nr_ioapics; i++) {
731 if ((irq >= mp_ioapic_routing[i].irq_start)
732 && (irq <= mp_ioapic_routing[i].irq_end))
733 return i;
734 }
735
736 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for IRQ %d\n", irq);
737
738 return -1;
739 }
740
741
mp_register_ioapic(u8 id,u32 address,u32 irq_base)742 void __init mp_register_ioapic (
743 u8 id,
744 u32 address,
745 u32 irq_base)
746 {
747 int idx = 0;
748
749 if (nr_ioapics >= MAX_IO_APICS) {
750 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
751 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
752 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
753 }
754 if (!address) {
755 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
756 " found in MADT table, skipping!\n");
757 return;
758 }
759
760 idx = nr_ioapics++;
761
762 mp_ioapics[idx].mpc_type = MP_IOAPIC;
763 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
764 mp_ioapics[idx].mpc_apicaddr = address;
765
766 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
767 mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
768 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
769
770 /*
771 * Build basic IRQ lookup table to facilitate irq->io_apic lookups
772 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
773 */
774 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
775 mp_ioapic_routing[idx].irq_start = irq_base;
776 mp_ioapic_routing[idx].irq_end = irq_base +
777 io_apic_get_redir_entries(idx);
778
779 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
780 "IRQ %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
781 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
782 mp_ioapic_routing[idx].irq_start,
783 mp_ioapic_routing[idx].irq_end);
784
785 return;
786 }
787
788
mp_override_legacy_irq(u8 bus_irq,u8 polarity,u8 trigger,u32 global_irq)789 void __init mp_override_legacy_irq (
790 u8 bus_irq,
791 u8 polarity,
792 u8 trigger,
793 u32 global_irq)
794 {
795 struct mpc_config_intsrc intsrc;
796 int ioapic = -1;
797 int pin = -1;
798
799 /*
800 * Convert 'global_irq' to 'ioapic.pin'.
801 */
802 ioapic = mp_find_ioapic(global_irq);
803 if (ioapic < 0)
804 return;
805 pin = global_irq - mp_ioapic_routing[ioapic].irq_start;
806
807 /*
808 * TBD: This check is for faulty timer entries, where the override
809 * erroneously sets the trigger to level, resulting in a HUGE
810 * increase of timer interrupts!
811 */
812 if ((bus_irq == 0) && (trigger == 3))
813 trigger = 1;
814
815 intsrc.mpc_type = MP_INTSRC;
816 intsrc.mpc_irqtype = mp_INT;
817 intsrc.mpc_irqflag = (trigger << 2) | polarity;
818 intsrc.mpc_srcbus = MP_ISA_BUS;
819 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
820 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
821 intsrc.mpc_dstirq = pin; /* INTIN# */
822
823 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
824 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
825 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
826 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
827
828 mp_irqs[mp_irq_entries] = intsrc;
829 if (++mp_irq_entries == MAX_IRQ_SOURCES)
830 panic("Max # of irq sources exceeded!\n");
831
832 return;
833 }
834
835
mp_config_acpi_legacy_irqs(void)836 void __init mp_config_acpi_legacy_irqs (void)
837 {
838 struct mpc_config_intsrc intsrc;
839 int i = 0;
840 int ioapic = -1;
841
842 /*
843 * Fabricate the legacy ISA bus (bus #31).
844 */
845 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
846 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
847
848 /*
849 * Locate the IOAPIC that manages the ISA IRQs (0-15).
850 */
851 ioapic = mp_find_ioapic(0);
852 if (ioapic < 0)
853 return;
854
855 intsrc.mpc_type = MP_INTSRC;
856 intsrc.mpc_irqflag = 0; /* Conforming */
857 intsrc.mpc_srcbus = MP_ISA_BUS;
858 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
859
860 /*
861 * Use the default configuration for the IRQs 0-15. Unless
862 * overriden by (MADT) interrupt source override entries.
863 */
864 for (i = 0; i < 16; i++) {
865 int idx;
866
867 for (idx = 0; idx < mp_irq_entries; idx++)
868 if (mp_irqs[idx].mpc_srcbus == MP_ISA_BUS &&
869 (mp_irqs[idx].mpc_dstapic == intsrc.mpc_dstapic) &&
870 (mp_irqs[idx].mpc_srcbusirq == i ||
871 mp_irqs[idx].mpc_dstirq == i))
872 break;
873
874 if (idx != mp_irq_entries) {
875 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
876 continue; /* IRQ already used */
877 }
878
879 intsrc.mpc_irqtype = mp_INT;
880 intsrc.mpc_srcbusirq = i; /* Identity mapped */
881 intsrc.mpc_dstirq = i;
882
883 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
884 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
885 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
886 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
887 intsrc.mpc_dstirq);
888
889 mp_irqs[mp_irq_entries] = intsrc;
890 if (++mp_irq_entries == MAX_IRQ_SOURCES)
891 panic("Max # of irq sources exceeded!\n");
892 }
893
894 return;
895 }
896
897
898
899 #ifndef CONFIG_ACPI_HT_ONLY
900
901 extern FADT_DESCRIPTOR acpi_fadt;
902
903 #endif /*CONFIG_ACPI_HT_ONLY*/
904
905 int acpi_tolerant;
906
907 #ifdef CONFIG_ACPI_PCI
908
mp_parse_prt(void)909 void __init mp_parse_prt (void)
910 {
911 struct list_head *node = NULL;
912 struct acpi_prt_entry *entry = NULL;
913 int vector = 0;
914 int ioapic = -1;
915 int ioapic_pin = 0;
916 int irq = 0;
917 int idx, bit = 0;
918 int edge_level = 0;
919 int active_high_low = 0;
920
921 /*
922 * Parsing through the PCI Interrupt Routing Table (PRT) and program
923 * routing for all static (IOAPIC-direct) entries.
924 */
925 list_for_each(node, &acpi_prt.entries) {
926 entry = list_entry(node, struct acpi_prt_entry, node);
927
928 /* Need to get irq for dynamic entry */
929 if (entry->link.handle) {
930 irq = acpi_pci_link_get_irq(entry->link.handle, entry->link.index, &edge_level, &active_high_low);
931 if (!irq)
932 continue;
933 } else {
934 edge_level = 1;
935 active_high_low = 1;
936 irq = entry->link.index;
937 }
938
939 /* Don't set up the ACPI SCI because it's already set up */
940 if (acpi_fadt.sci_int == irq) {
941 entry->irq = irq; /*we still need to set entry's irq*/
942 continue;
943 }
944
945 ioapic = mp_find_ioapic(irq);
946 if (ioapic < 0)
947 continue;
948 ioapic_pin = irq - mp_ioapic_routing[ioapic].irq_start;
949
950 /*
951 * Avoid pin reprogramming. PRTs typically include entries
952 * with redundant pin->irq mappings (but unique PCI devices);
953 * we only only program the IOAPIC on the first.
954 */
955 bit = ioapic_pin % 32;
956 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
957 if (idx > 3) {
958 printk(KERN_ERR "Invalid reference to IOAPIC pin "
959 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
960 ioapic_pin);
961 continue;
962 }
963 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
964 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
965 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
966 entry->irq = irq;
967 continue;
968 }
969
970 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
971
972 vector = io_apic_set_pci_routing(ioapic, ioapic_pin, irq, edge_level, active_high_low);
973 if (vector)
974 entry->irq = irq;
975
976 printk(KERN_DEBUG "%02x:%02x:%02x[%c] -> %d-%d -> vector 0x%02x"
977 " -> IRQ %d %s %s\n", entry->id.segment, entry->id.bus,
978 entry->id.device, ('A' + entry->pin),
979 mp_ioapic_routing[ioapic].apic_id, ioapic_pin, vector,
980 entry->irq, edge_level ? "level" : "edge",
981 active_high_low ? "low" : "high");
982 }
983
984 print_IO_APIC();
985
986 return;
987 }
988
989 #endif /*CONFIG_ACPI_PCI*/
990
991 #endif /*CONFIG_X86_IO_APIC && CONFIG_ACPI_INTERPRETER*/
992
993 #endif /*CONFIG_ACPI_BOOT*/
994