1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/acpi.h>
33
34 #include <asm/io.h>
35 #include <asm/smp.h>
36 #include <asm/desc.h>
37
38 #undef APIC_LOCKUP_DEBUG
39
40 #define APIC_LOCKUP_DEBUG
41
42 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
43
44 /*
45 * # of IRQ routing registers
46 */
47 int nr_ioapic_registers[MAX_IO_APICS];
48
49 /*
50 * Rough estimation of how many shared IRQs there are, can
51 * be changed anytime.
52 */
53 #define MAX_PLUS_SHARED_IRQS NR_IRQS
54 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
55
56 /*
57 * This is performance-critical, we want to do it O(1)
58 *
59 * the indexing order of this array favors 1:1 mappings
60 * between pins and IRQs.
61 */
62
63 static struct irq_pin_list {
64 int apic, pin, next;
65 } irq_2_pin[PIN_MAP_SIZE];
66
67 /*
68 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
69 * shared ISA-space IRQs, so we have to support them. We are super
70 * fast in the common case, and fast for shared ISA-space IRQs.
71 */
add_pin_to_irq(unsigned int irq,int apic,int pin)72 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
73 {
74 static int first_free_entry = NR_IRQS;
75 struct irq_pin_list *entry = irq_2_pin + irq;
76
77 while (entry->next)
78 entry = irq_2_pin + entry->next;
79
80 if (entry->pin != -1) {
81 entry->next = first_free_entry;
82 entry = irq_2_pin + entry->next;
83 if (++first_free_entry >= PIN_MAP_SIZE)
84 panic("io_apic.c: whoops");
85 }
86 entry->apic = apic;
87 entry->pin = pin;
88 }
89
90 /*
91 * Reroute an IRQ to a different pin.
92 */
replace_pin_at_irq(unsigned int irq,int oldapic,int oldpin,int newapic,int newpin)93 static void __init replace_pin_at_irq(unsigned int irq,
94 int oldapic, int oldpin,
95 int newapic, int newpin)
96 {
97 struct irq_pin_list *entry = irq_2_pin + irq;
98
99 while (1) {
100 if (entry->apic == oldapic && entry->pin == oldpin) {
101 entry->apic = newapic;
102 entry->pin = newpin;
103 }
104 if (!entry->next)
105 break;
106 entry = irq_2_pin + entry->next;
107 }
108 }
109
110 #define __DO_ACTION(R, ACTION, FINAL) \
111 \
112 { \
113 int pin; \
114 struct irq_pin_list *entry = irq_2_pin + irq; \
115 \
116 for (;;) { \
117 unsigned int reg; \
118 pin = entry->pin; \
119 if (pin == -1) \
120 break; \
121 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
122 reg ACTION; \
123 io_apic_modify(entry->apic, reg); \
124 if (!entry->next) \
125 break; \
126 entry = irq_2_pin + entry->next; \
127 } \
128 FINAL; \
129 }
130
131 #define DO_ACTION(name,R,ACTION, FINAL) \
132 \
133 static void name##_IO_APIC_irq (unsigned int irq) \
134 __DO_ACTION(R, ACTION, FINAL)
135
136 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
137 /* mask = 1 */
138 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
139 /* mask = 0 */
140 DO_ACTION( __mask_and_edge, 0, = (reg & 0xffff7fff) | 0x00010000, )
141 /* mask = 1, trigger = 0 */
142 DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, )
143 /* mask = 0, trigger = 1 */
144
mask_IO_APIC_irq(unsigned int irq)145 static void mask_IO_APIC_irq (unsigned int irq)
146 {
147 unsigned long flags;
148
149 spin_lock_irqsave(&ioapic_lock, flags);
150 __mask_IO_APIC_irq(irq);
151 spin_unlock_irqrestore(&ioapic_lock, flags);
152 }
153
unmask_IO_APIC_irq(unsigned int irq)154 static void unmask_IO_APIC_irq (unsigned int irq)
155 {
156 unsigned long flags;
157
158 spin_lock_irqsave(&ioapic_lock, flags);
159 __unmask_IO_APIC_irq(irq);
160 spin_unlock_irqrestore(&ioapic_lock, flags);
161 }
162
clear_IO_APIC_pin(unsigned int apic,unsigned int pin)163 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
164 {
165 struct IO_APIC_route_entry entry;
166 unsigned long flags;
167
168 /* Check delivery_mode to be sure we're not clearing an SMI pin */
169 spin_lock_irqsave(&ioapic_lock, flags);
170 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
171 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
172 spin_unlock_irqrestore(&ioapic_lock, flags);
173 if (entry.delivery_mode == dest_SMI)
174 return;
175
176 /*
177 * Disable it in the IO-APIC irq-routing table:
178 */
179 memset(&entry, 0, sizeof(entry));
180 entry.mask = 1;
181 spin_lock_irqsave(&ioapic_lock, flags);
182 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
183 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
184 spin_unlock_irqrestore(&ioapic_lock, flags);
185 }
186
clear_IO_APIC(void)187 static void clear_IO_APIC (void)
188 {
189 int apic, pin;
190
191 for (apic = 0; apic < nr_ioapics; apic++)
192 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
193 clear_IO_APIC_pin(apic, pin);
194 }
195
196 /*
197 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
198 * specific CPU-side IRQs.
199 */
200
201 #define MAX_PIRQS 8
202 int pirq_entries [MAX_PIRQS];
203 int pirqs_enabled;
204 int skip_ioapic_setup;
205 int ioapic_force;
206
noioapic_setup(char * str)207 static int __init noioapic_setup(char *str)
208 {
209 ioapic_force = 1;
210 skip_ioapic_setup = 1;
211 return 1;
212 }
213
214 __setup("noapic", noioapic_setup);
215
ioapic_setup(char * str)216 static int __init ioapic_setup(char *str)
217 {
218 ioapic_force = 1;
219 skip_ioapic_setup = 0;
220 return 1;
221 }
222
223 __setup("apic", ioapic_setup);
224
225 #include <asm/pci-direct.h>
226 #include <linux/pci_ids.h>
227 #include <linux/pci.h>
228
229 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
230 off. Check for an Nvidia or VIA PCI bridge and turn it off.
231 Use pci direct infrastructure because this runs before the PCI subsystem.
232
233 Can be overwritten with "apic" */
check_ioapic(void)234 void __init check_ioapic(void)
235 {
236 int num,slot,func;
237 if (ioapic_force)
238 return;
239
240 /* Poor man's PCI discovery */
241 for (num = 0; num < 32; num++) {
242 for (slot = 0; slot < 32; slot++) {
243 for (func = 0; func < 8; func++) {
244 u32 class;
245 u32 vendor;
246 class = read_pci_config(num,slot,func,
247 PCI_CLASS_REVISION);
248 if (class == 0xffffffff)
249 break;
250
251 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
252 continue;
253
254 vendor = read_pci_config(num, slot, func,
255 PCI_VENDOR_ID);
256 vendor &= 0xffff;
257 switch (vendor) {
258 case PCI_VENDOR_ID_VIA:
259 return;
260 case PCI_VENDOR_ID_NVIDIA:
261 #ifdef CONFIG_ACPI
262 /* All timer overrides on Nvidia
263 seem to be wrong. Skip them. */
264 acpi_skip_timer_override = 1;
265 printk(KERN_INFO
266 "Nvidia board detected. Ignoring ACPI timer override.\n");
267 #endif
268 /* RED-PEN skip them on mptables too? */
269 return;
270 }
271
272 /* No multi-function device? */
273 u8 type = read_pci_config_byte(num,slot,func,
274 PCI_HEADER_TYPE);
275 if (!(type & 0x80))
276 break;
277 }
278 }
279 }
280 }
281
ioapic_pirq_setup(char * str)282 static int __init ioapic_pirq_setup(char *str)
283 {
284 int i, max;
285 int ints[MAX_PIRQS+1];
286
287 get_options(str, ARRAY_SIZE(ints), ints);
288
289 for (i = 0; i < MAX_PIRQS; i++)
290 pirq_entries[i] = -1;
291
292 pirqs_enabled = 1;
293 printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
294 max = MAX_PIRQS;
295 if (ints[0] < MAX_PIRQS)
296 max = ints[0];
297
298 for (i = 0; i < max; i++) {
299 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
300 /*
301 * PIRQs are mapped upside down, usually.
302 */
303 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
304 }
305 return 1;
306 }
307
308 __setup("pirq=", ioapic_pirq_setup);
309
310 /*
311 * Find the IRQ entry number of a certain pin.
312 */
find_irq_entry(int apic,int pin,int type)313 static int __init find_irq_entry(int apic, int pin, int type)
314 {
315 int i;
316
317 for (i = 0; i < mp_irq_entries; i++)
318 if (mp_irqs[i].mpc_irqtype == type &&
319 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
320 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
321 mp_irqs[i].mpc_dstirq == pin)
322 return i;
323
324 return -1;
325 }
326
327 /*
328 * Find the pin to which IRQ[irq] (ISA) is connected
329 */
find_isa_irq_pin(int irq,int type)330 static int __init find_isa_irq_pin(int irq, int type)
331 {
332 int i;
333
334 for (i = 0; i < mp_irq_entries; i++) {
335 int lbus = mp_irqs[i].mpc_srcbus;
336
337 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
338 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
339 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
340 (mp_irqs[i].mpc_irqtype == type) &&
341 (mp_irqs[i].mpc_srcbusirq == irq))
342
343 return mp_irqs[i].mpc_dstirq;
344 }
345 return -1;
346 }
347
348 /*
349 * Find a specific PCI IRQ entry.
350 * Not an __init, possibly needed by modules
351 */
352 static int pin_2_irq(int idx, int apic, int pin);
353
IO_APIC_get_PCI_irq_vector(int bus,int slot,int pin)354 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
355 {
356 int apic, i, best_guess = -1;
357
358 Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
359 bus, slot, pin);
360 if (mp_bus_id_to_pci_bus[bus] == -1) {
361 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
362 return -1;
363 }
364 for (i = 0; i < mp_irq_entries; i++) {
365 int lbus = mp_irqs[i].mpc_srcbus;
366
367 for (apic = 0; apic < nr_ioapics; apic++)
368 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
369 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
370 break;
371
372 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
373 !mp_irqs[i].mpc_irqtype &&
374 (bus == lbus) &&
375 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
376 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
377
378 if (!(apic || IO_APIC_IRQ(irq)))
379 continue;
380
381 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
382 return irq;
383 /*
384 * Use the first all-but-pin matching entry as a
385 * best-guess fuzzy result for broken mptables.
386 */
387 if (best_guess < 0)
388 best_guess = irq;
389 }
390 }
391 return best_guess;
392 }
393
394 /*
395 * EISA Edge/Level control register, ELCR
396 */
EISA_ELCR(unsigned int irq)397 static int __init EISA_ELCR(unsigned int irq)
398 {
399 if (irq < 16) {
400 unsigned int port = 0x4d0 + (irq >> 3);
401 return (inb(port) >> (irq & 7)) & 1;
402 }
403 printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
404 return 0;
405 }
406
407 /* EISA interrupts are always polarity zero and can be edge or level
408 * trigger depending on the ELCR value. If an interrupt is listed as
409 * EISA conforming in the MP table, that means its trigger type must
410 * be read in from the ELCR */
411
412 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
413 #define default_EISA_polarity(idx) (0)
414
415 /* ISA interrupts are always polarity zero edge triggered,
416 * when listed as conforming in the MP table. */
417
418 #define default_ISA_trigger(idx) (0)
419 #define default_ISA_polarity(idx) (0)
420
421 /* PCI interrupts are always polarity one level triggered,
422 * when listed as conforming in the MP table. */
423
424 #define default_PCI_trigger(idx) (1)
425 #define default_PCI_polarity(idx) (1)
426
427 /* MCA interrupts are always polarity zero level triggered,
428 * when listed as conforming in the MP table. */
429
430 #define default_MCA_trigger(idx) (1)
431 #define default_MCA_polarity(idx) (0)
432
MPBIOS_polarity(int idx)433 static int __init MPBIOS_polarity(int idx)
434 {
435 int bus = mp_irqs[idx].mpc_srcbus;
436 int polarity;
437
438 /*
439 * Determine IRQ line polarity (high active or low active):
440 */
441 switch (mp_irqs[idx].mpc_irqflag & 3)
442 {
443 case 0: /* conforms, ie. bus-type dependent polarity */
444 {
445 switch (mp_bus_id_to_type[bus])
446 {
447 case MP_BUS_ISA: /* ISA pin */
448 {
449 polarity = default_ISA_polarity(idx);
450 break;
451 }
452 case MP_BUS_EISA: /* EISA pin */
453 {
454 polarity = default_EISA_polarity(idx);
455 break;
456 }
457 case MP_BUS_PCI: /* PCI pin */
458 {
459 polarity = default_PCI_polarity(idx);
460 break;
461 }
462 case MP_BUS_MCA: /* MCA pin */
463 {
464 polarity = default_MCA_polarity(idx);
465 break;
466 }
467 default:
468 {
469 printk(KERN_WARNING "broken BIOS!!\n");
470 polarity = 1;
471 break;
472 }
473 }
474 break;
475 }
476 case 1: /* high active */
477 {
478 polarity = 0;
479 break;
480 }
481 case 2: /* reserved */
482 {
483 printk(KERN_WARNING "broken BIOS!!\n");
484 polarity = 1;
485 break;
486 }
487 case 3: /* low active */
488 {
489 polarity = 1;
490 break;
491 }
492 default: /* invalid */
493 {
494 printk(KERN_WARNING "broken BIOS!!\n");
495 polarity = 1;
496 break;
497 }
498 }
499 return polarity;
500 }
501
MPBIOS_trigger(int idx)502 static int __init MPBIOS_trigger(int idx)
503 {
504 int bus = mp_irqs[idx].mpc_srcbus;
505 int trigger;
506
507 /*
508 * Determine IRQ trigger mode (edge or level sensitive):
509 */
510 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
511 {
512 case 0: /* conforms, ie. bus-type dependent */
513 {
514 switch (mp_bus_id_to_type[bus])
515 {
516 case MP_BUS_ISA: /* ISA pin */
517 {
518 trigger = default_ISA_trigger(idx);
519 break;
520 }
521 case MP_BUS_EISA: /* EISA pin */
522 {
523 trigger = default_EISA_trigger(idx);
524 break;
525 }
526 case MP_BUS_PCI: /* PCI pin */
527 {
528 trigger = default_PCI_trigger(idx);
529 break;
530 }
531 case MP_BUS_MCA: /* MCA pin */
532 {
533 trigger = default_MCA_trigger(idx);
534 break;
535 }
536 default:
537 {
538 printk(KERN_WARNING "broken BIOS!!\n");
539 trigger = 1;
540 break;
541 }
542 }
543 break;
544 }
545 case 1: /* edge */
546 {
547 trigger = 0;
548 break;
549 }
550 case 2: /* reserved */
551 {
552 printk(KERN_WARNING "broken BIOS!!\n");
553 trigger = 1;
554 break;
555 }
556 case 3: /* level */
557 {
558 trigger = 1;
559 break;
560 }
561 default: /* invalid */
562 {
563 printk(KERN_WARNING "broken BIOS!!\n");
564 trigger = 0;
565 break;
566 }
567 }
568 return trigger;
569 }
570
irq_polarity(int idx)571 static inline int irq_polarity(int idx)
572 {
573 return MPBIOS_polarity(idx);
574 }
575
irq_trigger(int idx)576 static inline int irq_trigger(int idx)
577 {
578 return MPBIOS_trigger(idx);
579 }
580
pin_2_irq(int idx,int apic,int pin)581 static int pin_2_irq(int idx, int apic, int pin)
582 {
583 int irq, i;
584 int bus = mp_irqs[idx].mpc_srcbus;
585
586 /*
587 * Debugging check, we are in big trouble if this message pops up!
588 */
589 if (mp_irqs[idx].mpc_dstirq != pin)
590 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
591
592 switch (mp_bus_id_to_type[bus])
593 {
594 case MP_BUS_ISA: /* ISA pin */
595 case MP_BUS_EISA:
596 case MP_BUS_MCA:
597 {
598 irq = mp_irqs[idx].mpc_srcbusirq;
599 break;
600 }
601 case MP_BUS_PCI: /* PCI pin */
602 {
603 /*
604 * PCI IRQs are mapped in order
605 */
606 i = irq = 0;
607 while (i < apic)
608 irq += nr_ioapic_registers[i++];
609 irq += pin;
610 break;
611 }
612 default:
613 {
614 printk(KERN_ERR "unknown bus type %d.\n",bus);
615 irq = 0;
616 break;
617 }
618 }
619
620 /*
621 * PCI IRQ command line redirection. Yes, limits are hardcoded.
622 */
623 if ((pin >= 16) && (pin <= 23)) {
624 if (pirq_entries[pin-16] != -1) {
625 if (!pirq_entries[pin-16]) {
626 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
627 } else {
628 irq = pirq_entries[pin-16];
629 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
630 pin-16, irq);
631 }
632 }
633 }
634 return irq;
635 }
636
IO_APIC_irq_trigger(int irq)637 static inline int IO_APIC_irq_trigger(int irq)
638 {
639 int apic, idx, pin;
640
641 for (apic = 0; apic < nr_ioapics; apic++) {
642 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
643 idx = find_irq_entry(apic,pin,mp_INT);
644 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
645 return irq_trigger(idx);
646 }
647 }
648 /*
649 * nonexistent IRQs are edge default
650 */
651 return 0;
652 }
653
654 int irq_vector[NR_IRQS] = { FIRST_DEVICE_VECTOR , 0 };
655
assign_irq_vector(int irq)656 static int __init assign_irq_vector(int irq)
657 {
658 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
659 if (IO_APIC_VECTOR(irq) > 0)
660 return IO_APIC_VECTOR(irq);
661 next:
662 current_vector += 8;
663 if (current_vector == IA32_SYSCALL_VECTOR)
664 goto next;
665
666 if (current_vector > FIRST_SYSTEM_VECTOR) {
667 offset++;
668 current_vector = FIRST_DEVICE_VECTOR + offset;
669 }
670
671 if (current_vector == FIRST_SYSTEM_VECTOR)
672 panic("ran out of interrupt sources!");
673
674 IO_APIC_VECTOR(irq) = current_vector;
675 return current_vector;
676 }
677
678 extern void (*interrupt[NR_IRQS])(void);
679 static struct hw_interrupt_type ioapic_level_irq_type;
680 static struct hw_interrupt_type ioapic_edge_irq_type;
681
setup_IO_APIC_irqs(void)682 void __init setup_IO_APIC_irqs(void)
683 {
684 struct IO_APIC_route_entry entry;
685 int apic, pin, idx, irq, first_notcon = 1, vector;
686 unsigned long flags;
687
688 printk(KERN_DEBUG "init IO_APIC IRQs\n");
689
690 for (apic = 0; apic < nr_ioapics; apic++) {
691 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
692
693 /*
694 * add it to the IO-APIC irq-routing table:
695 */
696 memset(&entry,0,sizeof(entry));
697
698 entry.delivery_mode = dest_LowestPrio;
699 entry.dest_mode = INT_DELIVERY_MODE;
700 entry.mask = 0; /* enable IRQ */
701 entry.dest.logical.logical_dest = TARGET_CPUS;
702
703 idx = find_irq_entry(apic,pin,mp_INT);
704 if (idx == -1) {
705 if (first_notcon) {
706 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
707 first_notcon = 0;
708 } else
709 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
710 continue;
711 }
712
713 entry.trigger = irq_trigger(idx);
714 entry.polarity = irq_polarity(idx);
715
716 if (irq_trigger(idx)) {
717 entry.trigger = 1;
718 entry.mask = 1;
719 entry.dest.logical.logical_dest = TARGET_CPUS;
720 }
721
722 irq = pin_2_irq(idx, apic, pin);
723 add_pin_to_irq(irq, apic, pin);
724
725 if (!apic && !IO_APIC_IRQ(irq))
726 continue;
727
728 if (IO_APIC_IRQ(irq)) {
729 vector = assign_irq_vector(irq);
730 entry.vector = vector;
731
732 if (IO_APIC_irq_trigger(irq))
733 irq_desc[irq].handler = &ioapic_level_irq_type;
734 else
735 irq_desc[irq].handler = &ioapic_edge_irq_type;
736
737 set_intr_gate(vector, interrupt[irq]);
738
739 if (!apic && (irq < 16))
740 disable_8259A_irq(irq);
741 }
742 spin_lock_irqsave(&ioapic_lock, flags);
743 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
744 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
745 spin_unlock_irqrestore(&ioapic_lock, flags);
746 }
747 }
748
749 if (!first_notcon)
750 printk(" not connected.\n");
751 }
752
753 /*
754 * Set up the 8259A-master output pin as broadcast to all
755 * CPUs.
756 */
setup_ExtINT_IRQ0_pin(unsigned int pin,int vector)757 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
758 {
759 struct IO_APIC_route_entry entry;
760 unsigned long flags;
761
762 memset(&entry,0,sizeof(entry));
763
764 disable_8259A_irq(0);
765
766 /* mask LVT0 */
767 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
768
769 /*
770 * We use logical delivery to get the timer IRQ
771 * to the first CPU.
772 */
773 entry.dest_mode = INT_DELIVERY_MODE;
774 entry.mask = 0; /* unmask IRQ now */
775 entry.dest.logical.logical_dest = TARGET_CPUS;
776 entry.delivery_mode = dest_LowestPrio;
777 entry.polarity = 0;
778 entry.trigger = 0;
779 entry.vector = vector;
780
781 /*
782 * The timer IRQ doesn't have to know that behind the
783 * scene we have a 8259A-master in AEOI mode ...
784 */
785 irq_desc[0].handler = &ioapic_edge_irq_type;
786
787 /*
788 * Add it to the IO-APIC irq-routing table:
789 */
790 spin_lock_irqsave(&ioapic_lock, flags);
791 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
792 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
793 spin_unlock_irqrestore(&ioapic_lock, flags);
794
795 enable_8259A_irq(0);
796 }
797
UNEXPECTED_IO_APIC(void)798 void __init UNEXPECTED_IO_APIC(void)
799 {
800 #if 0
801 printk(KERN_WARNING " WARNING: unexpected IO-APIC, please mail\n");
802 printk(KERN_WARNING " to linux-smp@vger.kernel.org\n");
803 #endif
804 }
805
print_IO_APIC(void)806 void __init print_IO_APIC(void)
807 {
808 int apic, i;
809 struct IO_APIC_reg_00 reg_00;
810 struct IO_APIC_reg_01 reg_01;
811 struct IO_APIC_reg_02 reg_02;
812 unsigned long flags;
813
814 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
815 for (i = 0; i < nr_ioapics; i++)
816 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
817 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
818
819 /*
820 * We are a bit conservative about what we expect. We have to
821 * know about every hardware change ASAP.
822 */
823 printk(KERN_INFO "testing the IO APIC.......................\n");
824
825 for (apic = 0; apic < nr_ioapics; apic++) {
826
827 spin_lock_irqsave(&ioapic_lock, flags);
828 *(int *)®_00 = io_apic_read(apic, 0);
829 *(int *)®_01 = io_apic_read(apic, 1);
830 if (reg_01.version >= 0x10)
831 *(int *)®_02 = io_apic_read(apic, 2);
832 spin_unlock_irqrestore(&ioapic_lock, flags);
833
834 printk("\n");
835 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
836 printk(KERN_DEBUG ".... register #00: %08X\n", *(int *)®_00);
837 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.ID);
838 if (reg_00.__reserved_1 || reg_00.__reserved_2)
839 UNEXPECTED_IO_APIC();
840
841 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
842 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.entries);
843 if ( (reg_01.entries != 0x0f) && /* older (Neptune) boards */
844 (reg_01.entries != 0x17) && /* typical ISA+PCI boards */
845 (reg_01.entries != 0x1b) && /* Compaq Proliant boards */
846 (reg_01.entries != 0x1f) && /* dual Xeon boards */
847 (reg_01.entries != 0x22) && /* bigger Xeon boards */
848 (reg_01.entries != 0x2E) &&
849 (reg_01.entries != 0x3F) &&
850 (reg_01.entries != 0x03) /* Golem */
851 )
852 UNEXPECTED_IO_APIC();
853
854 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.PRQ);
855 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.version);
856 if ( (reg_01.version != 0x01) && /* 82489DX IO-APICs */
857 (reg_01.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
858 (reg_01.version != 0x10) && /* oldest IO-APICs */
859 (reg_01.version != 0x11) && /* Pentium/Pro IO-APICs / GOLEM */
860 (reg_01.version != 0x13) && /* Xeon IO-APICs */
861 (reg_01.version != 0x20) /* Intel P64H (82806 AA) */
862 )
863 UNEXPECTED_IO_APIC();
864 if (reg_01.__reserved_1 || reg_01.__reserved_2)
865 UNEXPECTED_IO_APIC();
866
867 if (reg_01.version >= 0x10) {
868 printk(KERN_DEBUG ".... register #02: %08X\n", *(int *)®_02);
869 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.arbitration);
870 if (reg_02.__reserved_1 || reg_02.__reserved_2)
871 UNEXPECTED_IO_APIC();
872 }
873
874 printk(KERN_DEBUG ".... IRQ redirection table:\n");
875
876 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
877 " Stat Dest Deli Vect: \n");
878
879 for (i = 0; i <= reg_01.entries; i++) {
880 struct IO_APIC_route_entry entry;
881
882 spin_lock_irqsave(&ioapic_lock, flags);
883 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
884 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
885 spin_unlock_irqrestore(&ioapic_lock, flags);
886
887 printk(KERN_DEBUG " %02x %03X %02X ",
888 i,
889 entry.dest.logical.logical_dest,
890 entry.dest.physical.physical_dest
891 );
892
893 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
894 entry.mask,
895 entry.trigger,
896 entry.irr,
897 entry.polarity,
898 entry.delivery_status,
899 entry.dest_mode,
900 entry.delivery_mode,
901 entry.vector
902 );
903 }
904 }
905 printk(KERN_DEBUG "IRQ to pin mappings:\n");
906 for (i = 0; i < NR_IRQS; i++) {
907 struct irq_pin_list *entry = irq_2_pin + i;
908 if (entry->pin < 0)
909 continue;
910 printk(KERN_DEBUG "IRQ%d ", i);
911 for (;;) {
912 printk("-> %d:%d", entry->apic, entry->pin);
913 if (!entry->next)
914 break;
915 entry = irq_2_pin + entry->next;
916 }
917 printk("\n");
918 }
919
920 printk(KERN_INFO ".................................... done.\n");
921
922 return;
923 }
924
print_APIC_bitfield(int base)925 static void print_APIC_bitfield (int base)
926 {
927 unsigned int v;
928 int i, j;
929
930 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
931 for (i = 0; i < 8; i++) {
932 v = apic_read(base + i*0x10);
933 for (j = 0; j < 32; j++) {
934 if (v & (1<<j))
935 printk("1");
936 else
937 printk("0");
938 }
939 printk("\n");
940 }
941 }
942
print_local_APIC(void * dummy)943 void /*__init*/ print_local_APIC(void * dummy)
944 {
945 unsigned int v, ver, maxlvt;
946
947 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
948 smp_processor_id(), hard_smp_processor_id());
949 v = apic_read(APIC_ID);
950 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
951 v = apic_read(APIC_LVR);
952 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
953 ver = GET_APIC_VERSION(v);
954 maxlvt = get_maxlvt();
955
956 v = apic_read(APIC_TASKPRI);
957 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
958
959 if (APIC_INTEGRATED(ver)) { /* !82489DX */
960 v = apic_read(APIC_ARBPRI);
961 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
962 v & APIC_ARBPRI_MASK);
963 v = apic_read(APIC_PROCPRI);
964 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
965 }
966
967 v = apic_read(APIC_EOI);
968 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
969 v = apic_read(APIC_RRR);
970 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
971 v = apic_read(APIC_LDR);
972 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
973 v = apic_read(APIC_DFR);
974 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
975 v = apic_read(APIC_SPIV);
976 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
977
978 printk(KERN_DEBUG "... APIC ISR field:\n");
979 print_APIC_bitfield(APIC_ISR);
980 printk(KERN_DEBUG "... APIC TMR field:\n");
981 print_APIC_bitfield(APIC_TMR);
982 printk(KERN_DEBUG "... APIC IRR field:\n");
983 print_APIC_bitfield(APIC_IRR);
984
985 if (APIC_INTEGRATED(ver)) { /* !82489DX */
986 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
987 apic_write(APIC_ESR, 0);
988 v = apic_read(APIC_ESR);
989 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
990 }
991
992 v = apic_read(APIC_ICR);
993 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
994 v = apic_read(APIC_ICR2);
995 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
996
997 v = apic_read(APIC_LVTT);
998 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
999
1000 if (maxlvt > 3) { /* PC is LVT#4. */
1001 v = apic_read(APIC_LVTPC);
1002 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1003 }
1004 v = apic_read(APIC_LVT0);
1005 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1006 v = apic_read(APIC_LVT1);
1007 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1008
1009 if (maxlvt > 2) { /* ERR is LVT#3. */
1010 v = apic_read(APIC_LVTERR);
1011 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1012 }
1013
1014 v = apic_read(APIC_TMICT);
1015 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1016 v = apic_read(APIC_TMCCT);
1017 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1018 v = apic_read(APIC_TDCR);
1019 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1020 printk("\n");
1021 }
1022
print_all_local_APICs(void)1023 void print_all_local_APICs (void)
1024 {
1025 smp_call_function(print_local_APIC, NULL, 1, 1);
1026 print_local_APIC(NULL);
1027 }
1028
print_PIC(void)1029 void /*__init*/ print_PIC(void)
1030 {
1031 extern spinlock_t i8259A_lock;
1032 unsigned int v;
1033 unsigned long flags;
1034
1035 printk(KERN_DEBUG "\nprinting PIC contents\n");
1036
1037 spin_lock_irqsave(&i8259A_lock, flags);
1038
1039 v = inb(0xa1) << 8 | inb(0x21);
1040 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1041
1042 v = inb(0xa0) << 8 | inb(0x20);
1043 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1044
1045 outb(0x0b,0xa0);
1046 outb(0x0b,0x20);
1047 v = inb(0xa0) << 8 | inb(0x20);
1048 outb(0x0a,0xa0);
1049 outb(0x0a,0x20);
1050
1051 spin_unlock_irqrestore(&i8259A_lock, flags);
1052
1053 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1054
1055 v = inb(0x4d1) << 8 | inb(0x4d0);
1056 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1057 }
1058
enable_IO_APIC(void)1059 static void __init enable_IO_APIC(void)
1060 {
1061 struct IO_APIC_reg_01 reg_01;
1062 int i;
1063 unsigned long flags;
1064
1065 for (i = 0; i < PIN_MAP_SIZE; i++) {
1066 irq_2_pin[i].pin = -1;
1067 irq_2_pin[i].next = 0;
1068 }
1069 if (!pirqs_enabled)
1070 for (i = 0; i < MAX_PIRQS; i++)
1071 pirq_entries[i] = -1;
1072
1073 /*
1074 * The number of IO-APIC IRQ registers (== #pins):
1075 */
1076 for (i = 0; i < nr_ioapics; i++) {
1077 spin_lock_irqsave(&ioapic_lock, flags);
1078 *(int *)®_01 = io_apic_read(i, 1);
1079 spin_unlock_irqrestore(&ioapic_lock, flags);
1080 nr_ioapic_registers[i] = reg_01.entries+1;
1081 }
1082
1083 /*
1084 * Do not trust the IO-APIC being empty at bootup
1085 */
1086 clear_IO_APIC();
1087 }
1088
1089 /*
1090 * Not an __init, needed by the reboot code
1091 */
disable_IO_APIC(void)1092 void disable_IO_APIC(void)
1093 {
1094 /*
1095 * Clear the IO-APIC before rebooting:
1096 */
1097 clear_IO_APIC();
1098
1099 disconnect_bsp_APIC();
1100 }
1101
1102 /*
1103 * function to set the IO-APIC physical IDs based on the
1104 * values stored in the MPC table.
1105 *
1106 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1107 */
1108
setup_ioapic_ids_from_mpc(void)1109 static void __init setup_ioapic_ids_from_mpc (void)
1110 {
1111 struct IO_APIC_reg_00 reg_00;
1112 unsigned long phys_id_present_map = phys_cpu_present_map;
1113 int apic;
1114 int i;
1115 unsigned char old_id;
1116 unsigned long flags;
1117
1118 /*
1119 * Set the IOAPIC ID to the value stored in the MPC table.
1120 */
1121 for (apic = 0; apic < nr_ioapics; apic++) {
1122
1123 /* Read the register 0 value */
1124 spin_lock_irqsave(&ioapic_lock, flags);
1125 *(int *)®_00 = io_apic_read(apic, 0);
1126 spin_unlock_irqrestore(&ioapic_lock, flags);
1127
1128 old_id = mp_ioapics[apic].mpc_apicid;
1129
1130 if (mp_ioapics[apic].mpc_apicid >= 0xf) {
1131 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1132 apic, mp_ioapics[apic].mpc_apicid);
1133 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1134 reg_00.ID);
1135 mp_ioapics[apic].mpc_apicid = reg_00.ID;
1136 }
1137
1138 /*
1139 * Sanity check, is the ID really free? Every APIC in a
1140 * system must have a unique ID or we get lots of nice
1141 * 'stuck on smp_invalidate_needed IPI wait' messages.
1142 */
1143 if (phys_id_present_map & (1 << mp_ioapics[apic].mpc_apicid)) {
1144 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1145 apic, mp_ioapics[apic].mpc_apicid);
1146 for (i = 0; i < 0xf; i++)
1147 if (!(phys_id_present_map & (1 << i)))
1148 break;
1149 if (i >= 0xf)
1150 panic("Max APIC ID exceeded!\n");
1151 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1152 i);
1153 phys_id_present_map |= 1 << i;
1154 mp_ioapics[apic].mpc_apicid = i;
1155 } else {
1156 printk("Setting %d in the phys_id_present_map\n", mp_ioapics[apic].mpc_apicid);
1157 phys_id_present_map |= 1 << mp_ioapics[apic].mpc_apicid;
1158 }
1159
1160
1161 /*
1162 * We need to adjust the IRQ routing table
1163 * if the ID changed.
1164 */
1165 if (old_id != mp_ioapics[apic].mpc_apicid)
1166 for (i = 0; i < mp_irq_entries; i++)
1167 if (mp_irqs[i].mpc_dstapic == old_id)
1168 mp_irqs[i].mpc_dstapic
1169 = mp_ioapics[apic].mpc_apicid;
1170
1171 /*
1172 * Read the right value from the MPC table and
1173 * write it into the ID register.
1174 */
1175 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1176 mp_ioapics[apic].mpc_apicid);
1177
1178 reg_00.ID = mp_ioapics[apic].mpc_apicid;
1179 spin_lock_irqsave(&ioapic_lock, flags);
1180 io_apic_write(apic, 0, *(int *)®_00);
1181 spin_unlock_irqrestore(&ioapic_lock, flags);
1182
1183 /*
1184 * Sanity check
1185 */
1186 spin_lock_irqsave(&ioapic_lock, flags);
1187 *(int *)®_00 = io_apic_read(apic, 0);
1188 spin_unlock_irqrestore(&ioapic_lock, flags);
1189 if (reg_00.ID != mp_ioapics[apic].mpc_apicid)
1190 panic("could not set ID!\n");
1191 else
1192 printk(" ok.\n");
1193 }
1194 }
1195
1196 /*
1197 * There is a nasty bug in some older SMP boards, their mptable lies
1198 * about the timer IRQ. We do the following to work around the situation:
1199 *
1200 * - timer IRQ defaults to IO-APIC IRQ
1201 * - if this function detects that timer IRQs are defunct, then we fall
1202 * back to ISA timer IRQs
1203 */
timer_irq_works(void)1204 static int __init timer_irq_works(void)
1205 {
1206 unsigned int t1 = jiffies;
1207
1208 sti();
1209 /* Let ten ticks pass... */
1210 mdelay((10 * 1000) / HZ);
1211
1212 /*
1213 * Expect a few ticks at least, to be sure some possible
1214 * glue logic does not lock up after one or two first
1215 * ticks in a non-ExtINT mode. Also the local APIC
1216 * might have cached one ExtINT interrupt. Finally, at
1217 * least one tick may be lost due to delays.
1218 */
1219 if (jiffies - t1 > 4)
1220 return 1;
1221
1222 return 0;
1223 }
1224
1225 /*
1226 * In the SMP+IOAPIC case it might happen that there are an unspecified
1227 * number of pending IRQ events unhandled. These cases are very rare,
1228 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1229 * better to do it this way as thus we do not have to be aware of
1230 * 'pending' interrupts in the IRQ path, except at this point.
1231 */
1232 /*
1233 * Edge triggered needs to resend any interrupt
1234 * that was delayed but this is now handled in the device
1235 * independent code.
1236 */
1237 #define enable_edge_ioapic_irq unmask_IO_APIC_irq
1238
disable_edge_ioapic_irq(unsigned int irq)1239 static void disable_edge_ioapic_irq (unsigned int irq) { /* nothing */ }
1240
1241 /*
1242 * Starting up a edge-triggered IO-APIC interrupt is
1243 * nasty - we need to make sure that we get the edge.
1244 * If it is already asserted for some reason, we need
1245 * return 1 to indicate that is was pending.
1246 *
1247 * This is not complete - we should be able to fake
1248 * an edge even if it isn't on the 8259A...
1249 */
1250
startup_edge_ioapic_irq(unsigned int irq)1251 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1252 {
1253 int was_pending = 0;
1254 unsigned long flags;
1255
1256 spin_lock_irqsave(&ioapic_lock, flags);
1257 if (irq < 16) {
1258 disable_8259A_irq(irq);
1259 if (i8259A_irq_pending(irq))
1260 was_pending = 1;
1261 }
1262 __unmask_IO_APIC_irq(irq);
1263 spin_unlock_irqrestore(&ioapic_lock, flags);
1264
1265 return was_pending;
1266 }
1267
1268 #define shutdown_edge_ioapic_irq disable_edge_ioapic_irq
1269
1270 /*
1271 * Once we have recorded IRQ_PENDING already, we can mask the
1272 * interrupt for real. This prevents IRQ storms from unhandled
1273 * devices.
1274 */
ack_edge_ioapic_irq(unsigned int irq)1275 static void ack_edge_ioapic_irq(unsigned int irq)
1276 {
1277 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1278 == (IRQ_PENDING | IRQ_DISABLED))
1279 mask_IO_APIC_irq(irq);
1280 ack_APIC_irq();
1281 }
1282
end_edge_ioapic_irq(unsigned int i)1283 static void end_edge_ioapic_irq (unsigned int i) { /* nothing */ }
1284
1285
1286 /*
1287 * Level triggered interrupts can just be masked,
1288 * and shutting down and starting up the interrupt
1289 * is the same as enabling and disabling them -- except
1290 * with a startup need to return a "was pending" value.
1291 *
1292 * Level triggered interrupts are special because we
1293 * do not touch any IO-APIC register while handling
1294 * them. We ack the APIC in the end-IRQ handler, not
1295 * in the start-IRQ-handler. Protection against reentrance
1296 * from the same interrupt is still provided, both by the
1297 * generic IRQ layer and by the fact that an unacked local
1298 * APIC does not accept IRQs.
1299 */
startup_level_ioapic_irq(unsigned int irq)1300 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1301 {
1302 unmask_IO_APIC_irq(irq);
1303
1304 return 0; /* don't check for pending */
1305 }
1306
1307 #define shutdown_level_ioapic_irq mask_IO_APIC_irq
1308 #define enable_level_ioapic_irq unmask_IO_APIC_irq
1309 #define disable_level_ioapic_irq mask_IO_APIC_irq
1310
end_level_ioapic_irq(unsigned int irq)1311 static void end_level_ioapic_irq (unsigned int irq)
1312 {
1313 unsigned long v;
1314 int i;
1315
1316 /*
1317 * It appears there is an erratum which affects at least version 0x11
1318 * of I/O APIC (that's the 82093AA and cores integrated into various
1319 * chipsets). Under certain conditions a level-triggered interrupt is
1320 * erroneously delivered as edge-triggered one but the respective IRR
1321 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1322 * message but it will never arrive and further interrupts are blocked
1323 * from the source. The exact reason is so far unknown, but the
1324 * phenomenon was observed when two consecutive interrupt requests
1325 * from a given source get delivered to the same CPU and the source is
1326 * temporarily disabled in between.
1327 *
1328 * A workaround is to simulate an EOI message manually. We achieve it
1329 * by setting the trigger mode to edge and then to level when the edge
1330 * trigger mode gets detected in the TMR of a local APIC for a
1331 * level-triggered interrupt. We mask the source for the time of the
1332 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1333 * The idea is from Manfred Spraul. --macro
1334 */
1335 i = IO_APIC_VECTOR(irq);
1336 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1337
1338 ack_APIC_irq();
1339
1340 if (!(v & (1 << (i & 0x1f)))) {
1341 #ifdef APIC_LOCKUP_DEBUG
1342 struct irq_pin_list *entry;
1343 #endif
1344
1345 #ifdef APIC_MISMATCH_DEBUG
1346 atomic_inc(&irq_mis_count);
1347 #endif
1348 spin_lock(&ioapic_lock);
1349 __mask_and_edge_IO_APIC_irq(irq);
1350 #ifdef APIC_LOCKUP_DEBUG
1351 for (entry = irq_2_pin + irq;;) {
1352 unsigned int reg;
1353
1354 if (entry->pin == -1)
1355 break;
1356 reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1357 if (reg & 0x00004000)
1358 printk(KERN_CRIT "Aieee!!! Remote IRR"
1359 " still set after unlock!\n");
1360 if (!entry->next)
1361 break;
1362 entry = irq_2_pin + entry->next;
1363 }
1364 #endif
1365 __unmask_and_level_IO_APIC_irq(irq);
1366 spin_unlock(&ioapic_lock);
1367 }
1368 }
1369
mask_and_ack_level_ioapic_irq(unsigned int irq)1370 static void mask_and_ack_level_ioapic_irq (unsigned int irq) { /* nothing */ }
1371
set_ioapic_affinity(unsigned int irq,unsigned long mask)1372 static void set_ioapic_affinity (unsigned int irq, unsigned long mask)
1373 {
1374 unsigned long flags;
1375 /*
1376 * Only the first 8 bits are valid.
1377 */
1378 mask = mask << 24;
1379
1380 spin_lock_irqsave(&ioapic_lock, flags);
1381 __DO_ACTION(1, = mask, )
1382 spin_unlock_irqrestore(&ioapic_lock, flags);
1383 }
1384
1385 /*
1386 * Level and edge triggered IO-APIC interrupts need different handling,
1387 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1388 * handled with the level-triggered descriptor, but that one has slightly
1389 * more overhead. Level-triggered interrupts cannot be handled with the
1390 * edge-triggered handler, without risking IRQ storms and other ugly
1391 * races.
1392 */
1393
1394 static struct hw_interrupt_type ioapic_edge_irq_type = {
1395 "IO-APIC-edge",
1396 startup_edge_ioapic_irq,
1397 shutdown_edge_ioapic_irq,
1398 enable_edge_ioapic_irq,
1399 disable_edge_ioapic_irq,
1400 ack_edge_ioapic_irq,
1401 end_edge_ioapic_irq,
1402 set_ioapic_affinity,
1403 };
1404
1405 static struct hw_interrupt_type ioapic_level_irq_type = {
1406 "IO-APIC-level",
1407 startup_level_ioapic_irq,
1408 shutdown_level_ioapic_irq,
1409 enable_level_ioapic_irq,
1410 disable_level_ioapic_irq,
1411 mask_and_ack_level_ioapic_irq,
1412 end_level_ioapic_irq,
1413 set_ioapic_affinity,
1414 };
1415
init_IO_APIC_traps(void)1416 static inline void init_IO_APIC_traps(void)
1417 {
1418 int irq;
1419
1420 /*
1421 * NOTE! The local APIC isn't very good at handling
1422 * multiple interrupts at the same interrupt level.
1423 * As the interrupt level is determined by taking the
1424 * vector number and shifting that right by 4, we
1425 * want to spread these out a bit so that they don't
1426 * all fall in the same interrupt level.
1427 *
1428 * Also, we've got to be careful not to trash gate
1429 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1430 */
1431 for (irq = 0; irq < NR_IRQS ; irq++) {
1432 if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq)) {
1433 /*
1434 * Hmm.. We don't have an entry for this,
1435 * so default to an old-fashioned 8259
1436 * interrupt if we can..
1437 */
1438 if (irq < 16)
1439 make_8259A_irq(irq);
1440 else
1441 /* Strange. Oh, well.. */
1442 irq_desc[irq].handler = &no_irq_type;
1443 }
1444 }
1445 }
1446
enable_lapic_irq(unsigned int irq)1447 static void enable_lapic_irq (unsigned int irq)
1448 {
1449 unsigned long v;
1450
1451 v = apic_read(APIC_LVT0);
1452 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1453 }
1454
disable_lapic_irq(unsigned int irq)1455 static void disable_lapic_irq (unsigned int irq)
1456 {
1457 unsigned long v;
1458
1459 v = apic_read(APIC_LVT0);
1460 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1461 }
1462
ack_lapic_irq(unsigned int irq)1463 static void ack_lapic_irq (unsigned int irq)
1464 {
1465 ack_APIC_irq();
1466 }
1467
end_lapic_irq(unsigned int i)1468 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1469
1470 static struct hw_interrupt_type lapic_irq_type = {
1471 "local-APIC-edge",
1472 NULL, /* startup_irq() not used for IRQ0 */
1473 NULL, /* shutdown_irq() not used for IRQ0 */
1474 enable_lapic_irq,
1475 disable_lapic_irq,
1476 ack_lapic_irq,
1477 end_lapic_irq
1478 };
1479
enable_NMI_through_LVT0(void * dummy)1480 void enable_NMI_through_LVT0 (void * dummy)
1481 {
1482 unsigned int v, ver;
1483
1484 printk("enable NMI through LVT0 on cpu %d\n", smp_processor_id());
1485
1486 ver = apic_read(APIC_LVR);
1487 ver = GET_APIC_VERSION(ver);
1488 v = APIC_DM_NMI; /* unmask and set to NMI */
1489 if (!APIC_INTEGRATED(ver)) /* 82489DX */
1490 v |= APIC_LVT_LEVEL_TRIGGER;
1491 apic_write_around(APIC_LVT0, v);
1492 }
1493
setup_nmi(void)1494 static void setup_nmi (void)
1495 {
1496 /*
1497 * Dirty trick to enable the NMI watchdog ...
1498 * We put the 8259A master into AEOI mode and
1499 * unmask on all local APICs LVT0 as NMI.
1500 *
1501 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1502 * is from Maciej W. Rozycki - so we do not have to EOI from
1503 * the NMI handler or the timer interrupt.
1504 */
1505 printk(KERN_INFO "activating NMI Watchdog ...");
1506
1507 smp_call_function(enable_NMI_through_LVT0, NULL, 1, 1);
1508 enable_NMI_through_LVT0(NULL);
1509
1510 printk(" done.\n");
1511 }
1512
1513 /*
1514 * This looks a bit hackish but it's about the only one way of sending
1515 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1516 * not support the ExtINT mode, unfortunately. We need to send these
1517 * cycles as some i82489DX-based boards have glue logic that keeps the
1518 * 8259A interrupt line asserted until INTA. --macro
1519 */
unlock_ExtINT_logic(void)1520 static inline void unlock_ExtINT_logic(void)
1521 {
1522 int pin, i;
1523 struct IO_APIC_route_entry entry0, entry1;
1524 unsigned char save_control, save_freq_select;
1525 unsigned long flags;
1526
1527 pin = find_isa_irq_pin(8, mp_INT);
1528 if (pin == -1)
1529 return;
1530
1531 spin_lock_irqsave(&ioapic_lock, flags);
1532 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1533 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1534 spin_unlock_irqrestore(&ioapic_lock, flags);
1535 clear_IO_APIC_pin(0, pin);
1536
1537 memset(&entry1, 0, sizeof(entry1));
1538
1539 entry1.dest_mode = 0; /* physical delivery */
1540 entry1.mask = 0; /* unmask IRQ now */
1541 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1542 entry1.delivery_mode = dest_ExtINT;
1543 entry1.polarity = entry0.polarity;
1544 entry1.trigger = 0;
1545 entry1.vector = 0;
1546
1547 spin_lock_irqsave(&ioapic_lock, flags);
1548 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1549 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1550 spin_unlock_irqrestore(&ioapic_lock, flags);
1551
1552 save_control = CMOS_READ(RTC_CONTROL);
1553 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1554 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1555 RTC_FREQ_SELECT);
1556 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1557
1558 i = 100;
1559 while (i-- > 0) {
1560 mdelay(10);
1561 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1562 i -= 10;
1563 }
1564
1565 CMOS_WRITE(save_control, RTC_CONTROL);
1566 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1567 clear_IO_APIC_pin(0, pin);
1568
1569 spin_lock_irqsave(&ioapic_lock, flags);
1570 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1571 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1572 spin_unlock_irqrestore(&ioapic_lock, flags);
1573 }
1574
1575 /*
1576 * This code may look a bit paranoid, but it's supposed to cooperate with
1577 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1578 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1579 * fanatically on his truly buggy board.
1580 */
check_timer(void)1581 static inline void check_timer(void)
1582 {
1583 int pin1, pin2;
1584 int vector;
1585
1586 /*
1587 * get/set the timer IRQ vector:
1588 */
1589 disable_8259A_irq(0);
1590 vector = assign_irq_vector(0);
1591 set_intr_gate(vector, interrupt[0]);
1592
1593 /*
1594 * Subtle, code in do_timer_interrupt() expects an AEOI
1595 * mode for the 8259A whenever interrupts are routed
1596 * through I/O APICs. Also IRQ0 has to be enabled in
1597 * the 8259A which implies the virtual wire has to be
1598 * disabled in the local APIC.
1599 */
1600 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1601 init_8259A(1);
1602 enable_8259A_irq(0);
1603
1604 pin1 = find_isa_irq_pin(0, mp_INT);
1605 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1606
1607 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1608
1609 if (pin1 != -1) {
1610 /*
1611 * Ok, does IRQ0 through the IOAPIC work?
1612 */
1613 unmask_IO_APIC_irq(0);
1614 if (timer_irq_works()) {
1615 if (nmi_watchdog == NMI_IO_APIC) {
1616 disable_8259A_irq(0);
1617 setup_nmi();
1618 enable_8259A_irq(0);
1619 check_nmi_watchdog();
1620 }
1621 return;
1622 }
1623 clear_IO_APIC_pin(0, pin1);
1624 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1625 }
1626
1627 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1628 if (pin2 != -1) {
1629 printk("\n..... (found pin %d) ...", pin2);
1630 /*
1631 * legacy devices should be connected to IO APIC #0
1632 */
1633 setup_ExtINT_IRQ0_pin(pin2, vector);
1634 if (timer_irq_works()) {
1635 printk("works.\n");
1636 if (pin1 != -1)
1637 replace_pin_at_irq(0, 0, pin1, 0, pin2);
1638 else
1639 add_pin_to_irq(0, 0, pin2);
1640 if (nmi_watchdog == NMI_IO_APIC) {
1641 setup_nmi();
1642 check_nmi_watchdog();
1643 }
1644 return;
1645 }
1646 /*
1647 * Cleanup, just in case ...
1648 */
1649 clear_IO_APIC_pin(0, pin2);
1650 }
1651 printk(" failed.\n");
1652
1653 if (nmi_watchdog) {
1654 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1655 nmi_watchdog = 0;
1656 }
1657
1658 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1659
1660 disable_8259A_irq(0);
1661 irq_desc[0].handler = &lapic_irq_type;
1662 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1663 enable_8259A_irq(0);
1664
1665 if (timer_irq_works()) {
1666 printk(" works.\n");
1667 return;
1668 }
1669 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1670 printk(" failed.\n");
1671
1672 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1673
1674 init_8259A(0);
1675 make_8259A_irq(0);
1676 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1677
1678 unlock_ExtINT_logic();
1679
1680 if (timer_irq_works()) {
1681 printk(" works.\n");
1682 return;
1683 }
1684 printk(" failed :(.\n");
1685 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1686 }
1687
1688 /*
1689 *
1690 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1691 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1692 * Linux doesn't really care, as it's not actually used
1693 * for any interrupt handling anyway.
1694 */
1695 #define PIC_IRQS (1<<2)
1696
setup_IO_APIC(void)1697 void __init setup_IO_APIC(void)
1698 {
1699 enable_IO_APIC();
1700
1701 if (acpi_ioapic)
1702 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1703 else
1704 io_apic_irqs = ~PIC_IRQS;
1705
1706 printk("ENABLING IO-APIC IRQs\n");
1707
1708 /*
1709 * Set up IO-APIC IRQ routing.
1710 */
1711 if (!acpi_ioapic)
1712 setup_ioapic_ids_from_mpc();
1713 sync_Arb_IDs();
1714 setup_IO_APIC_irqs();
1715 init_IO_APIC_traps();
1716 check_timer();
1717 if (!acpi_ioapic)
1718 print_IO_APIC();
1719 }
1720
1721
1722 /* --------------------------------------------------------------------------
1723 ACPI-based IOAPIC Configuration
1724 -------------------------------------------------------------------------- */
1725
1726 #ifdef CONFIG_ACPI_BOOT
1727
1728 #define IO_APIC_MAX_ID 15
1729
io_apic_get_unique_id(int ioapic,int apic_id)1730 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1731 {
1732 struct IO_APIC_reg_00 reg_00;
1733 static unsigned long apic_id_map = 0;
1734 unsigned long flags;
1735 int i = 0;
1736
1737 /*
1738 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1739 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1740 * supports up to 16 on one shared APIC bus.
1741 *
1742 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1743 * advantage of new APIC bus architecture.
1744 */
1745
1746 if (!apic_id_map)
1747 apic_id_map = phys_cpu_present_map;
1748
1749 spin_lock_irqsave(&ioapic_lock, flags);
1750 *(int *)®_00 = io_apic_read(ioapic, 0);
1751 spin_unlock_irqrestore(&ioapic_lock, flags);
1752
1753 if (apic_id >= IO_APIC_MAX_ID) {
1754 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1755 "%d\n", ioapic, apic_id, reg_00.ID);
1756 apic_id = reg_00.ID;
1757 }
1758
1759 /*
1760 * Every APIC in a system must have a unique ID or we get lots of nice
1761 * 'stuck on smp_invalidate_needed IPI wait' messages.
1762 */
1763 if (apic_id_map & (1 << apic_id)) {
1764
1765 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1766 if (!(apic_id_map & (1 << i)))
1767 break;
1768 }
1769
1770 if (i == IO_APIC_MAX_ID)
1771 panic("Max apic_id exceeded!\n");
1772
1773 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1774 "trying %d\n", ioapic, apic_id, i);
1775
1776 apic_id = i;
1777 }
1778
1779 apic_id_map |= (1 << apic_id);
1780
1781 if (reg_00.ID != apic_id) {
1782 reg_00.ID = apic_id;
1783
1784 spin_lock_irqsave(&ioapic_lock, flags);
1785 io_apic_write(ioapic, 0, *(int *)®_00);
1786 *(int *)®_00 = io_apic_read(ioapic, 0);
1787 spin_unlock_irqrestore(&ioapic_lock, flags);
1788
1789 /* Sanity check */
1790 if (reg_00.ID != apic_id)
1791 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1792 }
1793
1794 printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1795
1796 return apic_id;
1797 }
1798
1799
io_apic_get_version(int ioapic)1800 int __init io_apic_get_version (int ioapic)
1801 {
1802 struct IO_APIC_reg_01 reg_01;
1803 unsigned long flags;
1804
1805 spin_lock_irqsave(&ioapic_lock, flags);
1806 *(int *)®_01 = io_apic_read(ioapic, 1);
1807 spin_unlock_irqrestore(&ioapic_lock, flags);
1808
1809 return reg_01.version;
1810 }
1811
1812
io_apic_get_redir_entries(int ioapic)1813 int __init io_apic_get_redir_entries (int ioapic)
1814 {
1815 struct IO_APIC_reg_01 reg_01;
1816 unsigned long flags;
1817
1818 spin_lock_irqsave(&ioapic_lock, flags);
1819 *(int *)®_01 = io_apic_read(ioapic, 1);
1820 spin_unlock_irqrestore(&ioapic_lock, flags);
1821
1822 return reg_01.entries;
1823 }
1824
1825
io_apic_set_pci_routing(int ioapic,int pin,int irq,int edge_level,int active_high_low)1826 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1827 {
1828 struct IO_APIC_route_entry entry;
1829 unsigned long flags;
1830
1831 if (!IO_APIC_IRQ(irq)) {
1832 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0/n",
1833 ioapic);
1834 return -EINVAL;
1835 }
1836
1837 /*
1838 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1839 * Note that we mask (disable) IRQs now -- these get enabled when the
1840 * corresponding device driver registers for this IRQ.
1841 */
1842
1843 memset(&entry,0,sizeof(entry));
1844
1845 entry.delivery_mode = dest_LowestPrio;
1846 entry.dest_mode = INT_DELIVERY_MODE;
1847 entry.dest.logical.logical_dest = TARGET_CPUS;
1848 entry.mask = 1; /* Disabled (masked) */
1849 entry.trigger = edge_level;
1850 entry.polarity = active_high_low;
1851
1852 /*
1853 * IRQs < 16 are already in the irq_2_pin[] map
1854 */
1855 if (irq >= 16)
1856 add_pin_to_irq(irq, ioapic, pin);
1857
1858 entry.vector = assign_irq_vector(irq);
1859
1860 Dprintk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1861 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1862 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, edge_level, active_high_low);
1863
1864 if (edge_level)
1865 irq_desc[irq].handler = &ioapic_level_irq_type;
1866 else
1867 irq_desc[irq].handler = &ioapic_edge_irq_type;
1868
1869 set_intr_gate(entry.vector, interrupt[irq]);
1870
1871 if (!ioapic && (irq < 16))
1872 disable_8259A_irq(irq);
1873
1874 spin_lock_irqsave(&ioapic_lock, flags);
1875 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1876 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1877 spin_unlock_irqrestore(&ioapic_lock, flags);
1878
1879 return entry.vector;
1880 }
1881
1882 #endif /*CONFIG_ACPI_BOOT*/
1883