1 /*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 */
14
15 #include <linux/config.h>
16 #include <linux/init.h>
17
18 #include <linux/mm.h>
19 #include <linux/irq.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/interrupt.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/kernel_stat.h>
26
27 #include <asm/atomic.h>
28 #include <asm/smp.h>
29 #include <asm/mtrr.h>
30 #include <asm/mpspec.h>
31 #include <asm/pgalloc.h>
32 #include <asm/timex.h>
33
34 int apic_disabled;
35
36 extern spinlock_t i8253_lock;
37
38 /* Using APIC to generate smp_local_timer_interrupt? */
39 int using_apic_timer = 0;
40
41 int prof_multiplier[NR_CPUS] = { 1, };
42 int prof_old_multiplier[NR_CPUS] = { 1, };
43 int prof_counter[NR_CPUS] = { 1, };
44
get_maxlvt(void)45 int get_maxlvt(void)
46 {
47 unsigned int v, ver, maxlvt;
48
49 v = apic_read(APIC_LVR);
50 ver = GET_APIC_VERSION(v);
51 /* 82489DXs do not report # of LVT entries. */
52 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
53 return maxlvt;
54 }
55
clear_local_APIC(void)56 void clear_local_APIC(void)
57 {
58 int maxlvt;
59 unsigned int v;
60
61 maxlvt = get_maxlvt();
62
63 /*
64 * Masking an LVT entry on a P6 can trigger a local APIC error
65 * if the vector is zero. Mask LVTERR first to prevent this.
66 */
67 if (maxlvt >= 3) {
68 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
69 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
70 }
71 /*
72 * Careful: we have to set masks only first to deassert
73 * any level-triggered sources.
74 */
75 v = apic_read(APIC_LVTT);
76 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
77 v = apic_read(APIC_LVT0);
78 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
79 v = apic_read(APIC_LVT1);
80 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
81 if (maxlvt >= 4) {
82 v = apic_read(APIC_LVTPC);
83 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
84 }
85
86 /*
87 * Clean APIC state for other OSs:
88 */
89 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
90 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
91 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
92 if (maxlvt >= 3)
93 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
94 if (maxlvt >= 4)
95 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
96 v = GET_APIC_VERSION(apic_read(APIC_LVR));
97 if (APIC_INTEGRATED(v)) { /* !82489DX */
98 if (maxlvt > 3)
99 apic_write(APIC_ESR, 0);
100 apic_read(APIC_ESR);
101 }
102 }
103
connect_bsp_APIC(void)104 void __init connect_bsp_APIC(void)
105 {
106 if (pic_mode) {
107 /*
108 * Do not trust the local APIC being empty at bootup.
109 */
110 clear_local_APIC();
111 /*
112 * PIC mode, enable APIC mode in the IMCR, i.e.
113 * connect BSP's local APIC to INT and NMI lines.
114 */
115 printk("leaving PIC mode, enabling APIC mode.\n");
116 outb(0x70, 0x22);
117 outb(0x01, 0x23);
118 }
119 }
120
disconnect_bsp_APIC(void)121 void disconnect_bsp_APIC(void)
122 {
123 if (pic_mode) {
124 /*
125 * Put the board back into PIC mode (has an effect
126 * only on certain older boards). Note that APIC
127 * interrupts, including IPIs, won't work beyond
128 * this point! The only exception are INIT IPIs.
129 */
130 printk("disabling APIC mode, entering PIC mode.\n");
131 outb(0x70, 0x22);
132 outb(0x00, 0x23);
133 }
134 }
135
disable_local_APIC(void)136 void disable_local_APIC(void)
137 {
138 unsigned int value;
139
140 clear_local_APIC();
141
142 /*
143 * Disable APIC (implies clearing of registers
144 * for 82489DX!).
145 */
146 value = apic_read(APIC_SPIV);
147 value &= ~APIC_SPIV_APIC_ENABLED;
148 apic_write_around(APIC_SPIV, value);
149 }
150
151 /*
152 * This is to verify that we're looking at a real local APIC.
153 * Check these against your board if the CPUs aren't getting
154 * started for no apparent reason.
155 */
verify_local_APIC(void)156 int __init verify_local_APIC(void)
157 {
158 unsigned int reg0, reg1;
159
160 /*
161 * The version register is read-only in a real APIC.
162 */
163 reg0 = apic_read(APIC_LVR);
164 Dprintk("Getting VERSION: %x\n", reg0);
165 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
166 reg1 = apic_read(APIC_LVR);
167 Dprintk("Getting VERSION: %x\n", reg1);
168
169 /*
170 * The two version reads above should print the same
171 * numbers. If the second one is different, then we
172 * poke at a non-APIC.
173 */
174 if (reg1 != reg0)
175 return 0;
176
177 /*
178 * Check if the version looks reasonably.
179 */
180 reg1 = GET_APIC_VERSION(reg0);
181 if (reg1 == 0x00 || reg1 == 0xff)
182 return 0;
183 reg1 = get_maxlvt();
184 if (reg1 < 0x02 || reg1 == 0xff)
185 return 0;
186
187 /*
188 * The ID register is read/write in a real APIC.
189 */
190 reg0 = apic_read(APIC_ID);
191 Dprintk("Getting ID: %x\n", reg0);
192 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
193 reg1 = apic_read(APIC_ID);
194 Dprintk("Getting ID: %x\n", reg1);
195 apic_write(APIC_ID, reg0);
196 if (reg1 != (reg0 ^ APIC_ID_MASK))
197 return 0;
198
199 /*
200 * The next two are just to see if we have sane values.
201 * They're only really relevant if we're in Virtual Wire
202 * compatibility mode, but most boxes are anymore.
203 */
204 reg0 = apic_read(APIC_LVT0);
205 Dprintk("Getting LVT0: %x\n", reg0);
206 reg1 = apic_read(APIC_LVT1);
207 Dprintk("Getting LVT1: %x\n", reg1);
208
209 return 1;
210 }
211
sync_Arb_IDs(void)212 void __init sync_Arb_IDs(void)
213 {
214 /*
215 * Wait for idle.
216 */
217 apic_wait_icr_idle();
218
219 Dprintk("Synchronizing Arb IDs.\n");
220 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
221 | APIC_DM_INIT);
222 }
223
224 extern void __error_in_apic_c (void);
225
226 /*
227 * An initial setup of the virtual wire mode.
228 */
init_bsp_APIC(void)229 void __init init_bsp_APIC(void)
230 {
231 unsigned int value, ver;
232
233 /*
234 * Don't do the setup now if we have a SMP BIOS as the
235 * through-I/O-APIC virtual wire mode might be active.
236 */
237 if (smp_found_config || !cpu_has_apic)
238 return;
239
240 value = apic_read(APIC_LVR);
241 ver = GET_APIC_VERSION(value);
242
243 /*
244 * Do not trust the local APIC being empty at bootup.
245 */
246 clear_local_APIC();
247
248 /*
249 * Enable APIC.
250 */
251 value = apic_read(APIC_SPIV);
252 value &= ~APIC_VECTOR_MASK;
253 value |= APIC_SPIV_APIC_ENABLED;
254 value |= APIC_SPIV_FOCUS_DISABLED;
255 value |= SPURIOUS_APIC_VECTOR;
256 apic_write_around(APIC_SPIV, value);
257
258 /*
259 * Set up the virtual wire mode.
260 */
261 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
262 value = APIC_DM_NMI;
263 if (!APIC_INTEGRATED(ver)) /* 82489DX */
264 value |= APIC_LVT_LEVEL_TRIGGER;
265 apic_write_around(APIC_LVT1, value);
266 }
267
setup_local_APIC(void)268 void __init setup_local_APIC (void)
269 {
270 unsigned int value, ver, maxlvt;
271
272 /* Pound the ESR really hard over the head with a big hammer - mbligh */
273 if (esr_disable) {
274 apic_write(APIC_ESR, 0);
275 apic_write(APIC_ESR, 0);
276 apic_write(APIC_ESR, 0);
277 apic_write(APIC_ESR, 0);
278 }
279
280 value = apic_read(APIC_LVR);
281 ver = GET_APIC_VERSION(value);
282
283 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
284 __error_in_apic_c();
285
286 /*
287 * Double-check wether this APIC is really registered.
288 * This is meaningless in clustered apic mode, so we skip it.
289 */
290 if (!clustered_apic_mode &&
291 !test_bit(GET_APIC_ID(apic_read(APIC_ID)), &phys_cpu_present_map))
292 BUG();
293
294 /*
295 * Intel recommends to set DFR, LDR and TPR before enabling
296 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
297 * document number 292116). So here it goes...
298 */
299
300 if (!clustered_apic_mode) {
301 /*
302 * In clustered apic mode, the firmware does this for us
303 * Put the APIC into flat delivery mode.
304 * Must be "all ones" explicitly for 82489DX.
305 */
306 apic_write_around(APIC_DFR, 0xffffffff);
307
308 /*
309 * Set up the logical destination ID.
310 */
311 value = apic_read(APIC_LDR);
312 value &= ~APIC_LDR_MASK;
313 value |= (1<<(smp_processor_id()+24));
314 apic_write_around(APIC_LDR, value);
315 }
316
317 /*
318 * Set Task Priority to 'accept all'. We never change this
319 * later on.
320 */
321 value = apic_read(APIC_TASKPRI);
322 value &= ~APIC_TPRI_MASK;
323 apic_write_around(APIC_TASKPRI, value);
324
325 /*
326 * Now that we are all set up, enable the APIC
327 */
328 value = apic_read(APIC_SPIV);
329 value &= ~APIC_VECTOR_MASK;
330 /*
331 * Enable APIC
332 */
333 value |= APIC_SPIV_APIC_ENABLED;
334
335 /*
336 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
337 * certain networking cards. If high frequency interrupts are
338 * happening on a particular IOAPIC pin, plus the IOAPIC routing
339 * entry is masked/unmasked at a high rate as well then sooner or
340 * later IOAPIC line gets 'stuck', no more interrupts are received
341 * from the device. If focus CPU is disabled then the hang goes
342 * away, oh well :-(
343 *
344 * [ This bug can be reproduced easily with a level-triggered
345 * PCI Ne2000 networking cards and PII/PIII processors, dual
346 * BX chipset. ]
347 */
348 /*
349 * Actually disabling the focus CPU check just makes the hang less
350 * frequent as it makes the interrupt distributon model be more
351 * like LRU than MRU (the short-term load is more even across CPUs).
352 * See also the comment in end_level_ioapic_irq(). --macro
353 */
354 #if 1
355 /* Enable focus processor (bit==0) */
356 value &= ~APIC_SPIV_FOCUS_DISABLED;
357 #else
358 /* Disable focus processor (bit==1) */
359 value |= APIC_SPIV_FOCUS_DISABLED;
360 #endif
361 /*
362 * Set spurious IRQ vector
363 */
364 value |= SPURIOUS_APIC_VECTOR;
365 apic_write_around(APIC_SPIV, value);
366
367 /*
368 * Set up LVT0, LVT1:
369 *
370 * set up through-local-APIC on the BP's LINT0. This is not
371 * strictly necessery in pure symmetric-IO mode, but sometimes
372 * we delegate interrupts to the 8259A.
373 */
374 /*
375 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
376 */
377 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
378 if (!smp_processor_id() && (pic_mode || !value)) {
379 value = APIC_DM_EXTINT;
380 Dprintk("enabled ExtINT on CPU#%d\n", smp_processor_id());
381 } else {
382 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
383 Dprintk("masked ExtINT on CPU#%d\n", smp_processor_id());
384 }
385 apic_write_around(APIC_LVT0, value);
386
387 /*
388 * only the BP should see the LINT1 NMI signal, obviously.
389 */
390 if (!smp_processor_id())
391 value = APIC_DM_NMI;
392 else
393 value = APIC_DM_NMI | APIC_LVT_MASKED;
394 if (!APIC_INTEGRATED(ver)) /* 82489DX */
395 value |= APIC_LVT_LEVEL_TRIGGER;
396 apic_write_around(APIC_LVT1, value);
397
398 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
399 maxlvt = get_maxlvt();
400 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
401 apic_write(APIC_ESR, 0);
402 value = apic_read(APIC_ESR);
403 Dprintk("ESR value before enabling vector: %08x\n", value);
404
405 value = ERROR_APIC_VECTOR; /* enables sending errors */
406 apic_write_around(APIC_LVTERR, value);
407 /*
408 * spec says clear errors after enabling vector.
409 */
410 if (maxlvt > 3)
411 apic_write(APIC_ESR, 0);
412 value = apic_read(APIC_ESR);
413 Dprintk("ESR value after enabling vector: %08x\n", value);
414 } else {
415 if (esr_disable)
416 /*
417 * Something untraceble is creating bad interrupts on
418 * secondary quads ... for the moment, just leave the
419 * ESR disabled - we can't do anything useful with the
420 * errors anyway - mbligh
421 */
422 Dprintk("Leaving ESR disabled.\n");
423 else
424 Dprintk("No ESR for 82489DX.\n");
425 }
426
427 if (nmi_watchdog == NMI_LOCAL_APIC)
428 setup_apic_nmi_watchdog();
429 }
430
431 #ifdef CONFIG_PM
432
433 #include <linux/slab.h>
434 #include <linux/pm.h>
435
436 static struct {
437 /* 'active' is true if the local APIC was enabled by us and
438 not the BIOS; this signifies that we are also responsible
439 for disabling it before entering apm/acpi suspend */
440 int active;
441 /* 'perfctr_pmdev' is here because the current (2.4.1) PM
442 callback system doesn't handle hierarchical dependencies */
443 struct pm_dev *perfctr_pmdev;
444 /* r/w apic fields */
445 unsigned int apic_id;
446 unsigned int apic_taskpri;
447 unsigned int apic_ldr;
448 unsigned int apic_dfr;
449 unsigned int apic_spiv;
450 unsigned int apic_lvtt;
451 unsigned int apic_lvtpc;
452 unsigned int apic_lvt0;
453 unsigned int apic_lvt1;
454 unsigned int apic_lvterr;
455 unsigned int apic_tmict;
456 unsigned int apic_tdcr;
457 } apic_pm_state;
458
apic_pm_suspend(void * data)459 static void apic_pm_suspend(void *data)
460 {
461 unsigned int l, h;
462 unsigned long flags;
463
464 if (apic_pm_state.perfctr_pmdev)
465 pm_send(apic_pm_state.perfctr_pmdev, PM_SUSPEND, data);
466 apic_pm_state.apic_id = apic_read(APIC_ID);
467 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
468 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
469 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
470 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
471 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
472 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
473 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
474 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
475 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
476 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
477 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
478 __save_flags(flags);
479 __cli();
480 disable_local_APIC();
481 rdmsr(MSR_IA32_APICBASE, l, h);
482 l &= ~MSR_IA32_APICBASE_ENABLE;
483 wrmsr(MSR_IA32_APICBASE, l, h);
484 __restore_flags(flags);
485 }
486
apic_pm_resume(void * data)487 static void apic_pm_resume(void *data)
488 {
489 unsigned int l, h;
490 unsigned long flags;
491
492 __save_flags(flags);
493 __cli();
494 rdmsr(MSR_IA32_APICBASE, l, h);
495 l &= ~MSR_IA32_APICBASE_BASE;
496 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
497 wrmsr(MSR_IA32_APICBASE, l, h);
498 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
499 apic_write(APIC_ID, apic_pm_state.apic_id);
500 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
501 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
502 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
503 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
504 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
505 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
506 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
507 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
508 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
509 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
510 apic_write(APIC_ESR, 0);
511 apic_read(APIC_ESR);
512 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
513 apic_write(APIC_ESR, 0);
514 apic_read(APIC_ESR);
515 __restore_flags(flags);
516 if (apic_pm_state.perfctr_pmdev)
517 pm_send(apic_pm_state.perfctr_pmdev, PM_RESUME, data);
518 }
519
apic_pm_callback(struct pm_dev * dev,pm_request_t rqst,void * data)520 static int apic_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data)
521 {
522 switch (rqst) {
523 case PM_SUSPEND:
524 apic_pm_suspend(data);
525 break;
526 case PM_RESUME:
527 apic_pm_resume(data);
528 break;
529 }
530 return 0;
531 }
532
533 /* perfctr driver should call this instead of pm_register() */
apic_pm_register(pm_dev_t type,unsigned long id,pm_callback callback)534 struct pm_dev *apic_pm_register(pm_dev_t type,
535 unsigned long id,
536 pm_callback callback)
537 {
538 struct pm_dev *dev;
539
540 if (!apic_pm_state.active)
541 return pm_register(type, id, callback);
542 if (apic_pm_state.perfctr_pmdev)
543 return NULL; /* we're busy */
544 dev = kmalloc(sizeof(struct pm_dev), GFP_KERNEL);
545 if (dev) {
546 memset(dev, 0, sizeof(*dev));
547 dev->type = type;
548 dev->id = id;
549 dev->callback = callback;
550 apic_pm_state.perfctr_pmdev = dev;
551 }
552 return dev;
553 }
554
555 /* perfctr driver should call this instead of pm_unregister() */
apic_pm_unregister(struct pm_dev * dev)556 void apic_pm_unregister(struct pm_dev *dev)
557 {
558 if (!apic_pm_state.active) {
559 pm_unregister(dev);
560 } else if (dev == apic_pm_state.perfctr_pmdev) {
561 apic_pm_state.perfctr_pmdev = NULL;
562 kfree(dev);
563 }
564 }
565
apic_pm_init1(void)566 static void __init apic_pm_init1(void)
567 {
568 /* can't pm_register() at this early stage in the boot process
569 (causes an immediate reboot), so just set the flag */
570 apic_pm_state.active = 1;
571 }
572
apic_pm_init2(void)573 static void __init apic_pm_init2(void)
574 {
575 if (apic_pm_state.active)
576 pm_register(PM_SYS_DEV, 0, apic_pm_callback);
577 }
578
579 #else /* CONFIG_PM */
580
apic_pm_init1(void)581 static inline void apic_pm_init1(void) { }
apic_pm_init2(void)582 static inline void apic_pm_init2(void) { }
583
584 #endif /* CONFIG_PM */
585
586 /*
587 * Detect and enable local APICs on non-SMP boards.
588 * Original code written by Keir Fraser.
589 */
590 int dont_enable_local_apic __initdata = 0;
591
detect_init_APIC(void)592 static int __init detect_init_APIC (void)
593 {
594 /* Disabled by DMI scan or kernel option? */
595 if (dont_enable_local_apic)
596 return -1;
597
598 /* Don't force the APIC if the BIOS didn't enable it. Usually
599 it is broken in some way. */
600 if (!cpu_has_apic) {
601 printk(KERN_INFO "APIC disabled by BIOS.\n");
602 return -1;
603 }
604 set_bit(X86_FEATURE_APIC, &boot_cpu_data.x86_capability);
605 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
606 boot_cpu_id = 0;
607 if (nmi_watchdog != NMI_NONE)
608 nmi_watchdog = NMI_LOCAL_APIC;
609
610 printk(KERN_INFO "Found and enabled local APIC!\n");
611
612 apic_pm_init1();
613
614 return 0;
615 }
616
init_apic_mappings(void)617 void __init init_apic_mappings(void)
618 {
619 unsigned long apic_phys;
620
621 /*
622 * If no local APIC can be found then set up a fake all
623 * zeroes page to simulate the local APIC and another
624 * one for the IO-APIC.
625 */
626 if (!smp_found_config && detect_init_APIC()) {
627 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
628 apic_phys = __pa(apic_phys);
629 } else
630 apic_phys = mp_lapic_addr;
631
632 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
633 Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys);
634
635 /*
636 * Fetch the APIC ID of the BSP in case we have a
637 * default configuration (or the MP table is broken).
638 */
639 if (boot_cpu_id == -1U)
640 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
641
642 #ifdef CONFIG_X86_IO_APIC
643 {
644 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
645 int i;
646
647 for (i = 0; i < nr_ioapics; i++) {
648 if (smp_found_config) {
649 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
650 if (!ioapic_phys) {
651 printk(KERN_ERR "WARNING: bogus zero IO-APIC address found in MPTABLE, disabling IO-APIC support\n");
652 smp_found_config = 0;
653 skip_ioapic_setup = 1;
654 goto fake_ioapic_page;
655 }
656 } else {
657 fake_ioapic_page:
658 ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
659 ioapic_phys = __pa(ioapic_phys);
660 }
661 set_fixmap_nocache(idx, ioapic_phys);
662 Dprintk("mapped IOAPIC to %08lx (%08lx)\n",
663 __fix_to_virt(idx), ioapic_phys);
664 idx++;
665 }
666 }
667 #endif
668 }
669
670 /*
671 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
672 * per second. We assume that the caller has already set up the local
673 * APIC.
674 */
675
676 /*
677 * This function sets up the local APIC timer, with a timeout of
678 * 'clocks' APIC bus clock. During calibration we actually call
679 * this function twice on the boot CPU, once with a bogus timeout
680 * value, second time for real. The other (noncalibrating) CPUs
681 * call this function only once, with the real, calibrated value.
682 *
683 * We do reads before writes even if unnecessary, to get around the
684 * P5 APIC double write bug.
685 */
686
687 #define APIC_DIVISOR 16
688
__setup_APIC_LVTT(unsigned int clocks)689 void __setup_APIC_LVTT(unsigned int clocks)
690 {
691 unsigned int lvtt1_value, tmp_value;
692
693 lvtt1_value = SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV) |
694 APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
695 apic_write_around(APIC_LVTT, lvtt1_value);
696
697 /*
698 * Divide PICLK by 16
699 */
700 tmp_value = apic_read(APIC_TDCR);
701 apic_write_around(APIC_TDCR, (tmp_value
702 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
703 | APIC_TDR_DIV_16);
704
705 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
706 }
707
setup_APIC_timer(void * data)708 void setup_APIC_timer(void * data)
709 {
710 unsigned int clocks = (unsigned long) data, slice, t0, t1;
711 int delta;
712
713 /*
714 * ok, Intel has some smart code in their APIC that knows
715 * if a CPU was in 'hlt' lowpower mode, and this increases
716 * its APIC arbitration priority. To avoid the external timer
717 * IRQ APIC event being in synchron with the APIC clock we
718 * introduce an interrupt skew to spread out timer events.
719 *
720 * The number of slices within a 'big' timeslice is smp_num_cpus+1
721 */
722
723 slice = clocks / (smp_num_cpus+1);
724 printk(KERN_INFO "cpu: %d, clocks: %d, slice: %d\n",
725 smp_processor_id(), clocks, slice);
726
727 /*
728 * Wait for timer IRQ slice:
729 */
730
731 if (hpet_address) {
732 int trigger = hpet_readl(HPET_T0_CMP);
733 while (hpet_readl(HPET_COUNTER) >= trigger);
734 while (hpet_readl(HPET_COUNTER) < trigger);
735 } else {
736 int c1, c2;
737 spin_lock(&i8253_lock);
738 outb_p(0x00, 0x43);
739 c2 = inb_p(0x40);
740 c2 |= inb_p(0x40) << 8;
741 do {
742 c1 = c2;
743 outb_p(0x00, 0x43);
744 c2 = inb_p(0x40);
745 c2 |= inb_p(0x40) << 8;
746 } while (c2 - c1 < 300);
747 spin_unlock(&i8253_lock);
748 }
749
750 __setup_APIC_LVTT(clocks);
751
752 t0 = apic_read(APIC_TMICT)*APIC_DIVISOR;
753
754 /* Wait till TMCCT gets reloaded from TMICT... */
755 do {
756 t1 = apic_read(APIC_TMCCT)*APIC_DIVISOR;
757 delta = (int)(t0 - t1 - slice*(smp_processor_id()+1));
758 } while (delta >= 0);
759
760 /* Now wait for our slice for real. */
761 do {
762 t1 = apic_read(APIC_TMCCT)*APIC_DIVISOR;
763 delta = (int)(t0 - t1 - slice*(smp_processor_id()+1));
764 } while (delta < 0);
765
766 __setup_APIC_LVTT(clocks);
767
768 printk(KERN_INFO "CPU%d<T0:%u,T1:%u,D:%d,S:%u,C:%u>\n",
769 smp_processor_id(), t0, t1, delta, slice, clocks);
770 }
771
772 /*
773 * In this function we calibrate APIC bus clocks to the external timer.
774 * Unlike on i386 we don't use the PIT to do that, but rely on a
775 * pre-calibrated TSC counter instead.
776 *
777 * We want to do the calibration only once since we want to have local timer
778 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
779 * frequency. And we want to have irqs off anyways, no accidental APIC irq
780 * that way.
781 */
782
783 #define TICK_COUNT 100000000
784
calibrate_APIC_clock(void)785 int __init calibrate_APIC_clock(void)
786 {
787 int apic, apic_start, tsc, tsc_start;
788 int result;
789 /*
790 * Put whatever arbitrary (but long enough) timeout
791 * value into the APIC clock, we just want to get the
792 * counter running for calibration.
793 */
794 __setup_APIC_LVTT(1000000000);
795
796 apic_start = apic_read(APIC_TMCCT);
797 rdtscl(tsc_start);
798
799 do {
800 apic = apic_read(APIC_TMCCT);
801 rdtscl(tsc);
802 } while ((tsc - tsc_start) < TICK_COUNT && (apic - apic_start) < TICK_COUNT);
803
804 result = (apic_start - apic) * 1000L * cpu_khz / (tsc - tsc_start);
805
806 printk("Detected %d.%03d MHz APIC timer.\n",
807 result / 1000 / 1000, result / 1000 % 1000);
808
809 return result * APIC_DIVISOR / HZ;
810 }
811
812 static unsigned int calibration_result;
813
814 int dont_use_local_apic_timer __initdata = 0;
815
setup_APIC_clocks(void)816 void __init setup_APIC_clocks (void)
817 {
818 /* Disabled by DMI scan or kernel option? */
819 if (dont_use_local_apic_timer)
820 return;
821
822 printk("Using local APIC timer interrupts.\n");
823 using_apic_timer = 1;
824
825 __cli();
826
827 calibration_result = calibrate_APIC_clock();
828 /*
829 * Now set up the timer for real.
830 */
831 setup_APIC_timer((void *)(u64)calibration_result);
832
833 __sti();
834
835 /* and update all other cpus */
836 smp_call_function(setup_APIC_timer, (void *)(u64)calibration_result, 1, 1);
837 }
838
839 /*
840 * the frequency of the profiling timer can be changed
841 * by writing a multiplier value into /proc/profile.
842 */
setup_profiling_timer(unsigned int multiplier)843 int setup_profiling_timer(unsigned int multiplier)
844 {
845 int i;
846
847 /*
848 * Sanity check. [at least 500 APIC cycles should be
849 * between APIC interrupts as a rule of thumb, to avoid
850 * irqs flooding us]
851 */
852 if ( (!multiplier) || (calibration_result/multiplier < 500))
853 return -EINVAL;
854
855 /*
856 * Set the new multiplier for each CPU. CPUs don't start using the
857 * new values until the next timer interrupt in which they do process
858 * accounting. At that time they also adjust their APIC timers
859 * accordingly.
860 */
861 for (i = 0; i < NR_CPUS; ++i)
862 prof_multiplier[i] = multiplier;
863
864 return 0;
865 }
866
867 #undef APIC_DIVISOR
868
869 /*
870 * Local timer interrupt handler. It does both profiling and
871 * process statistics/rescheduling.
872 *
873 * We do profiling in every local tick, statistics/rescheduling
874 * happen only every 'profiling multiplier' ticks. The default
875 * multiplier is 1 and it can be changed by writing the new multiplier
876 * value into /proc/profile.
877 */
878
smp_local_timer_interrupt(struct pt_regs * regs)879 inline void smp_local_timer_interrupt(struct pt_regs *regs)
880 {
881 int user = user_mode(regs);
882 int cpu = smp_processor_id();
883
884 /*
885 * The profiling function is SMP safe. (nothing can mess
886 * around with "current", and the profiling counters are
887 * updated with atomic operations). This is especially
888 * useful with a profiling multiplier != 1
889 */
890 if (!user)
891 x86_do_profile(regs->rip);
892
893 if (--prof_counter[cpu] <= 0) {
894 /*
895 * The multiplier may have changed since the last time we got
896 * to this point as a result of the user writing to
897 * /proc/profile. In this case we need to adjust the APIC
898 * timer accordingly.
899 *
900 * Interrupts are already masked off at this point.
901 */
902 prof_counter[cpu] = prof_multiplier[cpu];
903 if (prof_counter[cpu] != prof_old_multiplier[cpu]) {
904 __setup_APIC_LVTT(calibration_result/prof_counter[cpu]);
905 prof_old_multiplier[cpu] = prof_counter[cpu];
906 }
907
908 #ifdef CONFIG_SMP
909 update_process_times(user);
910 #endif
911 }
912
913 /*
914 * We take the 'long' return path, and there every subsystem
915 * grabs the apropriate locks (kernel lock/ irq lock).
916 *
917 * we might want to decouple profiling from the 'long path',
918 * and do the profiling totally in assembly.
919 *
920 * Currently this isn't too much of an issue (performance wise),
921 * we can take more than 100K local irqs per second on a 100 MHz P5.
922 */
923 }
924
925 /*
926 * Local APIC timer interrupt. This is the most natural way for doing
927 * local interrupts, but local timer interrupts can be emulated by
928 * broadcast interrupts too. [in case the hw doesnt support APIC timers]
929 *
930 * [ if a single-CPU system runs an SMP kernel then we call the local
931 * interrupt as well. Thus we cannot inline the local irq ... ]
932 */
933 unsigned int apic_timer_irqs [NR_CPUS];
934
smp_apic_timer_interrupt(struct pt_regs * regs)935 void smp_apic_timer_interrupt(struct pt_regs *regs)
936 {
937 int cpu = smp_processor_id();
938
939 /*
940 * the NMI deadlock-detector uses this.
941 */
942 apic_timer_irqs[cpu]++;
943
944 /*
945 * NOTE! We'd better ACK the irq immediately,
946 * because timer handling can be slow.
947 */
948 ack_APIC_irq();
949 /*
950 * update_process_times() expects us to have done irq_enter().
951 * Besides, if we don't timer interrupts ignore the global
952 * interrupt lock, which is the WrongThing (tm) to do.
953 */
954 irq_enter(cpu, 0);
955 smp_local_timer_interrupt(regs);
956 irq_exit(cpu, 0);
957
958 if (softirq_pending(cpu))
959 do_softirq();
960 }
961
962 /*
963 * This interrupt should _never_ happen with our APIC/SMP architecture
964 */
smp_spurious_interrupt(void)965 asmlinkage void smp_spurious_interrupt(void)
966 {
967 unsigned int v;
968 static unsigned long last_warning;
969 static unsigned long skipped;
970
971 /*
972 * Check if this really is a spurious interrupt and ACK it
973 * if it is a vectored one. Just in case...
974 * Spurious interrupts should not be ACKed.
975 */
976 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
977 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
978 ack_APIC_irq();
979
980 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
981 if (last_warning+30*HZ < jiffies) {
982 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n",
983 smp_processor_id(), skipped);
984 last_warning = jiffies;
985 skipped = 0;
986 } else {
987 skipped++;
988 }
989 }
990
991 /*
992 * This interrupt should never happen with our APIC/SMP architecture
993 */
994
smp_error_interrupt(void)995 asmlinkage void smp_error_interrupt(void)
996 {
997 unsigned int v, v1;
998
999 /* First tickle the hardware, only then report what went on. -- REW */
1000 v = apic_read(APIC_ESR);
1001 apic_write(APIC_ESR, 0);
1002 v1 = apic_read(APIC_ESR);
1003 ack_APIC_irq();
1004 atomic_inc(&irq_err_count);
1005
1006 /* Here is what the APIC error bits mean:
1007 0: Send CS error
1008 1: Receive CS error
1009 2: Send accept error
1010 3: Receive accept error
1011 4: Reserved
1012 5: Send illegal vector
1013 6: Received illegal vector
1014 7: Illegal register address
1015 */
1016 printk (KERN_ERR "APIC error on CPU%d: %02x(%02x)\n",
1017 smp_processor_id(), v , v1);
1018 }
1019
1020 /*
1021 * This initializes the IO-APIC and APIC hardware if this is
1022 * a UP kernel.
1023 */
APIC_init_uniprocessor(void)1024 int __init APIC_init_uniprocessor (void)
1025 {
1026 if (apic_disabled)
1027 clear_bit(X86_FEATURE_APIC, &boot_cpu_data.x86_capability);
1028
1029 if (!cpu_has_apic) {
1030 printk("No APIC available.\n");
1031 apic_disabled = 1;
1032 return -1;
1033 }
1034
1035 /*
1036 * Complain if the BIOS pretends there is one.
1037 */
1038 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_id])) {
1039 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1040 boot_cpu_id);
1041 apic_disabled = 1;
1042 return -1;
1043 }
1044
1045 verify_local_APIC();
1046
1047 connect_bsp_APIC();
1048
1049 phys_cpu_present_map = 1;
1050 apic_write_around(APIC_ID, boot_cpu_id);
1051
1052 apic_pm_init2();
1053
1054 setup_local_APIC();
1055
1056 if (nmi_watchdog == NMI_LOCAL_APIC)
1057 check_nmi_watchdog();
1058 #ifdef CONFIG_X86_IO_APIC
1059 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1060 setup_IO_APIC();
1061 else
1062 nr_ioapics = 0;
1063 #endif
1064 setup_APIC_clocks();
1065
1066 return 0;
1067 }
1068
disable_local_apic(char * s)1069 static int disable_local_apic(char *s)
1070 {
1071 apic_disabled = 1;
1072 return 0;
1073 }
1074 __setup("nolocalapic", disable_local_apic);
1075
1076