1 /* sun4c_irq.c
2 * arch/sparc/kernel/sun4c_irq.c:
3 *
4 * djhr: Hacked out of irq.c into a CPU dependent version.
5 *
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
9 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
10 */
11
12 #include <linux/config.h>
13 #include <linux/ptrace.h>
14 #include <linux/errno.h>
15 #include <linux/linkage.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/signal.h>
18 #include <linux/sched.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/init.h>
22
23 #include <asm/ptrace.h>
24 #include <asm/processor.h>
25 #include <asm/system.h>
26 #include <asm/psr.h>
27 #include <asm/vaddrs.h>
28 #include <asm/timer.h>
29 #include <asm/openprom.h>
30 #include <asm/oplib.h>
31 #include <asm/traps.h>
32 #include <asm/irq.h>
33 #include <asm/io.h>
34 #include <asm/sun4paddr.h>
35 #include <asm/idprom.h>
36 #include <asm/machines.h>
37 #include <asm/sbus.h>
38
39 #if 0
40 static struct resource sun4c_timer_eb = { "sun4c_timer" };
41 static struct resource sun4c_intr_eb = { "sun4c_intr" };
42 #endif
43
44 /* Pointer to the interrupt enable byte
45 *
46 * Dave Redman (djhr@tadpole.co.uk)
47 * What you may not be aware of is that entry.S requires this variable.
48 *
49 * --- linux_trap_nmi_sun4c --
50 *
51 * so don't go making it static, like I tried. sigh.
52 */
53 unsigned char *interrupt_enable = 0;
54
55 static int sun4c_pil_map[] = { 0, 1, 2, 3, 5, 7, 8, 9 };
56
sun4c_sbint_to_irq(struct sbus_dev * sdev,unsigned int sbint)57 unsigned int sun4c_sbint_to_irq(struct sbus_dev *sdev, unsigned int sbint)
58 {
59 if (sbint >= sizeof(sun4c_pil_map)) {
60 printk(KERN_ERR "%s: bogus SBINT %d\n", sdev->prom_name, sbint);
61 BUG();
62 }
63 return sun4c_pil_map[sbint];
64 }
65
sun4c_disable_irq(unsigned int irq_nr)66 static void sun4c_disable_irq(unsigned int irq_nr)
67 {
68 unsigned long flags;
69 unsigned char current_mask, new_mask;
70
71 save_and_cli(flags);
72 irq_nr &= (NR_IRQS - 1);
73 current_mask = *interrupt_enable;
74 switch(irq_nr) {
75 case 1:
76 new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
77 break;
78 case 8:
79 new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
80 break;
81 case 10:
82 new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
83 break;
84 case 14:
85 new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
86 break;
87 default:
88 restore_flags(flags);
89 return;
90 }
91 *interrupt_enable = new_mask;
92 restore_flags(flags);
93 }
94
sun4c_enable_irq(unsigned int irq_nr)95 static void sun4c_enable_irq(unsigned int irq_nr)
96 {
97 unsigned long flags;
98 unsigned char current_mask, new_mask;
99
100 save_and_cli(flags);
101 irq_nr &= (NR_IRQS - 1);
102 current_mask = *interrupt_enable;
103 switch(irq_nr) {
104 case 1:
105 new_mask = ((current_mask) | SUN4C_INT_E1);
106 break;
107 case 8:
108 new_mask = ((current_mask) | SUN4C_INT_E8);
109 break;
110 case 10:
111 new_mask = ((current_mask) | SUN4C_INT_E10);
112 break;
113 case 14:
114 new_mask = ((current_mask) | SUN4C_INT_E14);
115 break;
116 default:
117 restore_flags(flags);
118 return;
119 }
120 *interrupt_enable = new_mask;
121 restore_flags(flags);
122 }
123
124 #define TIMER_IRQ 10 /* Also at level 14, but we ignore that one. */
125 #define PROFILE_IRQ 14 /* Level14 ticker.. used by OBP for polling */
126
127 volatile struct sun4c_timer_info *sun4c_timers;
128
129 #ifdef CONFIG_SUN4
130 /* This is an ugly hack to work around the
131 current timer code, and make it work with
132 the sun4/260 intersil
133 */
134 volatile struct sun4c_timer_info sun4_timer;
135 #endif
136
sun4c_clear_clock_irq(void)137 static void sun4c_clear_clock_irq(void)
138 {
139 volatile unsigned int clear_intr;
140 #ifdef CONFIG_SUN4
141 if (idprom->id_machtype == (SM_SUN4 | SM_4_260))
142 clear_intr = sun4_timer.timer_limit10;
143 else
144 #endif
145 clear_intr = sun4c_timers->timer_limit10;
146 }
147
sun4c_clear_profile_irq(int cpu)148 static void sun4c_clear_profile_irq(int cpu)
149 {
150 /* Errm.. not sure how to do this.. */
151 }
152
sun4c_load_profile_irq(int cpu,unsigned int limit)153 static void sun4c_load_profile_irq(int cpu, unsigned int limit)
154 {
155 /* Errm.. not sure how to do this.. */
156 }
157
sun4c_init_timers(void (* counter_fn)(int,void *,struct pt_regs *))158 static void __init sun4c_init_timers(void (*counter_fn)(int, void *, struct pt_regs *))
159 {
160 int irq;
161
162 /* Map the Timer chip, this is implemented in hardware inside
163 * the cache chip on the sun4c.
164 */
165 #ifdef CONFIG_SUN4
166 if (idprom->id_machtype == (SM_SUN4 | SM_4_260))
167 sun4c_timers = &sun4_timer;
168 else
169 #endif
170 sun4c_timers = ioremap(SUN_TIMER_PHYSADDR,
171 sizeof(struct sun4c_timer_info));
172
173 /* Have the level 10 timer tick at 100HZ. We don't touch the
174 * level 14 timer limit since we are letting the prom handle
175 * them until we have a real console driver so L1-A works.
176 */
177 sun4c_timers->timer_limit10 = (((1000000/HZ) + 1) << 10);
178 master_l10_counter = &sun4c_timers->cur_count10;
179 master_l10_limit = &sun4c_timers->timer_limit10;
180
181 irq = request_irq(TIMER_IRQ,
182 counter_fn,
183 (SA_INTERRUPT | SA_STATIC_ALLOC),
184 "timer", NULL);
185 if (irq) {
186 prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
187 prom_halt();
188 }
189
190 #if 0
191 /* This does not work on 4/330 */
192 sun4c_enable_irq(10);
193 #endif
194 claim_ticker14(NULL, PROFILE_IRQ, 0);
195 }
196
197 #ifdef CONFIG_SMP
sun4c_nop(void)198 static void sun4c_nop(void) {}
199 #endif
200
201 extern char *sun4m_irq_itoa(unsigned int irq);
202
sun4c_init_IRQ(void)203 void __init sun4c_init_IRQ(void)
204 {
205 struct linux_prom_registers int_regs[2];
206 int ie_node;
207
208 if (ARCH_SUN4) {
209 interrupt_enable = (char *)
210 ioremap(sun4_ie_physaddr, PAGE_SIZE);
211 } else {
212 struct resource phyres;
213
214 ie_node = prom_searchsiblings (prom_getchild(prom_root_node),
215 "interrupt-enable");
216 if(ie_node == 0)
217 panic("Cannot find /interrupt-enable node");
218
219 /* Depending on the "address" property is bad news... */
220 prom_getproperty(ie_node, "reg", (char *) int_regs, sizeof(int_regs));
221 memset(&phyres, 0, sizeof(struct resource));
222 phyres.flags = int_regs[0].which_io;
223 phyres.start = int_regs[0].phys_addr;
224 interrupt_enable = (char *) sbus_ioremap(&phyres, 0,
225 int_regs[0].reg_size, "sun4c_intr");
226 }
227
228 BTFIXUPSET_CALL(sbint_to_irq, sun4c_sbint_to_irq, BTFIXUPCALL_NORM);
229 BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
230 BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
231 BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
232 BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
233 BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
234 BTFIXUPSET_CALL(clear_profile_irq, sun4c_clear_profile_irq, BTFIXUPCALL_NOP);
235 BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
236 BTFIXUPSET_CALL(__irq_itoa, sun4m_irq_itoa, BTFIXUPCALL_NORM);
237 sparc_init_timers = sun4c_init_timers;
238 #ifdef CONFIG_SMP
239 BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
240 BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
241 BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
242 #endif
243 *interrupt_enable = (SUN4C_INT_ENABLE);
244 /* Cannot enable interrupts until OBP ticker is disabled. */
245 }
246