1 /* $Id: time.c,v 1.1.1.1.2.6 2003/07/16 18:43:55 yoshii Exp $
2 *
3 * linux/arch/sh/kernel/time.c
4 *
5 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
7 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
8 *
9 * Some code taken from i386 version.
10 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
11 */
12
13 #include <linux/config.h>
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
17 #include <linux/param.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/interrupt.h>
21 #include <linux/time.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/smp.h>
25
26 #include <asm/processor.h>
27 #include <asm/uaccess.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30 #include <asm/delay.h>
31 #include <asm/machvec.h>
32 #include <asm/rtc.h>
33 #ifdef CONFIG_SH_KGDB
34 #include <asm/kgdb.h>
35 #endif
36
37 #include <linux/timex.h>
38 #include <linux/irq.h>
39
40 #define TMU_TOCR_INIT 0x00 /* Don't output RTC clock */
41
42 #define TMU0_TCR_INIT 0x0020 /* Clock/4, rising edge; interrupt on */
43 #define TMU0_TCR_CALIB 0x0000 /* Clock/4, rising edge; no interrupt */
44 #define TMU0_TSTR_INIT 0x01 /* Bit to turn on TMU0 */
45
46 #define TMU1_TCR_INIT 0x0000 /* Clock/4, rising edge; no interrupt */
47 #define TMU1_TSTR_INIT 0x02 /* Bit to turn on TMU1 */
48
49 #if defined(__sh3__)
50 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
51 #define TMU_TSTR 0xA412FE92 /* Byte access */
52
53 #define TMU0_TCOR 0xA412FE94 /* Long access */
54 #define TMU0_TCNT 0xA412FE98 /* Long access */
55 #define TMU0_TCR 0xA412FE9C /* Word access */
56
57 #define TMU1_TCOR 0xA412FEA0 /* Long access */
58 #define TMU1_TCNT 0xA412FEA4 /* Long access */
59 #define TMU1_TCR 0xA412FEA8 /* Word access */
60
61 #define FRQCR 0xA415FF80
62 #else
63 #define TMU_TOCR 0xfffffe90 /* Byte access */
64 #define TMU_TSTR 0xfffffe92 /* Byte access */
65
66 #define TMU0_TCOR 0xfffffe94 /* Long access */
67 #define TMU0_TCNT 0xfffffe98 /* Long access */
68 #define TMU0_TCR 0xfffffe9c /* Word access */
69
70 #define TMU1_TCOR 0xfffffea0 /* Long access */
71 #define TMU1_TCNT 0xfffffea4 /* Long access */
72 #define TMU1_TCR 0xfffffea8 /* Word access */
73
74 #define FRQCR 0xffffff80
75 #endif
76 #elif defined(__SH4__)
77 #define TMU_TOCR 0xffd80000 /* Byte access */
78 #define TMU_TSTR 0xffd80004 /* Byte access */
79
80 #define TMU0_TCOR 0xffd80008 /* Long access */
81 #define TMU0_TCNT 0xffd8000c /* Long access */
82 #define TMU0_TCR 0xffd80010 /* Word access */
83
84 #define TMU1_TCOR 0xffd80014 /* Long access */
85 #define TMU1_TCNT 0xffd80018 /* Long access */
86 #define TMU1_TCR 0xffd8001c /* Word access */
87
88 #define FRQCR 0xffc00000
89
90 /* Core Processor Version Register */
91 #define CCN_PVR 0xff000030
92 #define CCN_PVR_CHIP_SHIFT 24
93 #define CCN_PVR_CHIP_MASK 0xff
94 #define CCN_PVR_CHIP_ST40STB1 0x4
95
96 #ifdef CONFIG_CPU_SUBTYPE_ST40
97 #define CLOCKGEN_MEMCLKCR 0xbb040038
98 #define MEMCLKCR_RATIO_MASK 0x7
99 #endif /* CONFIG_CPU_SUBTYPE_ST40 */
100 #endif /* __sh3__ or __SH4__ */
101
102 extern rwlock_t xtime_lock;
103 extern unsigned long wall_jiffies;
104 #define TICK_SIZE tick
105
do_gettimeoffset(void)106 static unsigned long do_gettimeoffset(void)
107 {
108 int count;
109
110 static int count_p = 0x7fffffff; /* for the first call after boot */
111 static unsigned long jiffies_p = 0;
112
113 /*
114 * cache volatile jiffies temporarily; we have IRQs turned off.
115 */
116 unsigned long jiffies_t;
117
118 /* timer count may underflow right here */
119 count = ctrl_inl(TMU0_TCNT); /* read the latched count */
120
121 jiffies_t = jiffies;
122
123 /*
124 * avoiding timer inconsistencies (they are rare, but they happen)...
125 * there is one kind of problem that must be avoided here:
126 * 1. the timer counter underflows
127 */
128
129 if( jiffies_t == jiffies_p ) {
130 if( count > count_p ) {
131 /* the nutcase */
132
133 if(ctrl_inw(TMU0_TCR) & 0x100) { /* Check UNF bit */
134 /*
135 * We cannot detect lost timer interrupts ...
136 * well, that's why we call them lost, don't we? :)
137 * [hmm, on the Pentium and Alpha we can ... sort of]
138 */
139 count -= LATCH;
140 } else {
141 printk("do_slow_gettimeoffset(): hardware timer problem?\n");
142 }
143 }
144 } else
145 jiffies_p = jiffies_t;
146
147 count_p = count;
148
149 count = ((LATCH-1) - count) * TICK_SIZE;
150 count = (count + LATCH/2) / LATCH;
151
152 return count;
153 }
154
do_gettimeofday(struct timeval * tv)155 void do_gettimeofday(struct timeval *tv)
156 {
157 unsigned long flags;
158 unsigned long usec, sec;
159
160 read_lock_irqsave(&xtime_lock, flags);
161 usec = do_gettimeoffset();
162 {
163 unsigned long lost = jiffies - wall_jiffies;
164 if (lost)
165 usec += lost * (1000000 / HZ);
166 }
167 sec = xtime.tv_sec;
168 usec += xtime.tv_usec;
169 read_unlock_irqrestore(&xtime_lock, flags);
170
171 while (usec >= 1000000) {
172 usec -= 1000000;
173 sec++;
174 }
175
176 tv->tv_sec = sec;
177 tv->tv_usec = usec;
178 }
179
do_settimeofday(struct timeval * tv)180 void do_settimeofday(struct timeval *tv)
181 {
182 write_lock_irq(&xtime_lock);
183 /*
184 * This is revolting. We need to set "xtime" correctly. However, the
185 * value in this location is the value at the most recent update of
186 * wall time. Discover what correction gettimeofday() would have
187 * made, and then undo it!
188 */
189 tv->tv_usec -= do_gettimeoffset();
190 tv->tv_usec -= (jiffies - wall_jiffies) * (1000000 / HZ);
191
192 while (tv->tv_usec < 0) {
193 tv->tv_usec += 1000000;
194 tv->tv_sec--;
195 }
196
197 xtime = *tv;
198 time_adjust = 0; /* stop active adjtime() */
199 time_status |= STA_UNSYNC;
200 time_maxerror = NTP_PHASE_LIMIT;
201 time_esterror = NTP_PHASE_LIMIT;
202 write_unlock_irq(&xtime_lock);
203 }
204
205 /* last time the RTC clock got updated */
206 static long last_rtc_update;
207
sh_do_profile(unsigned long pc)208 static __inline__ void sh_do_profile (unsigned long pc)
209 {
210 extern int _stext;
211
212 if (!prof_buffer)
213 return;
214
215 if(pc >= 0xa0000000UL && pc < 0xc0000000UL)
216 pc -= 0x20000000;
217 pc -= (unsigned long) &_stext;
218 pc >>= prof_shift;
219 /*
220 * Don't ignore out-of-bounds PC values silently,
221 * put them into the last histogram slot, so if
222 * present, they will show up as a sharp peak.
223 */
224 if (pc > prof_len-1)
225 pc = prof_len-1;
226 prof_buffer[pc]++;
227 }
228
229 /*
230 * timer_interrupt() needs to keep up the real-time clock,
231 * as well as call the "do_timer()" routine every clocktick
232 */
do_timer_interrupt(int irq,void * dev_id,struct pt_regs * regs)233 static inline void do_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
234 {
235 do_timer(regs);
236
237 if (!user_mode(regs))
238 sh_do_profile(regs->pc);
239
240 #ifdef CONFIG_HEARTBEAT
241 if (sh_mv.mv_heartbeat != NULL)
242 sh_mv.mv_heartbeat();
243 #endif
244
245 /*
246 * If we have an externally synchronized Linux clock, then update
247 * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
248 * called as close as possible to 500 ms before the new second starts.
249 */
250 if ((time_status & STA_UNSYNC) == 0 &&
251 xtime.tv_sec > last_rtc_update + 660 &&
252 xtime.tv_usec >= 500000 - ((unsigned) tick) / 2 &&
253 xtime.tv_usec <= 500000 + ((unsigned) tick) / 2) {
254 if (sh_mv.mv_rtc_settimeofday(&xtime) == 0)
255 last_rtc_update = xtime.tv_sec;
256 else
257 last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
258 }
259 }
260
261 /*
262 * This is the same as the above, except we _also_ save the current
263 * Time Stamp Counter value at the time of the timer interrupt, so that
264 * we later on can estimate the time of day more exactly.
265 */
timer_interrupt(int irq,void * dev_id,struct pt_regs * regs)266 static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
267 {
268 unsigned long timer_status;
269
270 /* Clear UNF bit */
271 timer_status = ctrl_inw(TMU0_TCR);
272 timer_status &= ~0x100;
273 ctrl_outw(timer_status, TMU0_TCR);
274
275 /*
276 * Here we are in the timer irq handler. We just have irqs locally
277 * disabled but we don't know if the timer_bh is running on the other
278 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
279 * the irq version of write_lock because as just said we have irq
280 * locally disabled. -arca
281 */
282 write_lock(&xtime_lock);
283 do_timer_interrupt(irq, NULL, regs);
284 write_unlock(&xtime_lock);
285 }
286
get_timer_frequency(void)287 static unsigned int __init get_timer_frequency(void)
288 {
289 u32 freq;
290 struct timeval tv1, tv2;
291 unsigned long diff_usec;
292 unsigned long factor;
293
294 /* Setup the timer: We don't want to generate interrupts, just
295 * have it count down at its natural rate.
296 */
297 ctrl_outb(0, TMU_TSTR);
298 #if !defined(CONFIG_CPU_SUBTYPE_SH7300)
299 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
300 #endif
301 ctrl_outw(TMU0_TCR_CALIB, TMU0_TCR);
302 ctrl_outl(0xffffffff, TMU0_TCOR);
303 ctrl_outl(0xffffffff, TMU0_TCNT);
304
305 rtc_gettimeofday(&tv2);
306
307 do {
308 rtc_gettimeofday(&tv1);
309 } while (tv1.tv_usec == tv2.tv_usec && tv1.tv_sec == tv2.tv_sec);
310
311 /* actually start the timer */
312 ctrl_outb(TMU0_TSTR_INIT, TMU_TSTR);
313
314 do {
315 rtc_gettimeofday(&tv2);
316 } while (tv1.tv_usec == tv2.tv_usec && tv1.tv_sec == tv2.tv_sec);
317
318 freq = 0xffffffff - ctrl_inl(TMU0_TCNT);
319 if (tv2.tv_usec < tv1.tv_usec) {
320 tv2.tv_usec += 1000000;
321 tv2.tv_sec--;
322 }
323
324 diff_usec = (tv2.tv_sec - tv1.tv_sec) * 1000000 + (tv2.tv_usec - tv1.tv_usec);
325
326 /* this should work well if the RTC has a precision of n Hz, where
327 * n is an integer. I don't think we have to worry about the other
328 * cases. */
329 factor = (1000000 + diff_usec/2) / diff_usec;
330
331 if (factor * diff_usec > 1100000 ||
332 factor * diff_usec < 900000)
333 panic("weird RTC (diff_usec %ld)", diff_usec);
334
335 return freq * factor;
336 }
337
338 static unsigned int sh_pclk_freq __initdata = CONFIG_SH_PCLK_FREQ;
sh_pclk_setup(char * str)339 static int __init sh_pclk_setup(char *str)
340 {
341 unsigned int freq;
342 if (get_option(&str, &freq))
343 sh_pclk_freq = freq;
344 return 1;
345 }
346 __setup("sh_pclk=", sh_pclk_setup);
347
348 static struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL};
349
time_init(void)350 void __init time_init(void)
351 {
352 unsigned int cpu_clock, master_clock, bus_clock, module_clock;
353 #ifdef CONFIG_CPU_SUBTYPE_ST40
354 unsigned int memory_clock;
355 #endif
356 unsigned int timer_freq;
357 unsigned short frqcr, ifc, pfc, bfc;
358 unsigned long interval;
359 #if defined(__sh3__)
360 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
361 static int pfc_table[] = { 1, 2, 3, 4, 6 };
362 #else
363 static int ifc_table[] = { 1, 2, 4, 1, 3, 1, 1, 1 };
364 static int pfc_table[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
365 static int stc_table[] = { 1, 2, 4, 8, 3, 6, 1, 1 };
366 #endif
367 #elif defined(__SH4__)
368 static int ifc_table[] = { 1, 2, 3, 4, 6, 8, 1, 1 };
369 #define bfc_table ifc_table /* Same */
370 static int pfc_table[] = { 2, 3, 4, 6, 8, 2, 2, 2 };
371
372 #ifdef CONFIG_CPU_SUBTYPE_ST40
373 struct frqcr_data {
374 unsigned short frqcr;
375 struct {
376 unsigned char multiplier;
377 unsigned char divisor;
378 } factor[3];
379 };
380
381 static struct frqcr_data st40_frqcr_table[] = {
382 { 0x000, {{1,1}, {1,1}, {1,2}}},
383 { 0x002, {{1,1}, {1,1}, {1,4}}},
384 { 0x004, {{1,1}, {1,1}, {1,8}}},
385 { 0x008, {{1,1}, {1,2}, {1,2}}},
386 { 0x00A, {{1,1}, {1,2}, {1,4}}},
387 { 0x00C, {{1,1}, {1,2}, {1,8}}},
388 { 0x011, {{1,1}, {2,3}, {1,6}}},
389 { 0x013, {{1,1}, {2,3}, {1,3}}},
390 { 0x01A, {{1,1}, {1,2}, {1,4}}},
391 { 0x01C, {{1,1}, {1,2}, {1,8}}},
392 { 0x023, {{1,1}, {2,3}, {1,3}}},
393 { 0x02C, {{1,1}, {1,2}, {1,8}}},
394 { 0x048, {{1,2}, {1,2}, {1,4}}},
395 { 0x04A, {{1,2}, {1,2}, {1,6}}},
396 { 0x04C, {{1,2}, {1,2}, {1,8}}},
397 { 0x05A, {{1,2}, {1,3}, {1,6}}},
398 { 0x05C, {{1,2}, {1,3}, {1,6}}},
399 { 0x063, {{1,2}, {1,4}, {1,4}}},
400 { 0x06C, {{1,2}, {1,4}, {1,8}}},
401 { 0x091, {{1,3}, {1,3}, {1,6}}},
402 { 0x093, {{1,3}, {1,3}, {1,6}}},
403 { 0x0A3, {{1,3}, {1,6}, {1,6}}},
404 { 0x0DA, {{1,4}, {1,4}, {1,8}}},
405 { 0x0DC, {{1,4}, {1,4}, {1,8}}},
406 { 0x0EC, {{1,4}, {1,8}, {1,8}}},
407 { 0x123, {{1,4}, {1,4}, {1,8}}},
408 { 0x16C, {{1,4}, {1,8}, {1,8}}},
409 };
410
411 struct memclk_data {
412 unsigned char multiplier;
413 unsigned char divisor;
414 };
415 static struct memclk_data st40_memclk_table[8] = {
416 {1,1}, // 000
417 {1,2}, // 001
418 {1,3}, // 010
419 {2,3}, // 011
420 {1,4}, // 100
421 {1,6}, // 101
422 {1,8}, // 110
423 {1,8} // 111
424 };
425 #endif
426 #endif
427
428 if(rtc_gettimeofday)
429 rtc_gettimeofday(&xtime);
430 else{
431 xtime.tv_sec = mktime(2000, 1, 1, 0, 0, 0);
432 xtime.tv_usec = 0;
433 }
434
435 setup_irq(TIMER_IRQ, &irq0);
436
437 if( sh_pclk_freq ){
438 module_clock = sh_pclk_freq;
439 }else{
440 timer_freq = get_timer_frequency();
441 module_clock = timer_freq * 4;
442 }
443
444 #if defined(__sh3__)
445 {
446 unsigned short tmp;
447
448 frqcr = ctrl_inw(FRQCR);
449 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
450 bfc = ((frqcr & 0x0700) >> 8)+1;
451 ifc = ((frqcr & 0x0070) >> 4)+1;
452 tmp = frqcr & 0x0007;
453 pfc = pfc_table[tmp];
454 #else
455 tmp = (frqcr & 0x8000) >> 13;
456 tmp |= (frqcr & 0x0030) >> 4;
457 bfc = stc_table[tmp];
458 tmp = (frqcr & 0x4000) >> 12;
459 tmp |= (frqcr & 0x000c) >> 2;
460 ifc = ifc_table[tmp];
461 tmp = (frqcr & 0x2000) >> 11;
462 tmp |= frqcr & 0x0003;
463 pfc = pfc_table[tmp];
464 #endif
465 }
466 #elif defined(__SH4__)
467 {
468 #ifdef CONFIG_CPU_SUBTYPE_ST40
469 unsigned long pvr;
470
471 /* This should probably be moved into the SH3 probing code, and then use the processor
472 * structure to determine which CPU we are running on.
473 */
474 pvr = ctrl_inl(CCN_PVR);
475 printk("PVR %08x\n", pvr);
476
477 if (((pvr >>CCN_PVR_CHIP_SHIFT) & CCN_PVR_CHIP_MASK) == CCN_PVR_CHIP_ST40STB1) {
478 /* Unfortunatly the STB1 FRQCR values are different from the 7750 ones */
479 struct frqcr_data *d;
480 int a;
481 unsigned long memclkcr;
482 struct memclk_data *e;
483
484 for (a=0; a<ARRAY_SIZE(st40_frqcr_table); a++) {
485 d = &st40_frqcr_table[a];
486 if (d->frqcr == (frqcr & 0x1ff))
487 break;
488 }
489 if (a == ARRAY_SIZE(st40_frqcr_table)) {
490 d = st40_frqcr_table;
491 printk("ERROR: Unrecognised FRQCR value, using default multipliers\n");
492 }
493
494 memclkcr = ctrl_inl(CLOCKGEN_MEMCLKCR);
495 e = &st40_memclk_table[memclkcr & MEMCLKCR_RATIO_MASK];
496
497 printk("Clock multipliers: CPU: %d/%d Bus: %d/%d Mem: %d/%d Periph: %d/%d\n",
498 d->factor[0].multiplier, d->factor[0].divisor,
499 d->factor[1].multiplier, d->factor[1].divisor,
500 e->multiplier, e->divisor,
501 d->factor[2].multiplier, d->factor[2].divisor);
502
503 master_clock = module_clock * d->factor[2].divisor / d->factor[2].multiplier;
504 bus_clock = master_clock * d->factor[1].multiplier / d->factor[1].divisor;
505 memory_clock = master_clock * e->multiplier / e->divisor;
506 cpu_clock = master_clock * d->factor[0].multiplier / d->factor[0].divisor;
507 goto skip_calc;
508 } else
509 #endif
510 {
511 frqcr = ctrl_inw(FRQCR);
512
513 ifc = ifc_table[(frqcr>> 6) & 0x0007];
514 bfc = bfc_table[(frqcr>> 3) & 0x0007];
515 pfc = pfc_table[frqcr & 0x0007];
516 }
517 }
518 #endif
519 master_clock = module_clock * pfc;
520 bus_clock = master_clock / bfc;
521 cpu_clock = master_clock / ifc;
522 #ifdef CONFIG_CPU_SUBTYPE_ST40
523 skip_calc:
524 #endif
525 printk("CPU clock: %d.%02dMHz\n",
526 (cpu_clock / 1000000), (cpu_clock % 1000000)/10000);
527 printk("Bus clock: %d.%02dMHz\n",
528 (bus_clock/1000000), (bus_clock % 1000000)/10000);
529 #ifdef CONFIG_CPU_SUBTYPE_ST40
530 printk("Memory clock: %d.%02dMHz\n",
531 (memory_clock/1000000), (memory_clock % 1000000)/10000);
532 #endif
533 printk("Module clock: %d.%02dMHz\n",
534 (module_clock/1000000), (module_clock % 1000000)/10000);
535 interval = (module_clock/4 + HZ/2) / HZ;
536
537 printk("Interval = %ld\n", interval);
538
539 current_cpu_data.cpu_clock = cpu_clock;
540 current_cpu_data.master_clock = master_clock;
541 current_cpu_data.bus_clock = bus_clock;
542 #ifdef CONFIG_CPU_SUBTYPE_ST40
543 current_cpu_data.memory_clock = memory_clock;
544 #endif
545 current_cpu_data.module_clock = module_clock;
546
547 /* Stop all timers */
548 ctrl_outb(0, TMU_TSTR);
549 #if !defined(CONFIG_CPU_SUBTYPE_SH7300)
550 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
551 #endif
552
553 /* Start TMU0 (jiffy interrupts) */
554 ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
555 ctrl_outl(interval, TMU0_TCOR);
556 ctrl_outl(interval, TMU0_TCNT);
557 ctrl_outb(TMU0_TSTR_INIT, TMU_TSTR);
558
559 #if defined(CONFIG_START_TMU1)
560 /* Start TMU1 (free-running) */
561 ctrl_outw(TMU1_TCR_INIT, TMU1_TCR);
562 ctrl_outl(0xffffffff, TMU1_TCOR);
563 ctrl_outl(0xffffffff, TMU1_TCNT);
564 ctrl_outb((ctrl_inb(TMU_TSTR) | TMU1_TSTR_INIT), TMU_TSTR);
565 #endif
566
567 #if defined(CONFIG_SH_KGDB)
568 /*
569 * Set up kgdb as requested. We do it here because the serial
570 * init uses the timer vars we just set up for figuring baud.
571 */
572 kgdb_init();
573 #endif
574
575 }
576