1 /*
2 * $Id: pcibios.c,v 1.1 2001/08/24 12:38:19 dwmw2 Exp $
3 *
4 * arch/sh/kernel/pcibios.c
5 *
6 * This is GPL'd.
7 *
8 * Provided here are generic versions of:
9 * pcibios_update_resource()
10 * pcibios_align_resource()
11 * pcibios_enable_device()
12 * pcibios_set_master()
13 * pcibios_update_irq()
14 *
15 * These functions are collected here to reduce duplication of common
16 * code amongst the many platform-specific PCI support code files.
17 *
18 * Platform-specific files are expected to provide:
19 * pcibios_fixup_bus()
20 * pcibios_init()
21 * pcibios_setup()
22 * pcibios_fixup_pbus_ranges()
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28
29 void
pcibios_update_resource(struct pci_dev * dev,struct resource * root,struct resource * res,int resource)30 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
31 struct resource *res, int resource)
32 {
33 u32 new, check;
34 int reg;
35
36 new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
37 if (resource < 6) {
38 reg = PCI_BASE_ADDRESS_0 + 4*resource;
39 } else if (resource == PCI_ROM_RESOURCE) {
40 res->flags |= PCI_ROM_ADDRESS_ENABLE;
41 new |= PCI_ROM_ADDRESS_ENABLE;
42 reg = dev->rom_base_reg;
43 } else {
44 /* Somebody might have asked allocation of a non-standard resource */
45 return;
46 }
47
48 pci_write_config_dword(dev, reg, new);
49 pci_read_config_dword(dev, reg, &check);
50 if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
51 printk(KERN_ERR "PCI: Error while updating region "
52 "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
53 new, check);
54 }
55 }
56
57 /*
58 * We need to avoid collisions with `mirrored' VGA ports
59 * and other strange ISA hardware, so we always want the
60 * addresses to be allocated in the 0x000-0x0ff region
61 * modulo 0x400.
62 */
pcibios_align_resource(void * data,struct resource * res,unsigned long size,unsigned long align)63 void pcibios_align_resource(void *data, struct resource *res,
64 unsigned long size, unsigned long align)
65 {
66 if (res->flags & IORESOURCE_IO) {
67 unsigned long start = res->start;
68
69 if (start & 0x300) {
70 start = (start + 0x3ff) & ~0x3ff;
71 res->start = start;
72 }
73 }
74 }
75
pcibios_enable_device(struct pci_dev * dev,int mask)76 int pcibios_enable_device(struct pci_dev *dev, int mask)
77 {
78 u16 cmd, old_cmd;
79 int idx;
80 struct resource *r;
81
82 pci_read_config_word(dev, PCI_COMMAND, &cmd);
83 old_cmd = cmd;
84 for(idx=0; idx<6; idx++) {
85 if (!(mask & (1 << idx)))
86 continue;
87 r = &dev->resource[idx];
88 if (!r->start && r->end) {
89 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name);
90 return -EINVAL;
91 }
92 if (r->flags & IORESOURCE_IO)
93 cmd |= PCI_COMMAND_IO;
94 if (r->flags & IORESOURCE_MEM)
95 cmd |= PCI_COMMAND_MEMORY;
96 }
97 if (dev->resource[PCI_ROM_RESOURCE].start)
98 cmd |= PCI_COMMAND_MEMORY;
99 if (cmd != old_cmd) {
100 printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n", dev->name, old_cmd, cmd);
101 pci_write_config_word(dev, PCI_COMMAND, cmd);
102 }
103 return 0;
104 }
105
106 /*
107 * If we set up a device for bus mastering, we need to check and set
108 * the latency timer as it may not be properly set.
109 */
110 unsigned int pcibios_max_latency = 255;
111
pcibios_set_master(struct pci_dev * dev)112 void pcibios_set_master(struct pci_dev *dev)
113 {
114 u8 lat;
115 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
116 if (lat < 16)
117 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
118 else if (lat > pcibios_max_latency)
119 lat = pcibios_max_latency;
120 else
121 return;
122 printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n", dev->name, lat);
123 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
124 }
125
pcibios_update_irq(struct pci_dev * dev,int irq)126 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
127 {
128 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
129 }
130