1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 2, or (at your option) any later version.
11
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21 #include <linux/posix_types.h>
22 #include "ansidecl.h"
23 #include "ppc.h"
24
25 /* This file holds the PowerPC opcode table. The opcode table
26 includes almost all of the extended instruction mnemonics. This
27 permits the disassembler to use them, and simplifies the assembler
28 logic, at the cost of increasing the table size. The table is
29 strictly constant data, so the compiler should be able to put it in
30 the .text section.
31
32 This file also holds the operand table. All knowledge about
33 inserting operands into instructions and vice-versa is kept in this
34 file. */
35
36 /* Local insertion and extraction functions. */
37
38 static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
39 static long extract_bat PARAMS ((unsigned long, int *));
40 static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
41 static long extract_bba PARAMS ((unsigned long, int *));
42 static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
43 static long extract_bd PARAMS ((unsigned long, int *));
44 static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
45 static long extract_bdm PARAMS ((unsigned long, int *));
46 static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
47 static long extract_bdp PARAMS ((unsigned long, int *));
48 static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
49 static long extract_bo PARAMS ((unsigned long, int *));
50 static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
51 static long extract_boe PARAMS ((unsigned long, int *));
52 static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
53 static long extract_ds PARAMS ((unsigned long, int *));
54 static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
55 static long extract_li PARAMS ((unsigned long, int *));
56 static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
57 static long extract_mbe PARAMS ((unsigned long, int *));
58 static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
59 static long extract_mb6 PARAMS ((unsigned long, int *));
60 static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
61 static long extract_nb PARAMS ((unsigned long, int *));
62 static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
63 static long extract_nsi PARAMS ((unsigned long, int *));
64 static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
65 static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
66 static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
67 static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
68 static long extract_rbs PARAMS ((unsigned long, int *));
69 static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
70 static long extract_sh6 PARAMS ((unsigned long, int *));
71 static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
72 static long extract_spr PARAMS ((unsigned long, int *));
73 static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
74 static long extract_tbr PARAMS ((unsigned long, int *));
75
76 /* The operands table.
77
78 The fields are bits, shift, signed, insert, extract, flags. */
79
80 const struct powerpc_operand powerpc_operands[] =
81 {
82 /* The zero index is used to indicate the end of the list of
83 operands. */
84 #define UNUSED (0)
85 { 0, 0, 0, 0, 0 },
86
87 /* The BA field in an XL form instruction. */
88 #define BA (1)
89 #define BA_MASK (0x1f << 16)
90 { 5, 16, 0, 0, PPC_OPERAND_CR },
91
92 /* The BA field in an XL form instruction when it must be the same
93 as the BT field in the same instruction. */
94 #define BAT (2)
95 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
96
97 /* The BB field in an XL form instruction. */
98 #define BB (3)
99 #define BB_MASK (0x1f << 11)
100 { 5, 11, 0, 0, PPC_OPERAND_CR },
101
102 /* The BB field in an XL form instruction when it must be the same
103 as the BA field in the same instruction. */
104 #define BBA (4)
105 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
106
107 /* The BD field in a B form instruction. The lower two bits are
108 forced to zero. */
109 #define BD (5)
110 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
111
112 /* The BD field in a B form instruction when absolute addressing is
113 used. */
114 #define BDA (6)
115 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
116
117 /* The BD field in a B form instruction when the - modifier is used.
118 This sets the y bit of the BO field appropriately. */
119 #define BDM (7)
120 { 16, 0, insert_bdm, extract_bdm,
121 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
122
123 /* The BD field in a B form instruction when the - modifier is used
124 and absolute address is used. */
125 #define BDMA (8)
126 { 16, 0, insert_bdm, extract_bdm,
127 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
128
129 /* The BD field in a B form instruction when the + modifier is used.
130 This sets the y bit of the BO field appropriately. */
131 #define BDP (9)
132 { 16, 0, insert_bdp, extract_bdp,
133 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
134
135 /* The BD field in a B form instruction when the + modifier is used
136 and absolute addressing is used. */
137 #define BDPA (10)
138 { 16, 0, insert_bdp, extract_bdp,
139 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
140
141 /* The BF field in an X or XL form instruction. */
142 #define BF (11)
143 { 3, 23, 0, 0, PPC_OPERAND_CR },
144
145 /* An optional BF field. This is used for comparison instructions,
146 in which an omitted BF field is taken as zero. */
147 #define OBF (12)
148 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
149
150 /* The BFA field in an X or XL form instruction. */
151 #define BFA (13)
152 { 3, 18, 0, 0, PPC_OPERAND_CR },
153
154 /* The BI field in a B form or XL form instruction. */
155 #define BI (14)
156 #define BI_MASK (0x1f << 16)
157 { 5, 16, 0, 0, PPC_OPERAND_CR },
158
159 /* The BO field in a B form instruction. Certain values are
160 illegal. */
161 #define BO (15)
162 #define BO_MASK (0x1f << 21)
163 { 5, 21, insert_bo, extract_bo, 0 },
164
165 /* The BO field in a B form instruction when the + or - modifier is
166 used. This is like the BO field, but it must be even. */
167 #define BOE (16)
168 { 5, 21, insert_boe, extract_boe, 0 },
169
170 /* The BT field in an X or XL form instruction. */
171 #define BT (17)
172 { 5, 21, 0, 0, PPC_OPERAND_CR },
173
174 /* The condition register number portion of the BI field in a B form
175 or XL form instruction. This is used for the extended
176 conditional branch mnemonics, which set the lower two bits of the
177 BI field. This field is optional. */
178 #define CR (18)
179 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
180
181 /* The D field in a D form instruction. This is a displacement off
182 a register, and implies that the next operand is a register in
183 parentheses. */
184 #define D (19)
185 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
186
187 /* The DS field in a DS form instruction. This is like D, but the
188 lower two bits are forced to zero. */
189 #define DS (20)
190 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
191
192 /* The FL1 field in a POWER SC form instruction. */
193 #define FL1 (21)
194 { 4, 12, 0, 0, 0 },
195
196 /* The FL2 field in a POWER SC form instruction. */
197 #define FL2 (22)
198 { 3, 2, 0, 0, 0 },
199
200 /* The FLM field in an XFL form instruction. */
201 #define FLM (23)
202 { 8, 17, 0, 0, 0 },
203
204 /* The FRA field in an X or A form instruction. */
205 #define FRA (24)
206 #define FRA_MASK (0x1f << 16)
207 { 5, 16, 0, 0, PPC_OPERAND_FPR },
208
209 /* The FRB field in an X or A form instruction. */
210 #define FRB (25)
211 #define FRB_MASK (0x1f << 11)
212 { 5, 11, 0, 0, PPC_OPERAND_FPR },
213
214 /* The FRC field in an A form instruction. */
215 #define FRC (26)
216 #define FRC_MASK (0x1f << 6)
217 { 5, 6, 0, 0, PPC_OPERAND_FPR },
218
219 /* The FRS field in an X form instruction or the FRT field in a D, X
220 or A form instruction. */
221 #define FRS (27)
222 #define FRT (FRS)
223 { 5, 21, 0, 0, PPC_OPERAND_FPR },
224
225 /* The FXM field in an XFX instruction. */
226 #define FXM (28)
227 #define FXM_MASK (0xff << 12)
228 { 8, 12, 0, 0, 0 },
229
230 /* The L field in a D or X form instruction. */
231 #define L (29)
232 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
233
234 /* The LEV field in a POWER SC form instruction. */
235 #define LEV (30)
236 { 7, 5, 0, 0, 0 },
237
238 /* The LI field in an I form instruction. The lower two bits are
239 forced to zero. */
240 #define LI (31)
241 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
242
243 /* The LI field in an I form instruction when used as an absolute
244 address. */
245 #define LIA (32)
246 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
247
248 /* The MB field in an M form instruction. */
249 #define MB (33)
250 #define MB_MASK (0x1f << 6)
251 { 5, 6, 0, 0, 0 },
252
253 /* The ME field in an M form instruction. */
254 #define ME (34)
255 #define ME_MASK (0x1f << 1)
256 { 5, 1, 0, 0, 0 },
257
258 /* The MB and ME fields in an M form instruction expressed a single
259 operand which is a bitmask indicating which bits to select. This
260 is a two operand form using PPC_OPERAND_NEXT. See the
261 description in opcode/ppc.h for what this means. */
262 #define MBE (35)
263 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
264 { 32, 0, insert_mbe, extract_mbe, 0 },
265
266 /* The MB or ME field in an MD or MDS form instruction. The high
267 bit is wrapped to the low end. */
268 #define MB6 (37)
269 #define ME6 (MB6)
270 #define MB6_MASK (0x3f << 5)
271 { 6, 5, insert_mb6, extract_mb6, 0 },
272
273 /* The NB field in an X form instruction. The value 32 is stored as
274 0. */
275 #define NB (38)
276 { 6, 11, insert_nb, extract_nb, 0 },
277
278 /* The NSI field in a D form instruction. This is the same as the
279 SI field, only negated. */
280 #define NSI (39)
281 { 16, 0, insert_nsi, extract_nsi,
282 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
283
284 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
285 #define RA (40)
286 #define RA_MASK (0x1f << 16)
287 { 5, 16, 0, 0, PPC_OPERAND_GPR },
288
289 /* The RA field in a D or X form instruction which is an updating
290 load, which means that the RA field may not be zero and may not
291 equal the RT field. */
292 #define RAL (41)
293 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
294
295 /* The RA field in an lmw instruction, which has special value
296 restrictions. */
297 #define RAM (42)
298 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
299
300 /* The RA field in a D or X form instruction which is an updating
301 store or an updating floating point load, which means that the RA
302 field may not be zero. */
303 #define RAS (43)
304 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
305
306 /* The RB field in an X, XO, M, or MDS form instruction. */
307 #define RB (44)
308 #define RB_MASK (0x1f << 11)
309 { 5, 11, 0, 0, PPC_OPERAND_GPR },
310
311 /* The RB field in an X form instruction when it must be the same as
312 the RS field in the instruction. This is used for extended
313 mnemonics like mr. */
314 #define RBS (45)
315 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
316
317 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
318 instruction or the RT field in a D, DS, X, XFX or XO form
319 instruction. */
320 #define RS (46)
321 #define RT (RS)
322 #define RT_MASK (0x1f << 21)
323 { 5, 21, 0, 0, PPC_OPERAND_GPR },
324
325 /* The SH field in an X or M form instruction. */
326 #define SH (47)
327 #define SH_MASK (0x1f << 11)
328 { 5, 11, 0, 0, 0 },
329
330 /* The SH field in an MD form instruction. This is split. */
331 #define SH6 (48)
332 #define SH6_MASK ((0x1f << 11) | (1 << 1))
333 { 6, 1, insert_sh6, extract_sh6, 0 },
334
335 /* The SI field in a D form instruction. */
336 #define SI (49)
337 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
338
339 /* The SI field in a D form instruction when we accept a wide range
340 of positive values. */
341 #define SISIGNOPT (50)
342 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
343
344 /* The SPR field in an XFX form instruction. This is flipped--the
345 lower 5 bits are stored in the upper 5 and vice- versa. */
346 #define SPR (51)
347 #define SPR_MASK (0x3ff << 11)
348 { 10, 11, insert_spr, extract_spr, 0 },
349
350 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
351 #define SPRBAT (52)
352 #define SPRBAT_MASK (0x3 << 17)
353 { 2, 17, 0, 0, 0 },
354
355 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
356 #define SPRG (53)
357 #define SPRG_MASK (0x3 << 16)
358 { 2, 16, 0, 0, 0 },
359
360 /* The SR field in an X form instruction. */
361 #define SR (54)
362 { 4, 16, 0, 0, 0 },
363
364 /* The SV field in a POWER SC form instruction. */
365 #define SV (55)
366 { 14, 2, 0, 0, 0 },
367
368 /* The TBR field in an XFX form instruction. This is like the SPR
369 field, but it is optional. */
370 #define TBR (56)
371 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
372
373 /* The TO field in a D or X form instruction. */
374 #define TO (57)
375 #define TO_MASK (0x1f << 21)
376 { 5, 21, 0, 0, 0 },
377
378 /* The U field in an X form instruction. */
379 #define U (58)
380 { 4, 12, 0, 0, 0 },
381
382 /* The UI field in a D form instruction. */
383 #define UI (59)
384 { 16, 0, 0, 0, 0 },
385 };
386
387 /* The functions used to insert and extract complicated operands. */
388
389 /* The BA field in an XL form instruction when it must be the same as
390 the BT field in the same instruction. This operand is marked FAKE.
391 The insertion function just copies the BT field into the BA field,
392 and the extraction function just checks that the fields are the
393 same. */
394
395 /*ARGSUSED*/
396 static unsigned long
insert_bat(insn,value,errmsg)397 insert_bat (insn, value, errmsg)
398 unsigned long insn;
399 long value;
400 const char **errmsg;
401 {
402 return insn | (((insn >> 21) & 0x1f) << 16);
403 }
404
405 static long
extract_bat(insn,invalid)406 extract_bat (insn, invalid)
407 unsigned long insn;
408 int *invalid;
409 {
410 if (invalid != (int *) NULL
411 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
412 *invalid = 1;
413 return 0;
414 }
415
416 /* The BB field in an XL form instruction when it must be the same as
417 the BA field in the same instruction. This operand is marked FAKE.
418 The insertion function just copies the BA field into the BB field,
419 and the extraction function just checks that the fields are the
420 same. */
421
422 /*ARGSUSED*/
423 static unsigned long
insert_bba(insn,value,errmsg)424 insert_bba (insn, value, errmsg)
425 unsigned long insn;
426 long value;
427 const char **errmsg;
428 {
429 return insn | (((insn >> 16) & 0x1f) << 11);
430 }
431
432 static long
extract_bba(insn,invalid)433 extract_bba (insn, invalid)
434 unsigned long insn;
435 int *invalid;
436 {
437 if (invalid != (int *) NULL
438 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
439 *invalid = 1;
440 return 0;
441 }
442
443 /* The BD field in a B form instruction. The lower two bits are
444 forced to zero. */
445
446 /*ARGSUSED*/
447 static unsigned long
insert_bd(insn,value,errmsg)448 insert_bd (insn, value, errmsg)
449 unsigned long insn;
450 long value;
451 const char **errmsg;
452 {
453 return insn | (value & 0xfffc);
454 }
455
456 /*ARGSUSED*/
457 static long
extract_bd(insn,invalid)458 extract_bd (insn, invalid)
459 unsigned long insn;
460 int *invalid;
461 {
462 if ((insn & 0x8000) != 0)
463 return (insn & 0xfffc) - 0x10000;
464 else
465 return insn & 0xfffc;
466 }
467
468 /* The BD field in a B form instruction when the - modifier is used.
469 This modifier means that the branch is not expected to be taken.
470 We must set the y bit of the BO field to 1 if the offset is
471 negative. When extracting, we require that the y bit be 1 and that
472 the offset be positive, since if the y bit is 0 we just want to
473 print the normal form of the instruction. */
474
475 /*ARGSUSED*/
476 static unsigned long
insert_bdm(insn,value,errmsg)477 insert_bdm (insn, value, errmsg)
478 unsigned long insn;
479 long value;
480 const char **errmsg;
481 {
482 if ((value & 0x8000) != 0)
483 insn |= 1 << 21;
484 return insn | (value & 0xfffc);
485 }
486
487 static long
extract_bdm(insn,invalid)488 extract_bdm (insn, invalid)
489 unsigned long insn;
490 int *invalid;
491 {
492 if (invalid != (int *) NULL
493 && ((insn & (1 << 21)) == 0
494 || (insn & (1 << 15)) == 0))
495 *invalid = 1;
496 if ((insn & 0x8000) != 0)
497 return (insn & 0xfffc) - 0x10000;
498 else
499 return insn & 0xfffc;
500 }
501
502 /* The BD field in a B form instruction when the + modifier is used.
503 This is like BDM, above, except that the branch is expected to be
504 taken. */
505
506 /*ARGSUSED*/
507 static unsigned long
insert_bdp(insn,value,errmsg)508 insert_bdp (insn, value, errmsg)
509 unsigned long insn;
510 long value;
511 const char **errmsg;
512 {
513 if ((value & 0x8000) == 0)
514 insn |= 1 << 21;
515 return insn | (value & 0xfffc);
516 }
517
518 static long
extract_bdp(insn,invalid)519 extract_bdp (insn, invalid)
520 unsigned long insn;
521 int *invalid;
522 {
523 if (invalid != (int *) NULL
524 && ((insn & (1 << 21)) == 0
525 || (insn & (1 << 15)) != 0))
526 *invalid = 1;
527 if ((insn & 0x8000) != 0)
528 return (insn & 0xfffc) - 0x10000;
529 else
530 return insn & 0xfffc;
531 }
532
533 /* Check for legal values of a BO field. */
534
535 static int
valid_bo(long value)536 valid_bo (long value)
537 {
538 /* Certain encodings have bits that are required to be zero. These
539 are (z must be zero, y may be anything):
540 001zy
541 011zy
542 1z00y
543 1z01y
544 1z1zz
545 */
546 switch (value & 0x14)
547 {
548 default:
549 case 0:
550 return 1;
551 case 0x4:
552 return (value & 0x2) == 0;
553 case 0x10:
554 return (value & 0x8) == 0;
555 case 0x14:
556 return value == 0x14;
557 }
558 }
559
560 /* The BO field in a B form instruction. Warn about attempts to set
561 the field to an illegal value. */
562
563 static unsigned long
insert_bo(insn,value,errmsg)564 insert_bo (insn, value, errmsg)
565 unsigned long insn;
566 long value;
567 const char **errmsg;
568 {
569 if (errmsg != (const char **) NULL
570 && ! valid_bo (value))
571 *errmsg = "invalid conditional option";
572 return insn | ((value & 0x1f) << 21);
573 }
574
575 static long
extract_bo(insn,invalid)576 extract_bo (insn, invalid)
577 unsigned long insn;
578 int *invalid;
579 {
580 long value;
581
582 value = (insn >> 21) & 0x1f;
583 if (invalid != (int *) NULL
584 && ! valid_bo (value))
585 *invalid = 1;
586 return value;
587 }
588
589 /* The BO field in a B form instruction when the + or - modifier is
590 used. This is like the BO field, but it must be even. When
591 extracting it, we force it to be even. */
592
593 static unsigned long
insert_boe(insn,value,errmsg)594 insert_boe (insn, value, errmsg)
595 unsigned long insn;
596 long value;
597 const char **errmsg;
598 {
599 if (errmsg != (const char **) NULL)
600 {
601 if (! valid_bo (value))
602 *errmsg = "invalid conditional option";
603 else if ((value & 1) != 0)
604 *errmsg = "attempt to set y bit when using + or - modifier";
605 }
606 return insn | ((value & 0x1f) << 21);
607 }
608
609 static long
extract_boe(insn,invalid)610 extract_boe (insn, invalid)
611 unsigned long insn;
612 int *invalid;
613 {
614 long value;
615
616 value = (insn >> 21) & 0x1f;
617 if (invalid != (int *) NULL
618 && ! valid_bo (value))
619 *invalid = 1;
620 return value & 0x1e;
621 }
622
623 /* The DS field in a DS form instruction. This is like D, but the
624 lower two bits are forced to zero. */
625
626 /*ARGSUSED*/
627 static unsigned long
insert_ds(insn,value,errmsg)628 insert_ds (insn, value, errmsg)
629 unsigned long insn;
630 long value;
631 const char **errmsg;
632 {
633 return insn | (value & 0xfffc);
634 }
635
636 /*ARGSUSED*/
637 static long
extract_ds(insn,invalid)638 extract_ds (insn, invalid)
639 unsigned long insn;
640 int *invalid;
641 {
642 if ((insn & 0x8000) != 0)
643 return (insn & 0xfffc) - 0x10000;
644 else
645 return insn & 0xfffc;
646 }
647
648 /* The LI field in an I form instruction. The lower two bits are
649 forced to zero. */
650
651 /*ARGSUSED*/
652 static unsigned long
insert_li(insn,value,errmsg)653 insert_li (insn, value, errmsg)
654 unsigned long insn;
655 long value;
656 const char **errmsg;
657 {
658 return insn | (value & 0x3fffffc);
659 }
660
661 /*ARGSUSED*/
662 static long
extract_li(insn,invalid)663 extract_li (insn, invalid)
664 unsigned long insn;
665 int *invalid;
666 {
667 if ((insn & 0x2000000) != 0)
668 return (insn & 0x3fffffc) - 0x4000000;
669 else
670 return insn & 0x3fffffc;
671 }
672
673 /* The MB and ME fields in an M form instruction expressed as a single
674 operand which is itself a bitmask. The extraction function always
675 marks it as invalid, since we never want to recognize an
676 instruction which uses a field of this type. */
677
678 static unsigned long
insert_mbe(insn,value,errmsg)679 insert_mbe (insn, value, errmsg)
680 unsigned long insn;
681 long value;
682 const char **errmsg;
683 {
684 unsigned long uval;
685 int mb, me;
686
687 uval = value;
688
689 if (uval == 0)
690 {
691 if (errmsg != (const char **) NULL)
692 *errmsg = "illegal bitmask";
693 return insn;
694 }
695
696 me = 31;
697 while ((uval & 1) == 0)
698 {
699 uval >>= 1;
700 --me;
701 }
702
703 mb = me;
704 uval >>= 1;
705 while ((uval & 1) != 0)
706 {
707 uval >>= 1;
708 --mb;
709 }
710
711 if (uval != 0)
712 {
713 if (errmsg != (const char **) NULL)
714 *errmsg = "illegal bitmask";
715 }
716
717 return insn | (mb << 6) | (me << 1);
718 }
719
720 static long
extract_mbe(insn,invalid)721 extract_mbe (insn, invalid)
722 unsigned long insn;
723 int *invalid;
724 {
725 long ret;
726 int mb, me;
727 int i;
728
729 if (invalid != (int *) NULL)
730 *invalid = 1;
731
732 ret = 0;
733 mb = (insn >> 6) & 0x1f;
734 me = (insn >> 1) & 0x1f;
735 for (i = mb; i < me; i++)
736 ret |= 1 << (31 - i);
737 return ret;
738 }
739
740 /* The MB or ME field in an MD or MDS form instruction. The high bit
741 is wrapped to the low end. */
742
743 /*ARGSUSED*/
744 static unsigned long
insert_mb6(insn,value,errmsg)745 insert_mb6 (insn, value, errmsg)
746 unsigned long insn;
747 long value;
748 const char **errmsg;
749 {
750 return insn | ((value & 0x1f) << 6) | (value & 0x20);
751 }
752
753 /*ARGSUSED*/
754 static long
extract_mb6(insn,invalid)755 extract_mb6 (insn, invalid)
756 unsigned long insn;
757 int *invalid;
758 {
759 return ((insn >> 6) & 0x1f) | (insn & 0x20);
760 }
761
762 /* The NB field in an X form instruction. The value 32 is stored as
763 0. */
764
765 static unsigned long
insert_nb(insn,value,errmsg)766 insert_nb (insn, value, errmsg)
767 unsigned long insn;
768 long value;
769 const char **errmsg;
770 {
771 if (value < 0 || value > 32)
772 *errmsg = "value out of range";
773 if (value == 32)
774 value = 0;
775 return insn | ((value & 0x1f) << 11);
776 }
777
778 /*ARGSUSED*/
779 static long
extract_nb(insn,invalid)780 extract_nb (insn, invalid)
781 unsigned long insn;
782 int *invalid;
783 {
784 long ret;
785
786 ret = (insn >> 11) & 0x1f;
787 if (ret == 0)
788 ret = 32;
789 return ret;
790 }
791
792 /* The NSI field in a D form instruction. This is the same as the SI
793 field, only negated. The extraction function always marks it as
794 invalid, since we never want to recognize an instruction which uses
795 a field of this type. */
796
797 /*ARGSUSED*/
798 static unsigned long
insert_nsi(insn,value,errmsg)799 insert_nsi (insn, value, errmsg)
800 unsigned long insn;
801 long value;
802 const char **errmsg;
803 {
804 return insn | ((- value) & 0xffff);
805 }
806
807 static long
extract_nsi(insn,invalid)808 extract_nsi (insn, invalid)
809 unsigned long insn;
810 int *invalid;
811 {
812 if (invalid != (int *) NULL)
813 *invalid = 1;
814 if ((insn & 0x8000) != 0)
815 return - ((insn & 0xffff) - 0x10000);
816 else
817 return - (insn & 0xffff);
818 }
819
820 /* The RA field in a D or X form instruction which is an updating
821 load, which means that the RA field may not be zero and may not
822 equal the RT field. */
823
824 static unsigned long
insert_ral(insn,value,errmsg)825 insert_ral (insn, value, errmsg)
826 unsigned long insn;
827 long value;
828 const char **errmsg;
829 {
830 if (value == 0
831 || value == ((insn >> 21) & 0x1f))
832 *errmsg = "invalid register operand when updating";
833 return insn | ((value & 0x1f) << 16);
834 }
835
836 /* The RA field in an lmw instruction, which has special value
837 restrictions. */
838
839 static unsigned long
insert_ram(insn,value,errmsg)840 insert_ram (insn, value, errmsg)
841 unsigned long insn;
842 long value;
843 const char **errmsg;
844 {
845 if (value >= ((insn >> 21) & 0x1f))
846 *errmsg = "index register in load range";
847 return insn | ((value & 0x1f) << 16);
848 }
849
850 /* The RA field in a D or X form instruction which is an updating
851 store or an updating floating point load, which means that the RA
852 field may not be zero. */
853
854 static unsigned long
insert_ras(insn,value,errmsg)855 insert_ras (insn, value, errmsg)
856 unsigned long insn;
857 long value;
858 const char **errmsg;
859 {
860 if (value == 0)
861 *errmsg = "invalid register operand when updating";
862 return insn | ((value & 0x1f) << 16);
863 }
864
865 /* The RB field in an X form instruction when it must be the same as
866 the RS field in the instruction. This is used for extended
867 mnemonics like mr. This operand is marked FAKE. The insertion
868 function just copies the BT field into the BA field, and the
869 extraction function just checks that the fields are the same. */
870
871 /*ARGSUSED*/
872 static unsigned long
insert_rbs(insn,value,errmsg)873 insert_rbs (insn, value, errmsg)
874 unsigned long insn;
875 long value;
876 const char **errmsg;
877 {
878 return insn | (((insn >> 21) & 0x1f) << 11);
879 }
880
881 static long
extract_rbs(insn,invalid)882 extract_rbs (insn, invalid)
883 unsigned long insn;
884 int *invalid;
885 {
886 if (invalid != (int *) NULL
887 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
888 *invalid = 1;
889 return 0;
890 }
891
892 /* The SH field in an MD form instruction. This is split. */
893
894 /*ARGSUSED*/
895 static unsigned long
insert_sh6(insn,value,errmsg)896 insert_sh6 (insn, value, errmsg)
897 unsigned long insn;
898 long value;
899 const char **errmsg;
900 {
901 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
902 }
903
904 /*ARGSUSED*/
905 static long
extract_sh6(insn,invalid)906 extract_sh6 (insn, invalid)
907 unsigned long insn;
908 int *invalid;
909 {
910 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
911 }
912
913 /* The SPR field in an XFX form instruction. This is flipped--the
914 lower 5 bits are stored in the upper 5 and vice- versa. */
915
916 static unsigned long
insert_spr(insn,value,errmsg)917 insert_spr (insn, value, errmsg)
918 unsigned long insn;
919 long value;
920 const char **errmsg;
921 {
922 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
923 }
924
925 static long
extract_spr(insn,invalid)926 extract_spr (insn, invalid)
927 unsigned long insn;
928 int *invalid;
929 {
930 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
931 }
932
933 /* The TBR field in an XFX instruction. This is just like SPR, but it
934 is optional. When TBR is omitted, it must be inserted as 268 (the
935 magic number of the TB register). These functions treat 0
936 (indicating an omitted optional operand) as 268. This means that
937 ``mftb 4,0'' is not handled correctly. This does not matter very
938 much, since the architecture manual does not define mftb as
939 accepting any values other than 268 or 269. */
940
941 #define TB (268)
942
943 static unsigned long
insert_tbr(insn,value,errmsg)944 insert_tbr (insn, value, errmsg)
945 unsigned long insn;
946 long value;
947 const char **errmsg;
948 {
949 if (value == 0)
950 value = TB;
951 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
952 }
953
954 static long
extract_tbr(insn,invalid)955 extract_tbr (insn, invalid)
956 unsigned long insn;
957 int *invalid;
958 {
959 long ret;
960
961 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
962 if (ret == TB)
963 ret = 0;
964 return ret;
965 }
966
967 /* Macros used to form opcodes. */
968
969 /* The main opcode. */
970 #define OP(x) (((x) & 0x3f) << 26)
971 #define OP_MASK OP (0x3f)
972
973 /* The main opcode combined with a trap code in the TO field of a D
974 form instruction. Used for extended mnemonics for the trap
975 instructions. */
976 #define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
977 #define OPTO_MASK (OP_MASK | TO_MASK)
978
979 /* The main opcode combined with a comparison size bit in the L field
980 of a D form or X form instruction. Used for extended mnemonics for
981 the comparison instructions. */
982 #define OPL(x,l) (OP (x) | (((l) & 1) << 21))
983 #define OPL_MASK OPL (0x3f,1)
984
985 /* An A form instruction. */
986 #define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
987 #define A_MASK A (0x3f, 0x1f, 1)
988
989 /* An A_MASK with the FRB field fixed. */
990 #define AFRB_MASK (A_MASK | FRB_MASK)
991
992 /* An A_MASK with the FRC field fixed. */
993 #define AFRC_MASK (A_MASK | FRC_MASK)
994
995 /* An A_MASK with the FRA and FRC fields fixed. */
996 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
997
998 /* A B form instruction. */
999 #define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
1000 #define B_MASK B (0x3f, 1, 1)
1001
1002 /* A B form instruction setting the BO field. */
1003 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
1004 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1005
1006 /* A BBO_MASK with the y bit of the BO field removed. This permits
1007 matching a conditional branch regardless of the setting of the y
1008 bit. */
1009 #define Y_MASK (1 << 21)
1010 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1011
1012 /* A B form instruction setting the BO field and the condition bits of
1013 the BI field. */
1014 #define BBOCB(op, bo, cb, aa, lk) \
1015 (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
1016 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1017
1018 /* A BBOCB_MASK with the y bit of the BO field removed. */
1019 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1020
1021 /* A BBOYCB_MASK in which the BI field is fixed. */
1022 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1023
1024 /* The main opcode mask with the RA field clear. */
1025 #define DRA_MASK (OP_MASK | RA_MASK)
1026
1027 /* A DS form instruction. */
1028 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1029 #define DS_MASK DSO (0x3f, 3)
1030
1031 /* An M form instruction. */
1032 #define M(op, rc) (OP (op) | ((rc) & 1))
1033 #define M_MASK M (0x3f, 1)
1034
1035 /* An M form instruction with the ME field specified. */
1036 #define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
1037
1038 /* An M_MASK with the MB and ME fields fixed. */
1039 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1040
1041 /* An M_MASK with the SH and ME fields fixed. */
1042 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1043
1044 /* An MD form instruction. */
1045 #define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
1046 #define MD_MASK MD (0x3f, 0x7, 1)
1047
1048 /* An MD_MASK with the MB field fixed. */
1049 #define MDMB_MASK (MD_MASK | MB6_MASK)
1050
1051 /* An MD_MASK with the SH field fixed. */
1052 #define MDSH_MASK (MD_MASK | SH6_MASK)
1053
1054 /* An MDS form instruction. */
1055 #define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
1056 #define MDS_MASK MDS (0x3f, 0xf, 1)
1057
1058 /* An MDS_MASK with the MB field fixed. */
1059 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1060
1061 /* An SC form instruction. */
1062 #define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
1063 #define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
1064
1065 /* An X form instruction. */
1066 #define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1067
1068 /* An X form instruction with the RC bit specified. */
1069 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1070
1071 /* The mask for an X form instruction. */
1072 #define X_MASK XRC (0x3f, 0x3ff, 1)
1073
1074 /* An X_MASK with the RA field fixed. */
1075 #define XRA_MASK (X_MASK | RA_MASK)
1076
1077 /* An X_MASK with the RB field fixed. */
1078 #define XRB_MASK (X_MASK | RB_MASK)
1079
1080 /* An X_MASK with the RT field fixed. */
1081 #define XRT_MASK (X_MASK | RT_MASK)
1082
1083 /* An X_MASK with the RA and RB fields fixed. */
1084 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1085
1086 /* An X_MASK with the RT and RA fields fixed. */
1087 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1088
1089 /* An X form comparison instruction. */
1090 #define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
1091
1092 /* The mask for an X form comparison instruction. */
1093 #define XCMP_MASK (X_MASK | (1 << 22))
1094
1095 /* The mask for an X form comparison instruction with the L field
1096 fixed. */
1097 #define XCMPL_MASK (XCMP_MASK | (1 << 21))
1098
1099 /* An X form trap instruction with the TO field specified. */
1100 #define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
1101 #define XTO_MASK (X_MASK | TO_MASK)
1102
1103 /* An XFL form instruction. */
1104 #define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
1105 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
1106
1107 /* An XL form instruction with the LK field set to 0. */
1108 #define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1109
1110 /* An XL form instruction which uses the LK field. */
1111 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1112
1113 /* The mask for an XL form instruction. */
1114 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1115
1116 /* An XL form instruction which explicitly sets the BO field. */
1117 #define XLO(op, bo, xop, lk) \
1118 (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
1119 #define XLO_MASK (XL_MASK | BO_MASK)
1120
1121 /* An XL form instruction which explicitly sets the y bit of the BO
1122 field. */
1123 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
1124 #define XLYLK_MASK (XL_MASK | Y_MASK)
1125
1126 /* An XL form instruction which sets the BO field and the condition
1127 bits of the BI field. */
1128 #define XLOCB(op, bo, cb, xop, lk) \
1129 (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
1130 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1131
1132 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1133 #define XLBB_MASK (XL_MASK | BB_MASK)
1134 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1135 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1136
1137 /* An XL_MASK with the BO and BB fields fixed. */
1138 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1139
1140 /* An XL_MASK with the BO, BI and BB fields fixed. */
1141 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1142
1143 /* An XO form instruction. */
1144 #define XO(op, xop, oe, rc) \
1145 (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
1146 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1147
1148 /* An XO_MASK with the RB field fixed. */
1149 #define XORB_MASK (XO_MASK | RB_MASK)
1150
1151 /* An XS form instruction. */
1152 #define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
1153 #define XS_MASK XS (0x3f, 0x1ff, 1)
1154
1155 /* A mask for the FXM version of an XFX form instruction. */
1156 #define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
1157
1158 /* An XFX form instruction with the FXM field filled in. */
1159 #define XFXM(op, xop, fxm) \
1160 (X ((op), (xop)) | (((fxm) & 0xff) << 12))
1161
1162 /* An XFX form instruction with the SPR field filled in. */
1163 #define XSPR(op, xop, spr) \
1164 (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
1165 #define XSPR_MASK (X_MASK | SPR_MASK)
1166
1167 /* An XFX form instruction with the SPR field filled in except for the
1168 SPRBAT field. */
1169 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1170
1171 /* An XFX form instruction with the SPR field filled in except for the
1172 SPRG field. */
1173 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1174
1175 /* The BO encodings used in extended conditional branch mnemonics. */
1176 #define BODNZF (0x0)
1177 #define BODNZFP (0x1)
1178 #define BODZF (0x2)
1179 #define BODZFP (0x3)
1180 #define BOF (0x4)
1181 #define BOFP (0x5)
1182 #define BODNZT (0x8)
1183 #define BODNZTP (0x9)
1184 #define BODZT (0xa)
1185 #define BODZTP (0xb)
1186 #define BOT (0xc)
1187 #define BOTP (0xd)
1188 #define BODNZ (0x10)
1189 #define BODNZP (0x11)
1190 #define BODZ (0x12)
1191 #define BODZP (0x13)
1192 #define BOU (0x14)
1193
1194 /* The BI condition bit encodings used in extended conditional branch
1195 mnemonics. */
1196 #define CBLT (0)
1197 #define CBGT (1)
1198 #define CBEQ (2)
1199 #define CBSO (3)
1200
1201 /* The TO encodings used in extended trap mnemonics. */
1202 #define TOLGT (0x1)
1203 #define TOLLT (0x2)
1204 #define TOEQ (0x4)
1205 #define TOLGE (0x5)
1206 #define TOLNL (0x5)
1207 #define TOLLE (0x6)
1208 #define TOLNG (0x6)
1209 #define TOGT (0x8)
1210 #define TOGE (0xc)
1211 #define TONL (0xc)
1212 #define TOLT (0x10)
1213 #define TOLE (0x14)
1214 #define TONG (0x14)
1215 #define TONE (0x18)
1216 #define TOU (0x1f)
1217
1218 /* Smaller names for the flags so each entry in the opcodes table will
1219 fit on a single line. */
1220 #undef PPC
1221 #define PPC PPC_OPCODE_PPC
1222 #define POWER PPC_OPCODE_POWER
1223 #define POWER2 PPC_OPCODE_POWER2
1224 #define B32 PPC_OPCODE_32
1225 #define B64 PPC_OPCODE_64
1226 #define M601 PPC_OPCODE_601
1227
1228 /* The opcode table.
1229
1230 The format of the opcode table is:
1231
1232 NAME OPCODE MASK FLAGS { OPERANDS }
1233
1234 NAME is the name of the instruction.
1235 OPCODE is the instruction opcode.
1236 MASK is the opcode mask; this is used to tell the disassembler
1237 which bits in the actual opcode must match OPCODE.
1238 FLAGS are flags indicated what processors support the instruction.
1239 OPERANDS is the list of operands.
1240
1241 The disassembler reads the table in order and prints the first
1242 instruction which matches, so this table is sorted to put more
1243 specific instructions before more general instructions. It is also
1244 sorted by major opcode. */
1245
1246 const struct powerpc_opcode powerpc_opcodes[] = {
1247 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC|B64, { RA, SI } },
1248 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC|B64, { RA, SI } },
1249 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC|B64, { RA, SI } },
1250 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC|B64, { RA, SI } },
1251 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC|B64, { RA, SI } },
1252 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC|B64, { RA, SI } },
1253 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC|B64, { RA, SI } },
1254 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC|B64, { RA, SI } },
1255 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC|B64, { RA, SI } },
1256 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC|B64, { RA, SI } },
1257 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC|B64, { RA, SI } },
1258 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC|B64, { RA, SI } },
1259 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC|B64, { RA, SI } },
1260 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC|B64, { RA, SI } },
1261 { "tdi", OP(2), OP_MASK, PPC|B64, { TO, RA, SI } },
1262
1263 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPC, { RA, SI } },
1264 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, POWER, { RA, SI } },
1265 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPC, { RA, SI } },
1266 { "tllti", OPTO(3,TOLLT), OPTO_MASK, POWER, { RA, SI } },
1267 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPC, { RA, SI } },
1268 { "teqi", OPTO(3,TOEQ), OPTO_MASK, POWER, { RA, SI } },
1269 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPC, { RA, SI } },
1270 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, POWER, { RA, SI } },
1271 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPC, { RA, SI } },
1272 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, POWER, { RA, SI } },
1273 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPC, { RA, SI } },
1274 { "tllei", OPTO(3,TOLLE), OPTO_MASK, POWER, { RA, SI } },
1275 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPC, { RA, SI } },
1276 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, POWER, { RA, SI } },
1277 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPC, { RA, SI } },
1278 { "tgti", OPTO(3,TOGT), OPTO_MASK, POWER, { RA, SI } },
1279 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPC, { RA, SI } },
1280 { "tgei", OPTO(3,TOGE), OPTO_MASK, POWER, { RA, SI } },
1281 { "twnli", OPTO(3,TONL), OPTO_MASK, PPC, { RA, SI } },
1282 { "tnli", OPTO(3,TONL), OPTO_MASK, POWER, { RA, SI } },
1283 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPC, { RA, SI } },
1284 { "tlti", OPTO(3,TOLT), OPTO_MASK, POWER, { RA, SI } },
1285 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPC, { RA, SI } },
1286 { "tlei", OPTO(3,TOLE), OPTO_MASK, POWER, { RA, SI } },
1287 { "twngi", OPTO(3,TONG), OPTO_MASK, PPC, { RA, SI } },
1288 { "tngi", OPTO(3,TONG), OPTO_MASK, POWER, { RA, SI } },
1289 { "twnei", OPTO(3,TONE), OPTO_MASK, PPC, { RA, SI } },
1290 { "tnei", OPTO(3,TONE), OPTO_MASK, POWER, { RA, SI } },
1291 { "twi", OP(3), OP_MASK, PPC, { TO, RA, SI } },
1292 { "ti", OP(3), OP_MASK, POWER, { TO, RA, SI } },
1293
1294 { "mulli", OP(7), OP_MASK, PPC, { RT, RA, SI } },
1295 { "muli", OP(7), OP_MASK, POWER, { RT, RA, SI } },
1296
1297 { "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } },
1298 { "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } },
1299
1300 { "dozi", OP(9), OP_MASK, POWER|M601, { RT, RA, SI } },
1301
1302 { "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } },
1303 { "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } },
1304 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
1305 { "cmpli", OP(10), OP_MASK, POWER, { BF, RA, UI } },
1306
1307 { "cmpwi", OPL(11,0), OPL_MASK, PPC, { OBF, RA, SI } },
1308 { "cmpdi", OPL(11,1), OPL_MASK, PPC|B64, { OBF, RA, SI } },
1309 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
1310 { "cmpi", OP(11), OP_MASK, POWER, { BF, RA, SI } },
1311
1312 { "addic", OP(12), OP_MASK, PPC, { RT, RA, SI } },
1313 { "ai", OP(12), OP_MASK, POWER, { RT, RA, SI } },
1314 { "subic", OP(12), OP_MASK, PPC, { RT, RA, NSI } },
1315
1316 { "addic.", OP(13), OP_MASK, PPC, { RT, RA, SI } },
1317 { "ai.", OP(13), OP_MASK, POWER, { RT, RA, SI } },
1318 { "subic.", OP(13), OP_MASK, PPC, { RT, RA, NSI } },
1319
1320 { "li", OP(14), DRA_MASK, PPC, { RT, SI } },
1321 { "lil", OP(14), DRA_MASK, POWER, { RT, SI } },
1322 { "addi", OP(14), OP_MASK, PPC, { RT, RA, SI } },
1323 { "cal", OP(14), OP_MASK, POWER, { RT, D, RA } },
1324 { "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } },
1325 { "la", OP(14), OP_MASK, PPC, { RT, D, RA } },
1326
1327 { "lis", OP(15), DRA_MASK, PPC, { RT, SISIGNOPT } },
1328 { "liu", OP(15), DRA_MASK, POWER, { RT, SISIGNOPT } },
1329 { "addis", OP(15), OP_MASK, PPC, { RT,RA,SISIGNOPT } },
1330 { "cau", OP(15), OP_MASK, POWER, { RT,RA,SISIGNOPT } },
1331 { "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } },
1332
1333 { "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1334 { "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1335 { "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BD } },
1336 { "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER, { BD } },
1337 { "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1338 { "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1339 { "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BD } },
1340 { "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER, { BD } },
1341 { "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1342 { "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1343 { "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDA } },
1344 { "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER, { BDA } },
1345 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1346 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1347 { "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDA } },
1348 { "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER, { BDA } },
1349 { "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1350 { "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1351 { "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } },
1352 { "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1353 { "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1354 { "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } },
1355 { "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1356 { "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1357 { "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } },
1358 { "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1359 { "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1360 { "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } },
1361 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1362 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1363 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1364 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1365 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1366 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1367 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1368 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1369 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1370 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1371 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1372 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1373 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1374 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1375 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1376 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1377 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1378 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1379 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1380 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1381 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1382 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1383 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1384 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1385 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1386 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1387 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1388 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1389 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1390 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1391 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1392 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1393 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1394 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1395 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1396 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1397 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1398 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1399 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1400 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1401 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1402 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1403 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1404 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1405 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1406 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1407 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1408 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1409 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1410 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1411 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1412 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1413 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1414 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1415 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1416 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1417 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1418 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1419 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1420 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1421 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1422 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1423 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1424 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1425 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1426 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1427 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1428 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1429 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1430 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1431 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1432 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1433 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1434 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1435 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1436 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1437 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1438 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1439 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1440 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1441 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1442 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1443 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1444 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1445 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1446 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1447 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1448 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1449 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1450 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1451 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1452 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1453 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1454 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1455 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1456 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1457 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1458 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1459 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1460 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1461 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1462 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1463 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1464 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1465 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1466 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1467 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1468 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1469 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1470 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1471 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1472 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1473 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1474 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1475 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1476 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1477 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1478 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1479 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1480 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1481 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1482 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1483 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1484 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1485 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1486 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1487 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1488 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1489 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1490 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1491 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1492 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1493 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1494 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1495 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1496 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1497 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1498 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1499 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1500 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1501 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1502 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1503 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1504 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1505 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1506 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1507 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1508 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1509 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1510 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1511 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1512 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1513 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1514 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1515 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1516 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1517 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1518 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1519 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1520 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1521 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1522 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1523 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1524 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1525 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1526 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1527 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1528 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1529 { "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1530 { "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1531 { "bt", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BD } },
1532 { "bbt", BBO(16,BOT,0,0), BBOY_MASK, POWER, { BI, BD } },
1533 { "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1534 { "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1535 { "btl", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BD } },
1536 { "bbtl", BBO(16,BOT,0,1), BBOY_MASK, POWER, { BI, BD } },
1537 { "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1538 { "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1539 { "bta", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1540 { "bbta", BBO(16,BOT,1,0), BBOY_MASK, POWER, { BI, BDA } },
1541 { "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1542 { "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1543 { "btla", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1544 { "bbtla", BBO(16,BOT,1,1), BBOY_MASK, POWER, { BI, BDA } },
1545 { "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1546 { "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1547 { "bf", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BD } },
1548 { "bbf", BBO(16,BOF,0,0), BBOY_MASK, POWER, { BI, BD } },
1549 { "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1550 { "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1551 { "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BD } },
1552 { "bbfl", BBO(16,BOF,0,1), BBOY_MASK, POWER, { BI, BD } },
1553 { "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1554 { "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1555 { "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1556 { "bbfa", BBO(16,BOF,1,0), BBOY_MASK, POWER, { BI, BDA } },
1557 { "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1558 { "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1559 { "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1560 { "bbfla", BBO(16,BOF,1,1), BBOY_MASK, POWER, { BI, BDA } },
1561 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1562 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1563 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1564 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1565 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1566 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1567 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1568 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1569 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1570 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1571 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1572 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1573 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1574 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1575 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1576 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1577 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1578 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1579 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1580 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1581 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1582 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1583 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1584 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1585 { "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } },
1586 { "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } },
1587 { "bc", B(16,0,0), B_MASK, PPC|POWER, { BO, BI, BD } },
1588 { "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } },
1589 { "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } },
1590 { "bcl", B(16,0,1), B_MASK, PPC|POWER, { BO, BI, BD } },
1591 { "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } },
1592 { "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } },
1593 { "bca", B(16,1,0), B_MASK, PPC|POWER, { BO, BI, BDA } },
1594 { "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } },
1595 { "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } },
1596 { "bcla", B(16,1,1), B_MASK, PPC|POWER, { BO, BI, BDA } },
1597
1598 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
1599 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
1600 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
1601 { "svca", SC(17,1,0), SC_MASK, POWER, { SV } },
1602 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
1603
1604 { "b", B(18,0,0), B_MASK, PPC|POWER, { LI } },
1605 { "bl", B(18,0,1), B_MASK, PPC|POWER, { LI } },
1606 { "ba", B(18,1,0), B_MASK, PPC|POWER, { LIA } },
1607 { "bla", B(18,1,1), B_MASK, PPC|POWER, { LIA } },
1608
1609 { "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
1610
1611 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1612 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER, { 0 } },
1613 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1614 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER, { 0 } },
1615 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1616 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1617 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1618 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1619 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1620 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1621 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1622 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1623 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1624 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1625 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1626 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1627 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1628 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1629 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1630 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1631 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1632 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1633 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1634 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1635 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1636 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1637 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1638 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1639 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1640 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1641 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1642 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1643 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1644 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1645 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1646 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1647 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1648 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1649 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1650 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1651 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1652 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1653 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1654 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1655 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1656 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1657 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1658 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1659 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1660 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1661 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1662 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1663 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1664 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1665 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1666 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1667 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1668 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1669 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1670 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1671 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1672 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1673 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1674 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1675 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1676 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1677 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1678 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1679 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1680 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1681 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1682 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1683 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1684 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1685 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1686 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1687 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1688 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1689 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1690 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1691 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1692 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1693 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1694 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1695 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1696 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1697 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1698 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1699 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1700 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1701 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1702 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1703 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1704 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1705 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1706 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1707 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1708 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1709 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1710 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1711 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1712 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1713 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1714 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1715 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1716 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1717 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1718 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1719 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1720 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1721 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } },
1722 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, POWER, { BI } },
1723 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1724 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1725 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } },
1726 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, POWER, { BI } },
1727 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1728 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1729 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } },
1730 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, POWER, { BI } },
1731 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1732 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1733 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } },
1734 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, POWER, { BI } },
1735 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1736 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1737 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1738 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1739 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1740 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1741 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1742 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1743 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1744 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1745 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1746 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1747 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1748 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1749 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1750 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1751 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1752 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1753 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1754 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1755 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1756 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1757 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1758 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1759 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPC, { BO, BI } },
1760 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPC, { BO, BI } },
1761 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1762 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1763 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1764 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1765 { "bcr", XLLK(19,16,0), XLBB_MASK, POWER, { BO, BI } },
1766 { "bcrl", XLLK(19,16,1), XLBB_MASK, POWER, { BO, BI } },
1767
1768 { "crnot", XL(19,33), XL_MASK, PPC, { BT, BA, BBA } },
1769 { "crnor", XL(19,33), XL_MASK, PPC|POWER, { BT, BA, BB } },
1770
1771 { "rfi", XL(19,50), 0xffffffff, PPC|POWER, { 0 } },
1772 { "rfci", XL(19,51), 0xffffffff, PPC, { 0 } },
1773
1774 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
1775
1776 { "crandc", XL(19,129), XL_MASK, PPC|POWER, { BT, BA, BB } },
1777
1778 { "isync", XL(19,150), 0xffffffff, PPC, { 0 } },
1779 { "ics", XL(19,150), 0xffffffff, POWER, { 0 } },
1780
1781 { "crclr", XL(19,193), XL_MASK, PPC, { BT, BAT, BBA } },
1782 { "crxor", XL(19,193), XL_MASK, PPC|POWER, { BT, BA, BB } },
1783
1784 { "crnand", XL(19,225), XL_MASK, PPC|POWER, { BT, BA, BB } },
1785
1786 { "crand", XL(19,257), XL_MASK, PPC|POWER, { BT, BA, BB } },
1787
1788 { "crset", XL(19,289), XL_MASK, PPC, { BT, BAT, BBA } },
1789 { "creqv", XL(19,289), XL_MASK, PPC|POWER, { BT, BA, BB } },
1790
1791 { "crorc", XL(19,417), XL_MASK, PPC|POWER, { BT, BA, BB } },
1792
1793 { "crmove", XL(19,449), XL_MASK, PPC, { BT, BA, BBA } },
1794 { "cror", XL(19,449), XL_MASK, PPC|POWER, { BT, BA, BB } },
1795
1796 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } },
1797 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } },
1798 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1799 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1800 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1801 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1802 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1803 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1804 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1805 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1806 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1807 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1808 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1809 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1810 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1811 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1812 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1813 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1814 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1815 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1816 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1817 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1818 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1819 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1820 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1821 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1822 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1823 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1824 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1825 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1826 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1827 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1828 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1829 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1830 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1831 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1832 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1833 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1834 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1835 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1836 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1837 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1838 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1839 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1840 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1841 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1842 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1843 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1844 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1845 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1846 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1847 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1848 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1849 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1850 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1851 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1852 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1853 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1854 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1855 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1856 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1857 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1858 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1859 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1860 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1861 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1862 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1863 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1864 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1865 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1866 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1867 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1868 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1869 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1870 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1871 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1872 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } },
1873 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1874 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1875 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } },
1876 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1877 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1878 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } },
1879 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1880 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1881 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } },
1882 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPC, { BO, BI } },
1883 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1884 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1885 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPC, { BO, BI } },
1886 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1887 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1888 { "bcc", XLLK(19,528,0), XLBB_MASK, POWER, { BO, BI } },
1889 { "bccl", XLLK(19,528,1), XLBB_MASK, POWER, { BO, BI } },
1890
1891 { "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1892 { "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1893
1894 { "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1895 { "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1896
1897 { "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, SH } },
1898 { "clrlwi", MME(21,31,0), MSHME_MASK, PPC, { RA, RS, MB } },
1899 { "rlwinm", M(21,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1900 { "rlinm", M(21,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1901 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPC, { RA,RS,SH } },
1902 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPC, { RA, RS, MB } },
1903 { "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1904 { "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1905
1906 { "rlmi", M(22,0), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
1907 { "rlmi.", M(22,1), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
1908
1909 { "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } },
1910 { "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
1911 { "rlnm", M(23,0), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
1912 { "rotlw.", MME(23,31,1), MMBME_MASK, PPC, { RA, RS, RB } },
1913 { "rlwnm.", M(23,1), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
1914 { "rlnm.", M(23,1), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
1915
1916 { "nop", OP(24), 0xffffffff, PPC, { 0 } },
1917 { "ori", OP(24), OP_MASK, PPC, { RA, RS, UI } },
1918 { "oril", OP(24), OP_MASK, POWER, { RA, RS, UI } },
1919
1920 { "oris", OP(25), OP_MASK, PPC, { RA, RS, UI } },
1921 { "oriu", OP(25), OP_MASK, POWER, { RA, RS, UI } },
1922
1923 { "xori", OP(26), OP_MASK, PPC, { RA, RS, UI } },
1924 { "xoril", OP(26), OP_MASK, POWER, { RA, RS, UI } },
1925
1926 { "xoris", OP(27), OP_MASK, PPC, { RA, RS, UI } },
1927 { "xoriu", OP(27), OP_MASK, POWER, { RA, RS, UI } },
1928
1929 { "andi.", OP(28), OP_MASK, PPC, { RA, RS, UI } },
1930 { "andil.", OP(28), OP_MASK, POWER, { RA, RS, UI } },
1931
1932 { "andis.", OP(29), OP_MASK, PPC, { RA, RS, UI } },
1933 { "andiu.", OP(29), OP_MASK, POWER, { RA, RS, UI } },
1934
1935 { "rotldi", MD(30,0,0), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
1936 { "clrldi", MD(30,0,0), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
1937 { "rldicl", MD(30,0,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1938 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
1939 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
1940 { "rldicl.", MD(30,0,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1941
1942 { "rldicr", MD(30,1,0), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
1943 { "rldicr.", MD(30,1,1), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
1944
1945 { "rldic", MD(30,2,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1946 { "rldic.", MD(30,2,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1947
1948 { "rldimi", MD(30,3,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1949 { "rldimi.", MD(30,3,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1950
1951 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
1952 { "rldcl", MDS(30,8,0), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
1953 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
1954 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
1955
1956 { "rldcr", MDS(30,9,0), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
1957 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
1958
1959 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
1960 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
1961 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
1962 { "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } },
1963
1964 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } },
1965 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } },
1966 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPC, { RA, RB } },
1967 { "tllt", XTO(31,4,TOLLT), XTO_MASK, POWER, { RA, RB } },
1968 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPC, { RA, RB } },
1969 { "teq", XTO(31,4,TOEQ), XTO_MASK, POWER, { RA, RB } },
1970 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPC, { RA, RB } },
1971 { "tlge", XTO(31,4,TOLGE), XTO_MASK, POWER, { RA, RB } },
1972 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPC, { RA, RB } },
1973 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, POWER, { RA, RB } },
1974 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPC, { RA, RB } },
1975 { "tlle", XTO(31,4,TOLLE), XTO_MASK, POWER, { RA, RB } },
1976 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPC, { RA, RB } },
1977 { "tlng", XTO(31,4,TOLNG), XTO_MASK, POWER, { RA, RB } },
1978 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPC, { RA, RB } },
1979 { "tgt", XTO(31,4,TOGT), XTO_MASK, POWER, { RA, RB } },
1980 { "twge", XTO(31,4,TOGE), XTO_MASK, PPC, { RA, RB } },
1981 { "tge", XTO(31,4,TOGE), XTO_MASK, POWER, { RA, RB } },
1982 { "twnl", XTO(31,4,TONL), XTO_MASK, PPC, { RA, RB } },
1983 { "tnl", XTO(31,4,TONL), XTO_MASK, POWER, { RA, RB } },
1984 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPC, { RA, RB } },
1985 { "tlt", XTO(31,4,TOLT), XTO_MASK, POWER, { RA, RB } },
1986 { "twle", XTO(31,4,TOLE), XTO_MASK, PPC, { RA, RB } },
1987 { "tle", XTO(31,4,TOLE), XTO_MASK, POWER, { RA, RB } },
1988 { "twng", XTO(31,4,TONG), XTO_MASK, PPC, { RA, RB } },
1989 { "tng", XTO(31,4,TONG), XTO_MASK, POWER, { RA, RB } },
1990 { "twne", XTO(31,4,TONE), XTO_MASK, PPC, { RA, RB } },
1991 { "tne", XTO(31,4,TONE), XTO_MASK, POWER, { RA, RB } },
1992 { "trap", XTO(31,4,TOU), 0xffffffff, PPC, { 0 } },
1993 { "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } },
1994 { "t", X(31,4), X_MASK, POWER, { TO, RA, RB } },
1995
1996 { "subfc", XO(31,8,0,0), XO_MASK, PPC, { RT, RA, RB } },
1997 { "sf", XO(31,8,0,0), XO_MASK, POWER, { RT, RA, RB } },
1998 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
1999 { "subfc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RA, RB } },
2000 { "sf.", XO(31,8,0,1), XO_MASK, POWER, { RT, RA, RB } },
2001 { "subc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RB, RA } },
2002 { "subfco", XO(31,8,1,0), XO_MASK, PPC, { RT, RA, RB } },
2003 { "sfo", XO(31,8,1,0), XO_MASK, POWER, { RT, RA, RB } },
2004 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
2005 { "subfco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RA, RB } },
2006 { "sfo.", XO(31,8,1,1), XO_MASK, POWER, { RT, RA, RB } },
2007 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
2008
2009 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2010 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2011
2012 { "addc", XO(31,10,0,0), XO_MASK, PPC, { RT, RA, RB } },
2013 { "a", XO(31,10,0,0), XO_MASK, POWER, { RT, RA, RB } },
2014 { "addc.", XO(31,10,0,1), XO_MASK, PPC, { RT, RA, RB } },
2015 { "a.", XO(31,10,0,1), XO_MASK, POWER, { RT, RA, RB } },
2016 { "addco", XO(31,10,1,0), XO_MASK, PPC, { RT, RA, RB } },
2017 { "ao", XO(31,10,1,0), XO_MASK, POWER, { RT, RA, RB } },
2018 { "addco.", XO(31,10,1,1), XO_MASK, PPC, { RT, RA, RB } },
2019 { "ao.", XO(31,10,1,1), XO_MASK, POWER, { RT, RA, RB } },
2020
2021 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
2022 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
2023
2024 { "mfcr", X(31,19), XRARB_MASK, POWER|PPC, { RT } },
2025
2026 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
2027
2028 { "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } },
2029
2030 { "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } },
2031 { "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } },
2032
2033 { "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } },
2034 { "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } },
2035 { "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } },
2036 { "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } },
2037
2038 { "cntlzw", XRC(31,26,0), XRB_MASK, PPC, { RA, RS } },
2039 { "cntlz", XRC(31,26,0), XRB_MASK, POWER, { RA, RS } },
2040 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPC, { RA, RS } },
2041 { "cntlz.", XRC(31,26,1), XRB_MASK, POWER, { RA, RS } },
2042
2043 { "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } },
2044 { "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } },
2045
2046 { "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2047 { "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2048
2049 { "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } },
2050 { "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } },
2051
2052 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
2053 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
2054 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
2055 { "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } },
2056
2057 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
2058 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
2059 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
2060 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
2061 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
2062 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
2063 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
2064 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
2065
2066 { "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } },
2067
2068 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
2069
2070 { "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } },
2071 { "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } },
2072
2073 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } },
2074 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC|B64, { RA, RS } },
2075
2076 { "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2077 { "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2078
2079 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC|B64, { RA, RB } },
2080 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC|B64, { RA, RB } },
2081 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC|B64, { RA, RB } },
2082 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC|B64, { RA, RB } },
2083 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC|B64, { RA, RB } },
2084 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC|B64, { RA, RB } },
2085 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC|B64, { RA, RB } },
2086 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC|B64, { RA, RB } },
2087 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC|B64, { RA, RB } },
2088 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC|B64, { RA, RB } },
2089 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC|B64, { RA, RB } },
2090 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC|B64, { RA, RB } },
2091 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC|B64, { RA, RB } },
2092 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC|B64, { RA, RB } },
2093 { "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } },
2094
2095 { "mulhd", XO(31,73,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2096 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2097
2098 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2099 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2100
2101 { "mfmsr", X(31,83), XRARB_MASK, PPC|POWER, { RT } },
2102
2103 { "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } },
2104
2105 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2106
2107 { "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } },
2108
2109 { "neg", XO(31,104,0,0), XORB_MASK, PPC|POWER, { RT, RA } },
2110 { "neg.", XO(31,104,0,1), XORB_MASK, PPC|POWER, { RT, RA } },
2111 { "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } },
2112 { "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } },
2113
2114 { "mul", XO(31,107,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2115 { "mul.", XO(31,107,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2116 { "mulo", XO(31,107,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2117 { "mulo.", XO(31,107,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2118
2119 { "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
2120
2121 { "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } },
2122
2123 { "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2124 { "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2125 { "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2126 { "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2127
2128 { "subfe", XO(31,136,0,0), XO_MASK, PPC, { RT, RA, RB } },
2129 { "sfe", XO(31,136,0,0), XO_MASK, POWER, { RT, RA, RB } },
2130 { "subfe.", XO(31,136,0,1), XO_MASK, PPC, { RT, RA, RB } },
2131 { "sfe.", XO(31,136,0,1), XO_MASK, POWER, { RT, RA, RB } },
2132 { "subfeo", XO(31,136,1,0), XO_MASK, PPC, { RT, RA, RB } },
2133 { "sfeo", XO(31,136,1,0), XO_MASK, POWER, { RT, RA, RB } },
2134 { "subfeo.", XO(31,136,1,1), XO_MASK, PPC, { RT, RA, RB } },
2135 { "sfeo.", XO(31,136,1,1), XO_MASK, POWER, { RT, RA, RB } },
2136
2137 { "adde", XO(31,138,0,0), XO_MASK, PPC, { RT, RA, RB } },
2138 { "ae", XO(31,138,0,0), XO_MASK, POWER, { RT, RA, RB } },
2139 { "adde.", XO(31,138,0,1), XO_MASK, PPC, { RT, RA, RB } },
2140 { "ae.", XO(31,138,0,1), XO_MASK, POWER, { RT, RA, RB } },
2141 { "addeo", XO(31,138,1,0), XO_MASK, PPC, { RT, RA, RB } },
2142 { "aeo", XO(31,138,1,0), XO_MASK, POWER, { RT, RA, RB } },
2143 { "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } },
2144 { "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } },
2145
2146 { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }},
2147 { "mtcrf", X(31,144), XFXFXM_MASK, PPC|POWER, { FXM, RS } },
2148
2149 { "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } },
2150 { "mtmsrd", X(31,178), XRARB_MASK, PPC|POWER, { RS } },
2151
2152 { "stdx", X(31,149), X_MASK, PPC|B64, { RS, RA, RB } },
2153
2154 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2155
2156 { "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } },
2157 { "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } },
2158
2159 { "slq", XRC(31,152,0), X_MASK, POWER|M601, { RA, RS, RB } },
2160 { "slq.", XRC(31,152,1), X_MASK, POWER|M601, { RA, RS, RB } },
2161
2162 { "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } },
2163 { "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } },
2164
2165 { "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } },
2166
2167 { "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } },
2168 { "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } },
2169
2170 { "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } },
2171 { "sliq.", XRC(31,184,1), X_MASK, POWER|M601, { RA, RS, SH } },
2172
2173 { "subfze", XO(31,200,0,0), XORB_MASK, PPC, { RT, RA } },
2174 { "sfze", XO(31,200,0,0), XORB_MASK, POWER, { RT, RA } },
2175 { "subfze.", XO(31,200,0,1), XORB_MASK, PPC, { RT, RA } },
2176 { "sfze.", XO(31,200,0,1), XORB_MASK, POWER, { RT, RA } },
2177 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPC, { RT, RA } },
2178 { "sfzeo", XO(31,200,1,0), XORB_MASK, POWER, { RT, RA } },
2179 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC, { RT, RA } },
2180 { "sfzeo.", XO(31,200,1,1), XORB_MASK, POWER, { RT, RA } },
2181
2182 { "addze", XO(31,202,0,0), XORB_MASK, PPC, { RT, RA } },
2183 { "aze", XO(31,202,0,0), XORB_MASK, POWER, { RT, RA } },
2184 { "addze.", XO(31,202,0,1), XORB_MASK, PPC, { RT, RA } },
2185 { "aze.", XO(31,202,0,1), XORB_MASK, POWER, { RT, RA } },
2186 { "addzeo", XO(31,202,1,0), XORB_MASK, PPC, { RT, RA } },
2187 { "azeo", XO(31,202,1,0), XORB_MASK, POWER, { RT, RA } },
2188 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPC, { RT, RA } },
2189 { "azeo.", XO(31,202,1,1), XORB_MASK, POWER, { RT, RA } },
2190
2191 { "mtsr", X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } },
2192
2193 { "stdcx.", XRC(31,214,1), X_MASK, PPC|B64, { RS, RA, RB } },
2194
2195 { "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } },
2196
2197 { "sllq", XRC(31,216,0), X_MASK, POWER|M601, { RA, RS, RB } },
2198 { "sllq.", XRC(31,216,1), X_MASK, POWER|M601, { RA, RS, RB } },
2199
2200 { "sleq", XRC(31,217,0), X_MASK, POWER|M601, { RA, RS, RB } },
2201 { "sleq.", XRC(31,217,1), X_MASK, POWER|M601, { RA, RS, RB } },
2202
2203 { "subfme", XO(31,232,0,0), XORB_MASK, PPC, { RT, RA } },
2204 { "sfme", XO(31,232,0,0), XORB_MASK, POWER, { RT, RA } },
2205 { "subfme.", XO(31,232,0,1), XORB_MASK, PPC, { RT, RA } },
2206 { "sfme.", XO(31,232,0,1), XORB_MASK, POWER, { RT, RA } },
2207 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPC, { RT, RA } },
2208 { "sfmeo", XO(31,232,1,0), XORB_MASK, POWER, { RT, RA } },
2209 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC, { RT, RA } },
2210 { "sfmeo.", XO(31,232,1,1), XORB_MASK, POWER, { RT, RA } },
2211
2212 { "mulld", XO(31,233,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2213 { "mulld.", XO(31,233,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2214 { "mulldo", XO(31,233,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2215 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2216
2217 { "addme", XO(31,234,0,0), XORB_MASK, PPC, { RT, RA } },
2218 { "ame", XO(31,234,0,0), XORB_MASK, POWER, { RT, RA } },
2219 { "addme.", XO(31,234,0,1), XORB_MASK, PPC, { RT, RA } },
2220 { "ame.", XO(31,234,0,1), XORB_MASK, POWER, { RT, RA } },
2221 { "addmeo", XO(31,234,1,0), XORB_MASK, PPC, { RT, RA } },
2222 { "ameo", XO(31,234,1,0), XORB_MASK, POWER, { RT, RA } },
2223 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPC, { RT, RA } },
2224 { "ameo.", XO(31,234,1,1), XORB_MASK, POWER, { RT, RA } },
2225
2226 { "mullw", XO(31,235,0,0), XO_MASK, PPC, { RT, RA, RB } },
2227 { "muls", XO(31,235,0,0), XO_MASK, POWER, { RT, RA, RB } },
2228 { "mullw.", XO(31,235,0,1), XO_MASK, PPC, { RT, RA, RB } },
2229 { "muls.", XO(31,235,0,1), XO_MASK, POWER, { RT, RA, RB } },
2230 { "mullwo", XO(31,235,1,0), XO_MASK, PPC, { RT, RA, RB } },
2231 { "mulso", XO(31,235,1,0), XO_MASK, POWER, { RT, RA, RB } },
2232 { "mullwo.", XO(31,235,1,1), XO_MASK, PPC, { RT, RA, RB } },
2233 { "mulso.", XO(31,235,1,1), XO_MASK, POWER, { RT, RA, RB } },
2234
2235 { "mtsrin", X(31,242), XRA_MASK, PPC|B32, { RS, RB } },
2236 { "mtsri", X(31,242), XRA_MASK, POWER|B32, { RS, RB } },
2237
2238 { "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
2239
2240 { "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } },
2241
2242 { "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } },
2243 { "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } },
2244
2245 { "doz", XO(31,264,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2246 { "doz.", XO(31,264,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2247 { "dozo", XO(31,264,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2248 { "dozo.", XO(31,264,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2249
2250 { "add", XO(31,266,0,0), XO_MASK, PPC, { RT, RA, RB } },
2251 { "cax", XO(31,266,0,0), XO_MASK, POWER, { RT, RA, RB } },
2252 { "add.", XO(31,266,0,1), XO_MASK, PPC, { RT, RA, RB } },
2253 { "cax.", XO(31,266,0,1), XO_MASK, POWER, { RT, RA, RB } },
2254 { "addo", XO(31,266,1,0), XO_MASK, PPC, { RT, RA, RB } },
2255 { "caxo", XO(31,266,1,0), XO_MASK, POWER, { RT, RA, RB } },
2256 { "addo.", XO(31,266,1,1), XO_MASK, PPC, { RT, RA, RB } },
2257 { "caxo.", XO(31,266,1,1), XO_MASK, POWER, { RT, RA, RB } },
2258
2259 { "lscbx", XRC(31,277,0), X_MASK, POWER|M601, { RT, RA, RB } },
2260 { "lscbx.", XRC(31,277,1), X_MASK, POWER|M601, { RT, RA, RB } },
2261
2262 { "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
2263
2264 { "lhzx", X(31,279), X_MASK, PPC|POWER, { RT, RA, RB } },
2265
2266 { "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } },
2267
2268 { "eqv", XRC(31,284,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2269 { "eqv.", XRC(31,284,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2270
2271 { "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
2272 { "tlbi", X(31,306), XRTRA_MASK, POWER, { RB } },
2273
2274 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
2275
2276 { "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } },
2277
2278 { "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2279 { "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2280
2281 { "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } },
2282
2283 { "div", XO(31,331,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2284 { "div.", XO(31,331,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2285 { "divo", XO(31,331,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2286 { "divo.", XO(31,331,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2287
2288 { "mfmq", XSPR(31,339,0), XSPR_MASK, POWER|M601, { RT } },
2289 { "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } },
2290 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, PPC|POWER, { RT } },
2291 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, PPC|POWER, { RT } },
2292 { "mfdec", XSPR(31,339,6), XSPR_MASK, POWER|M601, { RT } },
2293 { "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } },
2294 { "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } },
2295 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
2296 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER, { RT } },
2297 { "mfdar", XSPR(31,339,19), XSPR_MASK, PPC|POWER, { RT } },
2298 { "mfdec", XSPR(31,339,22), XSPR_MASK, PPC, { RT } },
2299 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
2300 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, PPC|POWER, { RT } },
2301 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, PPC|POWER, { RT } },
2302 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, PPC|POWER, { RT } },
2303 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
2304 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC|B64, { RT } },
2305 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
2306 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
2307 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2308 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2309 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2310 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2311 { "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } },
2312
2313 { "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } },
2314
2315 { "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } },
2316
2317 { "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } },
2318
2319 { "abs", XO(31,360,0,0), XORB_MASK, POWER|M601, { RT, RA } },
2320 { "abs.", XO(31,360,0,1), XORB_MASK, POWER|M601, { RT, RA } },
2321 { "abso", XO(31,360,1,0), XORB_MASK, POWER|M601, { RT, RA } },
2322 { "abso.", XO(31,360,1,1), XORB_MASK, POWER|M601, { RT, RA } },
2323
2324 { "divs", XO(31,363,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2325 { "divs.", XO(31,363,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2326 { "divso", XO(31,363,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2327 { "divso.", XO(31,363,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2328
2329 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
2330
2331 { "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
2332 { "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
2333
2334 { "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } },
2335
2336 { "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } },
2337
2338 { "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } },
2339
2340 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
2341
2342 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
2343
2344 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
2345
2346 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
2347
2348 { "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2349 { "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2350
2351 { "sradi", XS(31,413,0), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2352 { "sradi.", XS(31,413,1), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2353
2354 { "slbie", X(31,434), XRTRA_MASK, PPC|B64, { RB } },
2355
2356 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
2357
2358 { "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } },
2359
2360 { "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2361 { "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2362 { "mr.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2363 { "or.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2364
2365 { "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } },
2366
2367 { "divdu", XO(31,457,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2368 { "divdu.", XO(31,457,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2369 { "divduo", XO(31,457,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2370 { "divduo.", XO(31,457,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2371
2372 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
2373 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
2374 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
2375 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
2376
2377 { "mtmq", XSPR(31,467,0), XSPR_MASK, POWER|M601, { RS } },
2378 { "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } },
2379 { "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } },
2380 { "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } },
2381 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
2382 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER, { RS } },
2383 { "mtdar", XSPR(31,467,19), XSPR_MASK, PPC|POWER, { RS } },
2384 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, PPC|POWER, { RS } },
2385 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, PPC|POWER, { RS } },
2386 { "mtdec", XSPR(31,467,22), XSPR_MASK, PPC|POWER, { RS } },
2387 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
2388 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, PPC|POWER, { RS } },
2389 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, PPC|POWER, { RS } },
2390 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, PPC|POWER, { RS } },
2391 { "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
2392 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC|B64, { RS } },
2393 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
2394 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
2395 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
2396 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2397 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2398 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2399 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2400 { "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } },
2401
2402 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
2403
2404 { "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2405 { "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2406
2407 { "nabs", XO(31,488,0,0), XORB_MASK, POWER|M601, { RT, RA } },
2408 { "nabs.", XO(31,488,0,1), XORB_MASK, POWER|M601, { RT, RA } },
2409 { "nabso", XO(31,488,1,0), XORB_MASK, POWER|M601, { RT, RA } },
2410 { "nabso.", XO(31,488,1,1), XORB_MASK, POWER|M601, { RT, RA } },
2411
2412 { "divd", XO(31,489,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2413 { "divd.", XO(31,489,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2414 { "divdo", XO(31,489,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2415 { "divdo.", XO(31,489,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2416
2417 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
2418 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
2419 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
2420 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
2421
2422 { "slbia", X(31,498), 0xffffffff, PPC|B64, { 0 } },
2423
2424 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
2425
2426 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), PPC|POWER, { BF } },
2427
2428 { "clcs", X(31,531), XRB_MASK, POWER|M601, { RT, RA } },
2429
2430 { "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } },
2431 { "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } },
2432
2433 { "lwbrx", X(31,534), X_MASK, PPC, { RT, RA, RB } },
2434 { "lbrx", X(31,534), X_MASK, POWER, { RT, RA, RB } },
2435
2436 { "lfsx", X(31,535), X_MASK, PPC|POWER, { FRT, RA, RB } },
2437
2438 { "srw", XRC(31,536,0), X_MASK, PPC, { RA, RS, RB } },
2439 { "sr", XRC(31,536,0), X_MASK, POWER, { RA, RS, RB } },
2440 { "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } },
2441 { "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } },
2442
2443 { "rrib", XRC(31,537,0), X_MASK, POWER|M601, { RA, RS, RB } },
2444 { "rrib.", XRC(31,537,1), X_MASK, POWER|M601, { RA, RS, RB } },
2445
2446 { "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } },
2447 { "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } },
2448
2449 { "maskir", XRC(31,541,0), X_MASK, POWER|M601, { RA, RS, RB } },
2450 { "maskir.", XRC(31,541,1), X_MASK, POWER|M601, { RA, RS, RB } },
2451
2452 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
2453
2454 { "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } },
2455
2456 { "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } },
2457
2458 { "lswi", X(31,597), X_MASK, PPC, { RT, RA, NB } },
2459 { "lsi", X(31,597), X_MASK, POWER, { RT, RA, NB } },
2460
2461 { "sync", X(31,598), 0xffffffff, PPC, { 0 } },
2462 { "dcs", X(31,598), 0xffffffff, POWER, { 0 } },
2463
2464 { "lfdx", X(31,599), X_MASK, PPC|POWER, { FRT, RA, RB } },
2465
2466 { "mfsri", X(31,627), X_MASK, POWER, { RT, RA, RB } },
2467
2468 { "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } },
2469
2470 { "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } },
2471
2472 { "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } },
2473
2474 { "stswx", X(31,661), X_MASK, PPC, { RS, RA, RB } },
2475 { "stsx", X(31,661), X_MASK, POWER, { RS, RA, RB } },
2476
2477 { "stwbrx", X(31,662), X_MASK, PPC, { RS, RA, RB } },
2478 { "stbrx", X(31,662), X_MASK, POWER, { RS, RA, RB } },
2479
2480 { "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } },
2481
2482 { "srq", XRC(31,664,0), X_MASK, POWER|M601, { RA, RS, RB } },
2483 { "srq.", XRC(31,664,1), X_MASK, POWER|M601, { RA, RS, RB } },
2484
2485 { "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } },
2486 { "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } },
2487
2488 { "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } },
2489
2490 { "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } },
2491 { "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } },
2492
2493 { "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } },
2494 { "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } },
2495
2496 { "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } },
2497
2498 { "srlq", XRC(31,728,0), X_MASK, POWER|M601, { RA, RS, RB } },
2499 { "srlq.", XRC(31,728,1), X_MASK, POWER|M601, { RA, RS, RB } },
2500
2501 { "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } },
2502 { "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } },
2503
2504 { "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } },
2505
2506 { "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } },
2507 { "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } },
2508
2509 { "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } },
2510
2511 { "sraw", XRC(31,792,0), X_MASK, PPC, { RA, RS, RB } },
2512 { "sra", XRC(31,792,0), X_MASK, POWER, { RA, RS, RB } },
2513 { "sraw.", XRC(31,792,1), X_MASK, PPC, { RA, RS, RB } },
2514 { "sra.", XRC(31,792,1), X_MASK, POWER, { RA, RS, RB } },
2515
2516 { "srad", XRC(31,794,0), X_MASK, PPC|B64, { RA, RS, RB } },
2517 { "srad.", XRC(31,794,1), X_MASK, PPC|B64, { RA, RS, RB } },
2518
2519 { "rac", X(31,818), X_MASK, POWER, { RT, RA, RB } },
2520
2521 { "srawi", XRC(31,824,0), X_MASK, PPC, { RA, RS, SH } },
2522 { "srai", XRC(31,824,0), X_MASK, POWER, { RA, RS, SH } },
2523 { "srawi.", XRC(31,824,1), X_MASK, PPC, { RA, RS, SH } },
2524 { "srai.", XRC(31,824,1), X_MASK, POWER, { RA, RS, SH } },
2525
2526 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
2527
2528 { "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } },
2529
2530 { "sraq", XRC(31,920,0), X_MASK, POWER|M601, { RA, RS, RB } },
2531 { "sraq.", XRC(31,920,1), X_MASK, POWER|M601, { RA, RS, RB } },
2532
2533 { "srea", XRC(31,921,0), X_MASK, POWER|M601, { RA, RS, RB } },
2534 { "srea.", XRC(31,921,1), X_MASK, POWER|M601, { RA, RS, RB } },
2535
2536 { "extsh", XRC(31,922,0), XRB_MASK, PPC, { RA, RS } },
2537 { "exts", XRC(31,922,0), XRB_MASK, POWER, { RA, RS } },
2538 { "extsh.", XRC(31,922,1), XRB_MASK, PPC, { RA, RS } },
2539 { "exts.", XRC(31,922,1), XRB_MASK, POWER, { RA, RS } },
2540
2541 { "sraiq", XRC(31,952,0), X_MASK, POWER|M601, { RA, RS, SH } },
2542 { "sraiq.", XRC(31,952,1), X_MASK, POWER|M601, { RA, RS, SH } },
2543
2544 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
2545 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
2546
2547 { "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } },
2548
2549 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
2550
2551 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
2552
2553 { "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
2554 { "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
2555
2556 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2557 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2558
2559 { "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } },
2560 { "l", OP(32), OP_MASK, POWER, { RT, D, RA } },
2561
2562 { "lwzu", OP(33), OP_MASK, PPC, { RT, D, RAL } },
2563 { "lu", OP(33), OP_MASK, POWER, { RT, D, RA } },
2564
2565 { "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } },
2566
2567 { "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RAL } },
2568
2569 { "stw", OP(36), OP_MASK, PPC, { RS, D, RA } },
2570 { "st", OP(36), OP_MASK, POWER, { RS, D, RA } },
2571
2572 { "stwu", OP(37), OP_MASK, PPC, { RS, D, RAS } },
2573 { "stu", OP(37), OP_MASK, POWER, { RS, D, RA } },
2574
2575 { "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } },
2576
2577 { "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RAS } },
2578
2579 { "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } },
2580
2581 { "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RAL } },
2582
2583 { "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } },
2584
2585 { "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RAL } },
2586
2587 { "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } },
2588
2589 { "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RAS } },
2590
2591 { "lmw", OP(46), OP_MASK, PPC, { RT, D, RAM } },
2592 { "lm", OP(46), OP_MASK, POWER, { RT, D, RA } },
2593
2594 { "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } },
2595 { "stm", OP(47), OP_MASK, POWER, { RS, D, RA } },
2596
2597 { "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } },
2598
2599 { "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RAS } },
2600
2601 { "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } },
2602
2603 { "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RAS } },
2604
2605 { "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } },
2606
2607 { "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RAS } },
2608
2609 { "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } },
2610
2611 { "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RAS } },
2612
2613 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
2614
2615 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
2616
2617 { "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } },
2618
2619 { "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RAL } },
2620
2621 { "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } },
2622
2623 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2624 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2625
2626 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2627 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2628
2629 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2630 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2631
2632 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2633 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2634
2635 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2636 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2637
2638 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2639 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2640
2641 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2642 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2643
2644 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2645 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2646
2647 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2648 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2649
2650 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2651 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2652
2653 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
2654
2655 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
2656
2657 { "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } },
2658
2659 { "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RAS } },
2660
2661 { "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2662
2663 { "frsp", XRC(63,12,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2664 { "frsp.", XRC(63,12,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2665
2666 { "fctiw", XRC(63,14,0), XRA_MASK, PPC, { FRT, FRB } },
2667 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
2668 { "fctiw.", XRC(63,14,1), XRA_MASK, PPC, { FRT, FRB } },
2669 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
2670
2671 { "fctiwz", XRC(63,15,0), XRA_MASK, PPC, { FRT, FRB } },
2672 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
2673 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPC, { FRT, FRB } },
2674 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
2675
2676 { "fdiv", A(63,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2677 { "fd", A(63,18,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2678 { "fdiv.", A(63,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2679 { "fd.", A(63,18,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2680
2681 { "fsub", A(63,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2682 { "fs", A(63,20,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2683 { "fsub.", A(63,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2684 { "fs.", A(63,20,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2685
2686 { "fadd", A(63,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2687 { "fa", A(63,21,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2688 { "fadd.", A(63,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2689 { "fa.", A(63,21,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2690
2691 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
2692 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
2693
2694 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2695 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2696
2697 { "fmul", A(63,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2698 { "fm", A(63,25,0), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2699 { "fmul.", A(63,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2700 { "fm.", A(63,25,1), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2701
2702 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2703 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2704
2705 { "fmsub", A(63,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2706 { "fms", A(63,28,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2707 { "fmsub.", A(63,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2708 { "fms.", A(63,28,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2709
2710 { "fmadd", A(63,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2711 { "fma", A(63,29,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2712 { "fmadd.", A(63,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2713 { "fma.", A(63,29,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2714
2715 { "fnmsub", A(63,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2716 { "fnms", A(63,30,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2717 { "fnmsub.", A(63,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2718 { "fnms.", A(63,30,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2719
2720 { "fnmadd", A(63,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2721 { "fnma", A(63,31,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2722 { "fnmadd.", A(63,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2723 { "fnma.", A(63,31,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2724
2725 { "fcmpo", X(63,30), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2726
2727 { "mtfsb1", XRC(63,38,0), XRARB_MASK, PPC|POWER, { BT } },
2728 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, PPC|POWER, { BT } },
2729
2730 { "fneg", XRC(63,40,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2731 { "fneg.", XRC(63,40,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2732
2733 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
2734
2735 { "mtfsb0", XRC(63,70,0), XRARB_MASK, PPC|POWER, { BT } },
2736 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, PPC|POWER, { BT } },
2737
2738 { "fmr", XRC(63,72,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2739 { "fmr.", XRC(63,72,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2740
2741 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2742 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2743
2744 { "fnabs", XRC(63,136,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2745 { "fnabs.", XRC(63,136,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2746
2747 { "fabs", XRC(63,264,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2748 { "fabs.", XRC(63,264,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2749
2750 { "mffs", XRC(63,583,0), XRARB_MASK, PPC|POWER, { FRT } },
2751 { "mffs.", XRC(63,583,1), XRARB_MASK, PPC|POWER, { FRT } },
2752
2753 { "mtfsf", XFL(63,711,0), XFL_MASK, PPC|POWER, { FLM, FRB } },
2754 { "mtfsf.", XFL(63,711,1), XFL_MASK, PPC|POWER, { FLM, FRB } },
2755
2756 { "fctid", XRC(63,814,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2757 { "fctid.", XRC(63,814,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2758
2759 { "fctidz", XRC(63,815,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2760 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2761
2762 { "fcfid", XRC(63,846,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2763 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2764
2765 };
2766
2767 const int powerpc_num_opcodes =
2768 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
2769
2770 /* The macro table. This is only used by the assembler. */
2771
2772 const struct powerpc_macro powerpc_macros[] = {
2773 { "extldi", 4, PPC|B64, "rldicr %0,%1,%3,(%2)-1" },
2774 { "extldi.", 4, PPC|B64, "rldicr. %0,%1,%3,(%2)-1" },
2775 { "extrdi", 4, PPC|B64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
2776 { "extrdi.", 4, PPC|B64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
2777 { "insrdi", 4, PPC|B64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
2778 { "insrdi.", 4, PPC|B64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
2779 { "rotrdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),0" },
2780 { "rotrdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),0" },
2781 { "sldi", 3, PPC|B64, "rldicr %0,%1,%2,63-(%2)" },
2782 { "sldi.", 3, PPC|B64, "rldicr. %0,%1,%2,63-(%2)" },
2783 { "srdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),%2" },
2784 { "srdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),%2" },
2785 { "clrrdi", 3, PPC|B64, "rldicr %0,%1,0,63-(%2)" },
2786 { "clrrdi.", 3, PPC|B64, "rldicr. %0,%1,0,63-(%2)" },
2787 { "clrlsldi",4, PPC|B64, "rldic %0,%1,%3,(%2)-(%3)" },
2788 { "clrlsldi.",4, PPC|B64, "rldic. %0,%1,%3,(%2)-(%3)" },
2789
2790 { "extlwi", 4, PPC, "rlwinm %0,%1,%3,0,(%2)-1" },
2791 { "extlwi.", 4, PPC, "rlwinm. %0,%1,%3,0,(%2)-1" },
2792 { "extrwi", 4, PPC, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
2793 { "extrwi.", 4, PPC, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
2794 { "inslwi", 4, PPC, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2795 { "inslwi.", 4, PPC, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2796 { "insrwi", 4, PPC, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
2797 { "insrwi.", 4, PPC, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
2798 { "rotrwi", 3, PPC, "rlwinm %0,%1,32-(%2),0,31" },
2799 { "rotrwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),0,31" },
2800 { "slwi", 3, PPC, "rlwinm %0,%1,%2,0,31-(%2)" },
2801 { "sli", 3, POWER, "rlinm %0,%1,%2,0,31-(%2)" },
2802 { "slwi.", 3, PPC, "rlwinm. %0,%1,%2,0,31-(%2)" },
2803 { "sli.", 3, POWER, "rlinm. %0,%1,%2,0,31-(%2)" },
2804 { "srwi", 3, PPC, "rlwinm %0,%1,32-(%2),%2,31" },
2805 { "sri", 3, POWER, "rlinm %0,%1,32-(%2),%2,31" },
2806 { "srwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),%2,31" },
2807 { "sri.", 3, POWER, "rlinm. %0,%1,32-(%2),%2,31" },
2808 { "clrrwi", 3, PPC, "rlwinm %0,%1,0,0,31-(%2)" },
2809 { "clrrwi.", 3, PPC, "rlwinm. %0,%1,0,0,31-(%2)" },
2810 { "clrlslwi",4, PPC, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
2811 { "clrlslwi.",4, PPC, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
2812
2813 };
2814
2815 const int powerpc_num_macros =
2816 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
2817