1 /*
2 * arch/ppc/platforms/setup.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 * Adapted from 'alpha' version by Gary Thomas
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 *
8 * Support for PReP (Motorola MTX/MVME)
9 * by Troy Benjegerdes (hozer@drgw.net)
10 */
11
12 /*
13 * bootup setup stuff..
14 */
15
16 #include <linux/config.h>
17 #include <linux/delay.h>
18 #include <linux/module.h>
19 #include <linux/errno.h>
20 #include <linux/sched.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/stddef.h>
24 #include <linux/unistd.h>
25 #include <linux/ptrace.h>
26 #include <linux/slab.h>
27 #include <linux/user.h>
28 #include <linux/a.out.h>
29 #include <linux/tty.h>
30 #include <linux/major.h>
31 #include <linux/interrupt.h>
32 #include <linux/reboot.h>
33 #include <linux/init.h>
34 #include <linux/blk.h>
35 #include <linux/ioport.h>
36 #include <linux/console.h>
37 #include <linux/timex.h>
38 #include <linux/pci.h>
39 #include <linux/ide.h>
40 #include <linux/seq_file.h>
41
42 #include <asm/sections.h>
43 #include <asm/mmu.h>
44 #include <asm/processor.h>
45 #include <asm/residual.h>
46 #include <asm/io.h>
47 #include <asm/pgtable.h>
48 #include <asm/cache.h>
49 #include <asm/dma.h>
50 #include <asm/machdep.h>
51 #include <asm/mk48t59.h>
52 #include <asm/prep_nvram.h>
53 #include <asm/raven.h>
54 #include <asm/keyboard.h>
55 #include <asm/vga.h>
56 #include <asm/time.h>
57 #include <asm/i8259.h>
58 #include <asm/open_pic.h>
59 #include <asm/pci-bridge.h>
60 #include <asm/bootinfo.h>
61
62 unsigned char ucSystemType;
63 unsigned char ucBoardRev;
64 unsigned char ucBoardRevMaj, ucBoardRevMin;
65
66 extern unsigned long mc146818_get_rtc_time(void);
67 extern int mc146818_set_rtc_time(unsigned long nowtime);
68 extern unsigned long mk48t59_get_rtc_time(void);
69 extern int mk48t59_set_rtc_time(unsigned long nowtime);
70
71 extern unsigned char prep_nvram_read_val(int addr);
72 extern void prep_nvram_write_val(int addr,
73 unsigned char val);
74 extern unsigned char rs_nvram_read_val(int addr);
75 extern void rs_nvram_write_val(int addr,
76 unsigned char val);
77 extern void ibm_prep_init(void);
78
79 extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
80 extern int pckbd_getkeycode(unsigned int scancode);
81 extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
82 char raw_mode);
83 extern char pckbd_unexpected_up(unsigned char keycode);
84 extern void pckbd_leds(unsigned char leds);
85 extern void pckbd_init_hw(void);
86 extern unsigned char pckbd_sysrq_xlate[];
87
88 extern void prep_find_bridges(void);
89 extern char saved_command_line[];
90
91 int _prep_type;
92
93 extern void prep_sandalfoot_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
94 extern void prep_thinkpad_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
95 extern void prep_carolina_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
96 extern void prep_tiger1_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
97
98
99 #define cached_21 (((char *)(ppc_cached_irq_mask))[3])
100 #define cached_A1 (((char *)(ppc_cached_irq_mask))[2])
101
102 /* for the mac fs */
103 kdev_t boot_dev;
104
105 #ifdef CONFIG_SOUND_CS4232
106 long ppc_cs4232_dma, ppc_cs4232_dma2;
107 #endif
108
109 extern PTE *Hash, *Hash_end;
110 extern unsigned long Hash_size, Hash_mask;
111 extern int probingmem;
112 extern unsigned long loops_per_jiffy;
113
114 #ifdef CONFIG_SOUND_CS4232
115 EXPORT_SYMBOL(ppc_cs4232_dma);
116 EXPORT_SYMBOL(ppc_cs4232_dma2);
117 #endif
118
119 /* useful ISA ports */
120 #define PREP_SYSCTL 0x81c
121 /* present in the IBM reference design; possibly identical in Mot boxes: */
122 #define PREP_IBM_SIMM_ID 0x803 /* SIMM size: 32 or 8 MiB */
123 #define PREP_IBM_SIMM_PRESENCE 0x804
124 #define PREP_IBM_EQUIPMENT 0x80c
125 #define PREP_IBM_L2INFO 0x80d
126 #define PREP_IBM_PM1 0x82a /* power management register 1 */
127 #define PREP_IBM_PLANAR 0x852 /* planar ID - identifies the motherboard */
128
129 /* Equipment Present Register masks: */
130 #define PREP_IBM_EQUIPMENT_RESERVED 0x80
131 #define PREP_IBM_EQUIPMENT_SCSIFUSE 0x40
132 #define PREP_IBM_EQUIPMENT_L2_COPYBACK 0x08
133 #define PREP_IBM_EQUIPMENT_L2_256 0x04
134 #define PREP_IBM_EQUIPMENT_CPU 0x02
135 #define PREP_IBM_EQUIPMENT_L2 0x01
136
137 /* planar ID values: */
138 /* Sandalfoot/Sandalbow (6015/7020) */
139 #define PREP_IBM_SANDALFOOT 0xfc
140 /* Woodfield, Thinkpad 850/860 (6042/7249) */
141 #define PREP_IBM_THINKPAD 0xff /* planar ID unimplemented */
142 /* PowerSeries 830/850 (6050/6070) */
143 #define PREP_IBM_CAROLINA_IDE_0 0xf0
144 #define PREP_IBM_CAROLINA_IDE_1 0xf1
145 #define PREP_IBM_CAROLINA_IDE_2 0xf2
146 /* 7248-43P */
147 #define PREP_IBM_CAROLINA_SCSI_0 0xf4
148 #define PREP_IBM_CAROLINA_SCSI_1 0xf5
149 #define PREP_IBM_CAROLINA_SCSI_2 0xf6
150 #define PREP_IBM_CAROLINA_SCSI_3 0xf7 /* missing from Carolina Tech Spec */
151 /* Tiger1 (7043-140) */
152 #define PREP_IBM_TIGER1_133 0xd1
153 #define PREP_IBM_TIGER1_166 0xd2
154 #define PREP_IBM_TIGER1_180 0xd3
155 #define PREP_IBM_TIGER1_xxx 0xd4 /* unknown, but probably exists */
156 #define PREP_IBM_TIGER1_333 0xd5 /* missing from Tiger Tech Spec */
157
158 /* setup_ibm_pci:
159 * set Motherboard_map_name, Motherboard_map, Motherboard_routes.
160 * return 8259 edge/level masks.
161 */
162 void (*setup_ibm_pci)(char *irq_lo, char *irq_hi);
163
164 extern char *Motherboard_map_name; /* for use in *_cpuinfo */
165
166 /*
167 * As found in the PReP reference implementation.
168 * Used by Thinkpad, Sandalfoot (6015/7020), and all Motorola PReP.
169 */
170 static void __init
prep_gen_enable_l2(void)171 prep_gen_enable_l2(void)
172 {
173 outb(inb(PREP_SYSCTL) | 0x3, PREP_SYSCTL);
174 }
175
176 /* Used by Carolina and Tiger1 */
177 static void __init
prep_carolina_enable_l2(void)178 prep_carolina_enable_l2(void)
179 {
180 outb(inb(PREP_SYSCTL) | 0xc0, PREP_SYSCTL);
181 }
182
183 /* cpuinfo code common to all IBM PReP */
184 static void __prep
prep_ibm_cpuinfo(struct seq_file * m)185 prep_ibm_cpuinfo(struct seq_file *m)
186 {
187 unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
188
189 seq_printf(m, "machine\t\t: PReP %s\n", Motherboard_map_name);
190
191 seq_printf(m, "upgrade cpu\t: ");
192 if (equip_reg & PREP_IBM_EQUIPMENT_CPU) {
193 seq_printf(m, "not ");
194 }
195 seq_printf(m, "present\n");
196
197 /* print info about the SCSI fuse */
198 seq_printf(m, "scsi fuse\t: ");
199 if (equip_reg & PREP_IBM_EQUIPMENT_SCSIFUSE)
200 seq_printf(m, "ok");
201 else
202 seq_printf(m, "bad");
203 seq_printf(m, "\n");
204
205 #ifdef CONFIG_PREP_RESIDUAL
206 /* print info about SIMMs */
207 if (res->ResidualLength != 0) {
208 int i;
209 seq_printf(m, "simms\t\t: ");
210 for (i = 0; (res->ActualNumMemories) && (i < MAX_MEMS); i++) {
211 if (res->Memories[i].SIMMSize != 0)
212 seq_printf(m, "%d:%ldMiB ", i,
213 (res->Memories[i].SIMMSize > 1024) ?
214 res->Memories[i].SIMMSize>>20 :
215 res->Memories[i].SIMMSize);
216 }
217 seq_printf(m, "\n");
218 }
219 #endif
220 }
221
222 static int __prep
prep_sandalfoot_cpuinfo(struct seq_file * m)223 prep_sandalfoot_cpuinfo(struct seq_file *m)
224 {
225 unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
226
227 prep_ibm_cpuinfo(m);
228
229 /* report amount and type of L2 cache present */
230 seq_printf(m, "L2 cache\t: ");
231 if (equip_reg & PREP_IBM_EQUIPMENT_L2) {
232 seq_printf(m, "not present");
233 } else {
234 if (equip_reg & PREP_IBM_EQUIPMENT_L2_256)
235 seq_printf(m, "256KiB");
236 else
237 seq_printf(m, "unknown size");
238
239 if (equip_reg & PREP_IBM_EQUIPMENT_L2_COPYBACK)
240 seq_printf(m, ", copy-back");
241 else
242 seq_printf(m, ", write-through");
243 }
244 seq_printf(m, "\n");
245
246 return 0;
247 }
248
249 static int __prep
prep_thinkpad_cpuinfo(struct seq_file * m)250 prep_thinkpad_cpuinfo(struct seq_file *m)
251 {
252 unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
253 char *cpubus_speed, *pci_speed;
254
255 prep_ibm_cpuinfo(m);
256
257 /* report amount and type of L2 cache present */
258 seq_printf(m, "l2 cache\t: ");
259 if ((equip_reg & 0x1) == 0) {
260 switch ((equip_reg & 0xc) >> 2) {
261 case 0x0:
262 seq_printf(m, "128KiB look-aside 2-way write-through\n");
263 break;
264 case 0x1:
265 seq_printf(m, "512KiB look-aside direct-mapped write-back\n");
266 break;
267 case 0x2:
268 seq_printf(m, "256KiB look-aside 2-way write-through\n");
269 break;
270 case 0x3:
271 seq_printf(m, "256KiB look-aside direct-mapped write-back\n");
272 break;
273 }
274 } else {
275 seq_printf(m, "not present\n");
276 }
277
278 /* report bus speeds because we can */
279 if ((equip_reg & 0x80) == 0) {
280 switch ((equip_reg & 0x30) >> 4) {
281 case 0x1:
282 cpubus_speed = "50";
283 pci_speed = "25";
284 break;
285 case 0x3:
286 cpubus_speed = "66";
287 pci_speed = "33";
288 break;
289 default:
290 cpubus_speed = "unknown";
291 pci_speed = "unknown";
292 break;
293 }
294 } else {
295 switch ((equip_reg & 0x30) >> 4) {
296 case 0x1:
297 cpubus_speed = "25";
298 pci_speed = "25";
299 break;
300 case 0x2:
301 cpubus_speed = "60";
302 pci_speed = "30";
303 break;
304 case 0x3:
305 cpubus_speed = "33";
306 pci_speed = "33";
307 break;
308 default:
309 cpubus_speed = "unknown";
310 pci_speed = "unknown";
311 break;
312 }
313 }
314 seq_printf(m, "60x bus\t\t: %sMHz\n", cpubus_speed);
315 seq_printf(m, "pci bus\t\t: %sMHz\n", pci_speed);
316
317 return 0;
318 }
319
320 static int __prep
prep_carolina_cpuinfo(struct seq_file * m)321 prep_carolina_cpuinfo(struct seq_file *m)
322 {
323 unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
324
325 prep_ibm_cpuinfo(m);
326
327 /* report amount and type of L2 cache present */
328 seq_printf(m, "l2 cache\t: ");
329 if ((equip_reg & 0x1) == 0) {
330 unsigned int l2_reg = inb(PREP_IBM_L2INFO);
331
332 /* L2 size */
333 switch ((l2_reg & 0x60) >> 5) {
334 case 0:
335 seq_printf(m, "256KiB");
336 break;
337 case 1:
338 seq_printf(m, "512KiB");
339 break;
340 default:
341 seq_printf(m, "unknown size");
342 break;
343 }
344
345 /* L2 type */
346 if ((l2_reg & 0x3) == 0)
347 seq_printf(m, ", async");
348 else if ((l2_reg & 0x3) == 1)
349 seq_printf(m, ", sync");
350 else
351 seq_printf(m, ", unknown type");
352
353 seq_printf(m, "\n");
354 } else {
355 seq_printf(m, "not present\n");
356 }
357
358 return 0;
359 }
360
361 static int __prep
prep_tiger1_cpuinfo(struct seq_file * m)362 prep_tiger1_cpuinfo(struct seq_file *m)
363 {
364 unsigned int l2_reg = inb(PREP_IBM_L2INFO);
365
366 prep_ibm_cpuinfo(m);
367
368 /* report amount and type of L2 cache present */
369 seq_printf(m, "l2 cache\t: ");
370 if ((l2_reg & 0xf) == 0xf) {
371 seq_printf(m, "not present\n");
372 } else {
373 if (l2_reg & 0x8)
374 seq_printf(m, "async, ");
375 else
376 seq_printf(m, "sync burst, ");
377
378 if (l2_reg & 0x4)
379 seq_printf(m, "parity, ");
380 else
381 seq_printf(m, "no parity, ");
382
383 switch (l2_reg & 0x3) {
384 case 0x0:
385 seq_printf(m, "256KiB\n");
386 break;
387 case 0x1:
388 seq_printf(m, "512KiB\n");
389 break;
390 case 0x2:
391 seq_printf(m, "1MiB\n");
392 break;
393 default:
394 seq_printf(m, "unknown size\n");
395 break;
396 }
397 }
398
399 return 0;
400 }
401
402
403 /* Used by all Motorola PReP */
404 static int __prep
prep_mot_cpuinfo(struct seq_file * m)405 prep_mot_cpuinfo(struct seq_file *m)
406 {
407 unsigned int cachew = *((unsigned char *)CACHECRBA);
408
409 seq_printf(m, "machine\t\t: PReP %s\n", Motherboard_map_name);
410
411 /* report amount and type of L2 cache present */
412 seq_printf(m, "l2 cache\t: ");
413 switch (cachew & L2CACHE_MASK) {
414 case L2CACHE_512KB:
415 seq_printf(m, "512KiB");
416 break;
417 case L2CACHE_256KB:
418 seq_printf(m, "256KiB");
419 break;
420 case L2CACHE_1MB:
421 seq_printf(m, "1MiB");
422 break;
423 case L2CACHE_NONE:
424 seq_printf(m, "none\n");
425 goto no_l2;
426 break;
427 default:
428 seq_printf(m, "%x\n", cachew);
429 }
430
431 seq_printf(m, ", parity %s",
432 (cachew & L2CACHE_PARITY)? "enabled" : "disabled");
433
434 seq_printf(m, " SRAM:");
435
436 switch ( ((cachew & 0xf0) >> 4) & ~(0x3) ) {
437 case 1: seq_printf(m, "synchronous, parity, flow-through\n");
438 break;
439 case 2: seq_printf(m, "asynchronous, no parity\n");
440 break;
441 case 3: seq_printf(m, "asynchronous, parity\n");
442 break;
443 default:seq_printf(m, "synchronous, pipelined, no parity\n");
444 break;
445 }
446
447 no_l2:
448 #ifdef CONFIG_PREP_RESIDUAL
449 /* print info about SIMMs */
450 if (res->ResidualLength != 0) {
451 int i;
452 seq_printf(m, "simms\t\t: ");
453 for (i = 0; (res->ActualNumMemories) && (i < MAX_MEMS); i++) {
454 if (res->Memories[i].SIMMSize != 0)
455 seq_printf(m, "%d:%ldM ", i,
456 (res->Memories[i].SIMMSize > 1024) ?
457 res->Memories[i].SIMMSize>>20 :
458 res->Memories[i].SIMMSize);
459 }
460 seq_printf(m, "\n");
461 }
462 #endif
463
464 return 0;
465 }
466
467 static void __prep
prep_restart(char * cmd)468 prep_restart(char *cmd)
469 {
470 #define PREP_SP92 0x92 /* Special Port 92 */
471 __cli(); /* no interrupts */
472
473 /* set exception prefix high - to the prom */
474 _nmask_and_or_msr(0, MSR_IP);
475
476 /* make sure bit 0 (reset) is a 0 */
477 outb( inb(PREP_SP92) & ~1L , PREP_SP92);
478 /* signal a reset to system control port A - soft reset */
479 outb( inb(PREP_SP92) | 1 , PREP_SP92);
480
481 while ( 1 ) ;
482 /* not reached */
483 #undef PREP_SP92
484 }
485
486 static void __prep
prep_halt(void)487 prep_halt(void)
488 {
489 __cli(); /* no interrupts */
490
491 /* set exception prefix high - to the prom */
492 _nmask_and_or_msr(0, MSR_IP);
493
494 while ( 1 ) ;
495 /* not reached */
496 }
497
498 /* Carrera is the power manager in the Thinkpads. Unfortunately not much is
499 * known about it, so we can't power down.
500 */
501 static void __prep
prep_carrera_poweroff(void)502 prep_carrera_poweroff(void)
503 {
504 prep_halt();
505 }
506
507 /*
508 * On most IBM PReP's, power management is handled by a Signetics 87c750
509 * behind the Utah component on the ISA bus. To access the 750 you must write
510 * a series of nibbles to port 0x82a (decoded by the Utah). This is described
511 * somewhat in the IBM Carolina Technical Specification.
512 * -Hollis
513 */
514 static void __prep
utah_sig87c750_setbit(unsigned int bytenum,unsigned int bitnum,int value)515 utah_sig87c750_setbit(unsigned int bytenum, unsigned int bitnum, int value)
516 {
517 /*
518 * byte1: 0 0 0 1 0 d a5 a4
519 * byte2: 0 0 0 1 a3 a2 a1 a0
520 *
521 * d = the bit's value, enabled or disabled
522 * (a5 a4 a3) = the byte number, minus 20
523 * (a2 a1 a0) = the bit number
524 *
525 * example: set the 5th bit of byte 21 (21.5)
526 * a5 a4 a3 = 001 (byte 1)
527 * a2 a1 a0 = 101 (bit 5)
528 *
529 * byte1 = 0001 0100 (0x14)
530 * byte2 = 0001 1101 (0x1d)
531 */
532 unsigned char byte1=0x10, byte2=0x10;
533
534 /* the 750's '20.0' is accessed as '0.0' through Utah (which adds 20) */
535 bytenum -= 20;
536
537 byte1 |= (!!value) << 2; /* set d */
538 byte1 |= (bytenum >> 1) & 0x3; /* set a5, a4 */
539
540 byte2 |= (bytenum & 0x1) << 3; /* set a3 */
541 byte2 |= bitnum & 0x7; /* set a2, a1, a0 */
542
543 outb(byte1, PREP_IBM_PM1); /* first nibble */
544 mb();
545 udelay(100); /* important: let controller recover */
546
547 outb(byte2, PREP_IBM_PM1); /* second nibble */
548 mb();
549 udelay(100); /* important: let controller recover */
550 }
551
552 static void __prep
prep_sig750_poweroff(void)553 prep_sig750_poweroff(void)
554 {
555 /* tweak the power manager found in most IBM PRePs (except Thinkpads) */
556 unsigned long flags;
557 __cli();
558 /* set exception prefix high - to the prom */
559 save_flags( flags );
560 restore_flags( flags|MSR_IP );
561
562 utah_sig87c750_setbit(21, 5, 1); /* set bit 21.5, "PMEXEC_OFF" */
563
564 while (1) ;
565 /* not reached */
566 }
567
568 static int __prep
prep_show_percpuinfo(struct seq_file * m,int i)569 prep_show_percpuinfo(struct seq_file *m, int i)
570 {
571 /* PREP's without residual data will give incorrect values here */
572 seq_printf(m, "clock\t\t: ");
573 #ifdef CONFIG_PREP_RESIDUAL
574 if (res->ResidualLength)
575 seq_printf(m, "%ldMHz\n",
576 (res->VitalProductData.ProcessorHz > 1024) ?
577 res->VitalProductData.ProcessorHz / 1000000 :
578 res->VitalProductData.ProcessorHz);
579 else
580 #endif /* CONFIG_PREP_RESIDUAL */
581 seq_printf(m, "???\n");
582
583 return 0;
584 }
585
586 #ifdef CONFIG_SOUND_CS4232
masktoint(unsigned int i)587 static long __init masktoint(unsigned int i)
588 {
589 int t = -1;
590 while (i >> ++t)
591 ;
592 return (t-1);
593 }
594
595 /*
596 * ppc_cs4232_dma and ppc_cs4232_dma2 are used in include/asm/dma.h
597 * to distinguish sound dma-channels from others. This is because
598 * blocksize on 16 bit dma-channels 5,6,7 is 128k, but
599 * the cs4232.c uses 64k like on 8 bit dma-channels 0,1,2,3
600 */
601
prep_init_sound(void)602 static void __init prep_init_sound(void)
603 {
604 PPC_DEVICE *audiodevice = NULL;
605
606 /*
607 * Get the needed resource informations from residual data.
608 *
609 */
610 #ifdef CONFIG_PREP_RESIDUAL
611 audiodevice = residual_find_device(~0, NULL, MultimediaController,
612 AudioController, -1, 0);
613 if (audiodevice != NULL) {
614 PnP_TAG_PACKET *pkt;
615
616 pkt = PnP_find_packet((unsigned char *)&res->DevicePnPHeap[audiodevice->AllocatedOffset],
617 S5_Packet, 0);
618 if (pkt != NULL)
619 ppc_cs4232_dma = masktoint(pkt->S5_Pack.DMAMask);
620 pkt = PnP_find_packet((unsigned char*)&res->DevicePnPHeap[audiodevice->AllocatedOffset],
621 S5_Packet, 1);
622 if (pkt != NULL)
623 ppc_cs4232_dma2 = masktoint(pkt->S5_Pack.DMAMask);
624 }
625 #endif
626
627 /*
628 * These are the PReP specs' defaults for the cs4231. We use these
629 * as fallback incase we don't have residual data.
630 * At least the IBM Thinkpad 850 with IDE DMA Channels at 6 and 7
631 * will use the other values.
632 */
633 if (audiodevice == NULL) {
634 switch (_prep_type) {
635 case _PREP_IBM:
636 ppc_cs4232_dma = 1;
637 ppc_cs4232_dma2 = -1;
638 break;
639 default:
640 ppc_cs4232_dma = 6;
641 ppc_cs4232_dma2 = 7;
642 }
643 }
644
645 /*
646 * Find a way to push these informations to the cs4232 driver
647 * Give it out with printk, when not in cmd_line?
648 * Append it to cmd_line and saved_command_line?
649 * Format is cs4232=io,irq,dma,dma2
650 */
651 }
652 #endif /* CONFIG_SOUND_CS4232 */
653
654 /*
655 * Fill out screen_info according to the residual data. This allows us to use
656 * at least vesafb.
657 */
658 static void __init
prep_init_vesa(void)659 prep_init_vesa(void)
660 {
661 #if defined(CONFIG_PREP_RESIDUAL) && \
662 (defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_FB))
663 PPC_DEVICE *vgadev;
664
665 vgadev = residual_find_device(~0, NULL, DisplayController, SVGAController,
666 -1, 0);
667 if (vgadev != NULL) {
668 PnP_TAG_PACKET *pkt;
669
670 pkt = PnP_find_large_vendor_packet(
671 (unsigned char *)&res->DevicePnPHeap[vgadev->AllocatedOffset],
672 0x04, 0); /* 0x04 = Display Tag */
673 if (pkt != NULL) {
674 unsigned char *ptr = (unsigned char *)pkt;
675
676 if (ptr[4]) {
677 /* graphics mode */
678 screen_info.orig_video_isVGA = VIDEO_TYPE_VLFB;
679
680 screen_info.lfb_depth = ptr[4] * 8;
681
682 screen_info.lfb_width = swab16(*(short *)(ptr+6));
683 screen_info.lfb_height = swab16(*(short *)(ptr+8));
684 screen_info.lfb_linelength = swab16(*(short *)(ptr+10));
685
686 screen_info.lfb_base = swab32(*(long *)(ptr+12));
687 screen_info.lfb_size = swab32(*(long *)(ptr+20)) / 65536;
688 }
689 }
690 }
691 #endif /* CONFIG_PREP_RESIDUAL */
692 }
693
694 static void __init
prep_setup_arch(void)695 prep_setup_arch(void)
696 {
697 unsigned char reg;
698 int is_ide=0;
699
700 /* init to some ~sane value until calibrate_delay() runs */
701 loops_per_jiffy = 50000000;
702
703 /* Lookup PCI host bridges */
704 prep_find_bridges();
705
706 /* Set up floppy in PS/2 mode */
707 outb(0x09, SIO_CONFIG_RA);
708 reg = inb(SIO_CONFIG_RD);
709 reg = (reg & 0x3F) | 0x40;
710 outb(reg, SIO_CONFIG_RD);
711 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
712
713 switch ( _prep_type )
714 {
715 case _PREP_IBM:
716 reg = inb(PREP_IBM_PLANAR);
717 printk(KERN_INFO "IBM planar ID: %08x", reg);
718 switch (reg) {
719 case PREP_IBM_SANDALFOOT:
720 prep_gen_enable_l2();
721 setup_ibm_pci = prep_sandalfoot_setup_pci;
722 ppc_md.power_off = prep_sig750_poweroff;
723 ppc_md.show_cpuinfo = prep_sandalfoot_cpuinfo;
724 break;
725 case PREP_IBM_THINKPAD:
726 prep_gen_enable_l2();
727 setup_ibm_pci = prep_thinkpad_setup_pci;
728 ppc_md.power_off = prep_carrera_poweroff;
729 ppc_md.show_cpuinfo = prep_thinkpad_cpuinfo;
730 break;
731 default:
732 printk(" -- unknown! Assuming Carolina");
733 case PREP_IBM_CAROLINA_IDE_0:
734 case PREP_IBM_CAROLINA_IDE_1:
735 case PREP_IBM_CAROLINA_IDE_2:
736 is_ide = 1;
737 case PREP_IBM_CAROLINA_SCSI_0:
738 case PREP_IBM_CAROLINA_SCSI_1:
739 case PREP_IBM_CAROLINA_SCSI_2:
740 case PREP_IBM_CAROLINA_SCSI_3:
741 prep_carolina_enable_l2();
742 setup_ibm_pci = prep_carolina_setup_pci;
743 ppc_md.power_off = prep_sig750_poweroff;
744 ppc_md.show_cpuinfo = prep_carolina_cpuinfo;
745 break;
746 case PREP_IBM_TIGER1_133:
747 case PREP_IBM_TIGER1_166:
748 case PREP_IBM_TIGER1_180:
749 case PREP_IBM_TIGER1_xxx:
750 case PREP_IBM_TIGER1_333:
751 prep_carolina_enable_l2();
752 setup_ibm_pci = prep_tiger1_setup_pci;
753 ppc_md.power_off = prep_sig750_poweroff;
754 ppc_md.show_cpuinfo = prep_tiger1_cpuinfo;
755 break;
756 }
757 printk("\n");
758
759 /* default root device */
760 if (is_ide)
761 ROOT_DEV = to_kdev_t(0x0303); /* hda3 */
762 else
763 ROOT_DEV = to_kdev_t(0x0803); /* sda3 */
764
765 break;
766 case _PREP_Motorola:
767 prep_gen_enable_l2();
768 ppc_md.power_off = prep_halt;
769 ppc_md.show_cpuinfo = prep_mot_cpuinfo;
770
771 #ifdef CONFIG_BLK_DEV_INITRD
772 if (initrd_start)
773 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); /* /dev/ram */
774 else
775 #endif
776 #ifdef CONFIG_ROOT_NFS
777 ROOT_DEV = to_kdev_t(0x00ff); /* /dev/nfs */
778 #else
779 ROOT_DEV = to_kdev_t(0x0802); /* /dev/sda2 */
780 #endif
781 break;
782 }
783
784 /* Read in NVRAM data */
785 init_prep_nvram();
786
787 /* if no bootargs, look in NVRAM */
788 if ( cmd_line[0] == '\0' ) {
789 char *bootargs;
790 bootargs = prep_nvram_get_var("bootargs");
791 if (bootargs != NULL) {
792 strcpy(cmd_line, bootargs);
793 /* again.. */
794 strcpy(saved_command_line, cmd_line);
795 }
796 }
797
798 #ifdef CONFIG_SOUND_CS4232
799 prep_init_sound();
800 #endif /* CONFIG_SOUND_CS4232 */
801
802 prep_init_vesa();
803
804 switch (_prep_type) {
805 case _PREP_Motorola:
806 raven_init();
807 break;
808 case _PREP_IBM:
809 ibm_prep_init();
810 break;
811 }
812
813 #ifdef CONFIG_VGA_CONSOLE
814 /* vgacon.c needs to know where we mapped IO memory in io_block_mapping() */
815 vgacon_remap_base = 0xf0000000;
816 conswitchp = &vga_con;
817 #elif defined(CONFIG_DUMMY_CONSOLE)
818 conswitchp = &dummy_con;
819 #endif
820 }
821
822 /*
823 * Determine the decrementer frequency from the residual data
824 * This allows for a faster boot as we do not need to calibrate the
825 * decrementer against another clock. This is important for embedded systems.
826 */
827 static int __init
prep_res_calibrate_decr(void)828 prep_res_calibrate_decr(void)
829 {
830 #ifdef CONFIG_PREP_RESIDUAL
831 unsigned long freq, divisor = 4;
832
833 if ( res->VitalProductData.ProcessorBusHz ) {
834 freq = res->VitalProductData.ProcessorBusHz;
835 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
836 (freq/divisor)/1000000,
837 (freq/divisor)%1000000);
838 tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
839 tb_ticks_per_jiffy = freq / HZ / divisor;
840 return 0;
841 } else
842 #endif
843 return 1;
844 }
845
846 /*
847 * Uses the on-board timer to calibrate the on-chip decrementer register
848 * for prep systems. On the pmac the OF tells us what the frequency is
849 * but on prep we have to figure it out.
850 * -- Cort
851 */
852 /* Done with 3 interrupts: the first one primes the cache and the
853 * 2 following ones measure the interval. The precision of the method
854 * is still doubtful due to the short interval sampled.
855 */
856 static volatile int calibrate_steps __initdata = 3;
857 static unsigned tbstamp __initdata = 0;
858
859 static void __init
prep_calibrate_decr_handler(int irq,void * dev,struct pt_regs * regs)860 prep_calibrate_decr_handler(int irq, void *dev, struct pt_regs *regs)
861 {
862 unsigned long t, freq;
863 int step=--calibrate_steps;
864
865 t = get_tbl();
866 if (step > 0) {
867 tbstamp = t;
868 } else {
869 freq = (t - tbstamp)*HZ;
870 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
871 freq/1000000, freq%1000000);
872 tb_ticks_per_jiffy = freq / HZ;
873 tb_to_us = mulhwu_scale_factor(freq, 1000000);
874 }
875 }
876
877 static void __init
prep_calibrate_decr(void)878 prep_calibrate_decr(void)
879 {
880 int res;
881
882 /* Try and get this from the residual data. */
883 res = prep_res_calibrate_decr();
884
885 /* If we didn't get it from the residual data, try this. */
886 if ( res ) {
887 unsigned long flags;
888
889 save_flags(flags);
890
891 #define TIMER0_COUNT 0x40
892 #define TIMER_CONTROL 0x43
893 /* set timer to periodic mode */
894 outb_p(0x34,TIMER_CONTROL);/* binary, mode 2, LSB/MSB, ch 0 */
895 /* set the clock to ~100 Hz */
896 outb_p(LATCH & 0xff , TIMER0_COUNT); /* LSB */
897 outb(LATCH >> 8 , TIMER0_COUNT); /* MSB */
898
899 if (request_irq(0, prep_calibrate_decr_handler, 0, "timer", NULL) != 0)
900 panic("Could not allocate timer IRQ!");
901 __sti();
902 /* wait for calibrate */
903 while ( calibrate_steps )
904 ;
905 restore_flags(flags);
906 free_irq( 0, NULL);
907 }
908 }
909
910 static long __init
mk48t59_init(void)911 mk48t59_init(void) {
912 unsigned char tmp;
913
914 tmp = ppc_md.nvram_read_val(MK48T59_RTC_CONTROLB);
915 if (tmp & MK48T59_RTC_CB_STOP) {
916 printk("Warning: RTC was stopped, date will be wrong.\n");
917 ppc_md.nvram_write_val(MK48T59_RTC_CONTROLB,
918 tmp & ~MK48T59_RTC_CB_STOP);
919 /* Low frequency crystal oscillators may take a very long
920 * time to startup and stabilize. For now just ignore the
921 * the issue, but attempting to calibrate the decrementer
922 * from the RTC just after this wakeup is likely to be very
923 * inaccurate. Firmware should not allow to load
924 * the OS with the clock stopped anyway...
925 */
926 }
927 /* Ensure that the clock registers are updated */
928 tmp = ppc_md.nvram_read_val(MK48T59_RTC_CONTROLA);
929 tmp &= ~(MK48T59_RTC_CA_READ | MK48T59_RTC_CA_WRITE);
930 ppc_md.nvram_write_val(MK48T59_RTC_CONTROLA, tmp);
931 return 0;
932 }
933
934 /* We use the NVRAM RTC to time a second to calibrate the decrementer,
935 * the RTC registers have just been set up in the right state by the
936 * preceding routine.
937 */
938 static void __init
mk48t59_calibrate_decr(void)939 mk48t59_calibrate_decr(void)
940 {
941 unsigned long freq;
942 unsigned long t1;
943 unsigned char save_control;
944 long i;
945 unsigned char sec;
946
947
948 /* Make sure the time is not stopped. */
949 save_control = ppc_md.nvram_read_val(MK48T59_RTC_CONTROLB);
950
951 ppc_md.nvram_write_val(MK48T59_RTC_CONTROLA,
952 (save_control & (~MK48T59_RTC_CB_STOP)));
953
954 /* Now make sure the read bit is off so the value will change. */
955 save_control = ppc_md.nvram_read_val(MK48T59_RTC_CONTROLA);
956 save_control &= ~MK48T59_RTC_CA_READ;
957 ppc_md.nvram_write_val(MK48T59_RTC_CONTROLA, save_control);
958
959
960 /* Read the seconds value to see when it changes. */
961 sec = ppc_md.nvram_read_val(MK48T59_RTC_SECONDS);
962 /* Actually this is bad for precision, we should have a loop in
963 * which we only read the seconds counter. nvram_read_val writes
964 * the address bytes on every call and this takes a lot of time.
965 * Perhaps an nvram_wait_change method returning a time
966 * stamp with a loop count as parameter would be the solution.
967 */
968 for (i = 0 ; i < 1000000 ; i++) { /* may take up to 1 second... */
969 t1 = get_tbl();
970 if (ppc_md.nvram_read_val(MK48T59_RTC_SECONDS) != sec) {
971 break;
972 }
973 }
974
975 sec = ppc_md.nvram_read_val(MK48T59_RTC_SECONDS);
976 for (i = 0 ; i < 1000000 ; i++) { /* Should take up 1 second... */
977 freq = get_tbl()-t1;
978 if (ppc_md.nvram_read_val(MK48T59_RTC_SECONDS) != sec)
979 break;
980 }
981
982 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
983 freq/1000000, freq%1000000);
984 tb_ticks_per_jiffy = freq / HZ;
985 tb_to_us = mulhwu_scale_factor(freq, 1000000);
986 }
987
988 static unsigned int __prep
prep_irq_cannonicalize(u_int irq)989 prep_irq_cannonicalize(u_int irq)
990 {
991 if (irq == 2)
992 {
993 return 9;
994 }
995 else
996 {
997 return irq;
998 }
999 }
1000
1001 static void __init
prep_init_IRQ(void)1002 prep_init_IRQ(void)
1003 {
1004 int i;
1005 unsigned int pci_viddid, pci_did;
1006
1007 if (OpenPIC_Addr != NULL) {
1008 openpic_init(NUM_8259_INTERRUPTS);
1009 /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
1010 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
1011 i8259_irq);
1012 }
1013 for (i = 0; i < NUM_8259_INTERRUPTS; i++)
1014 irq_desc[i].handler = &i8259_pic;
1015 /* If we have a Raven PCI bridge or a Hawk PCI bridge / Memory
1016 * controller, we poll (as they have a different int-ack address). */
1017 early_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &pci_viddid);
1018 pci_did = (pci_viddid & 0xffff0000) >> 16;
1019 if (((pci_viddid & 0xffff) == PCI_VENDOR_ID_MOTOROLA)
1020 && ((pci_did == PCI_DEVICE_ID_MOTOROLA_RAVEN)
1021 || (pci_did == PCI_DEVICE_ID_MOTOROLA_HAWK)))
1022 i8259_init(0);
1023 else
1024 /* PCI interrupt ack address given in section 6.1.8 of the
1025 * PReP specification. */
1026 i8259_init(0xbffffff0);
1027 }
1028
1029 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
1030 /*
1031 * IDE stuff.
1032 */
1033 static int __prep
prep_ide_default_irq(ide_ioreg_t base)1034 prep_ide_default_irq(ide_ioreg_t base)
1035 {
1036 switch (base) {
1037 case 0x1f0: return 13;
1038 case 0x170: return 13;
1039 case 0x1e8: return 11;
1040 case 0x168: return 10;
1041 case 0xfff0: return 14; /* MCP(N)750 ide0 */
1042 case 0xffe0: return 15; /* MCP(N)750 ide1 */
1043 default: return 0;
1044 }
1045 }
1046
1047 static ide_ioreg_t __prep
prep_ide_default_io_base(int index)1048 prep_ide_default_io_base(int index)
1049 {
1050 switch (index) {
1051 case 0: return 0x1f0;
1052 case 1: return 0x170;
1053 case 2: return 0x1e8;
1054 case 3: return 0x168;
1055 default:
1056 return 0;
1057 }
1058 }
1059 #endif
1060
1061 #ifdef CONFIG_SMP
1062 /* PReP (MTX) support */
1063 static int __init
smp_prep_probe(void)1064 smp_prep_probe(void)
1065 {
1066 extern int mot_multi;
1067
1068 if (mot_multi) {
1069 openpic_request_IPIs();
1070 smp_hw_index[1] = 1;
1071 return 2;
1072 }
1073
1074 return 1;
1075 }
1076
1077 static void __init
smp_prep_kick_cpu(int nr)1078 smp_prep_kick_cpu(int nr)
1079 {
1080 *(unsigned long *)KERNELBASE = nr;
1081 asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory");
1082 printk("CPU1 released, waiting\n");
1083 }
1084
1085 static void __init
smp_prep_setup_cpu(int cpu_nr)1086 smp_prep_setup_cpu(int cpu_nr)
1087 {
1088 if (OpenPIC_Addr)
1089 do_openpic_setup_cpu();
1090 }
1091
1092 static struct smp_ops_t prep_smp_ops __prepdata = {
1093 smp_openpic_message_pass,
1094 smp_prep_probe,
1095 smp_prep_kick_cpu,
1096 smp_prep_setup_cpu,
1097 };
1098 #endif /* CONFIG_SMP */
1099
1100 /*
1101 * What ever boots us must pass in the ammount of memory.
1102 */
1103 static unsigned long __init
prep_find_end_of_memory(void)1104 prep_find_end_of_memory(void)
1105 {
1106 return boot_mem_size;
1107 }
1108
1109 /*
1110 * Setup the bat mappings we're going to load that cover
1111 * the io areas. RAM was mapped by mapin_ram().
1112 * -- Cort
1113 */
1114 static void __init
prep_map_io(void)1115 prep_map_io(void)
1116 {
1117 io_block_mapping(0x80000000, PREP_ISA_IO_BASE, 0x10000000, _PAGE_IO);
1118 io_block_mapping(0xf0000000, PREP_ISA_MEM_BASE, 0x08000000, _PAGE_IO);
1119 }
1120
1121 static void __init
prep_init2(void)1122 prep_init2(void)
1123 {
1124 #ifdef CONFIG_NVRAM
1125 request_region(PREP_NVRAM_AS0, 0x8, "nvram");
1126 #endif
1127 request_region(0x00,0x20,"dma1");
1128 request_region(0x40,0x20,"timer");
1129 request_region(0x80,0x10,"dma page reg");
1130 request_region(0xc0,0x20,"dma2");
1131 }
1132
1133 void __init
prep_init(unsigned long r3,unsigned long r4,unsigned long r5,unsigned long r6,unsigned long r7)1134 prep_init(unsigned long r3, unsigned long r4, unsigned long r5,
1135 unsigned long r6, unsigned long r7)
1136 {
1137 #ifdef CONFIG_PREP_RESIDUAL
1138 /* make a copy of residual data */
1139 if ( r3 ) {
1140 memcpy((void *)res,(void *)(r3+KERNELBASE),
1141 sizeof(RESIDUAL));
1142 }
1143 #endif
1144
1145 isa_io_base = PREP_ISA_IO_BASE;
1146 isa_mem_base = PREP_ISA_MEM_BASE;
1147 pci_dram_offset = PREP_PCI_DRAM_OFFSET;
1148 ISA_DMA_THRESHOLD = 0x00ffffff;
1149 DMA_MODE_READ = 0x44;
1150 DMA_MODE_WRITE = 0x48;
1151
1152 /* figure out what kind of prep workstation we are */
1153 #ifdef CONFIG_PREP_RESIDUAL
1154 if ( res->ResidualLength != 0 ) {
1155 if ( !strncmp(res->VitalProductData.PrintableModel,"IBM",3) )
1156 _prep_type = _PREP_IBM;
1157 else
1158 _prep_type = _PREP_Motorola;
1159 } else /* assume motorola if no residual (netboot?) */
1160 #endif
1161 {
1162 _prep_type = _PREP_Motorola;
1163 }
1164
1165 ppc_md.setup_arch = prep_setup_arch;
1166 ppc_md.show_percpuinfo = prep_show_percpuinfo;
1167 ppc_md.show_cpuinfo = NULL; /* set in prep_setup_arch() */
1168 ppc_md.irq_cannonicalize = prep_irq_cannonicalize;
1169 ppc_md.init_IRQ = prep_init_IRQ;
1170 /* this gets changed later on if we have an OpenPIC -- Cort */
1171 ppc_md.get_irq = i8259_irq;
1172 ppc_md.init = prep_init2;
1173
1174 ppc_md.restart = prep_restart;
1175 ppc_md.power_off = NULL; /* set in prep_setup_arch() */
1176 ppc_md.halt = prep_halt;
1177
1178 ppc_md.nvram_read_val = prep_nvram_read_val;
1179 ppc_md.nvram_write_val = prep_nvram_write_val;
1180
1181 ppc_md.time_init = NULL;
1182 if (_prep_type == _PREP_IBM) {
1183 ppc_md.set_rtc_time = mc146818_set_rtc_time;
1184 ppc_md.get_rtc_time = mc146818_get_rtc_time;
1185 ppc_md.calibrate_decr = prep_calibrate_decr;
1186 } else {
1187 ppc_md.set_rtc_time = mk48t59_set_rtc_time;
1188 ppc_md.get_rtc_time = mk48t59_get_rtc_time;
1189 ppc_md.calibrate_decr = mk48t59_calibrate_decr;
1190 ppc_md.time_init = mk48t59_init;
1191 }
1192
1193 ppc_md.find_end_of_memory = prep_find_end_of_memory;
1194 ppc_md.setup_io_mappings = prep_map_io;
1195
1196 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
1197 ppc_ide_md.default_irq = prep_ide_default_irq;
1198 ppc_ide_md.default_io_base = prep_ide_default_io_base;
1199 #endif
1200
1201 #ifdef CONFIG_VT
1202 ppc_md.kbd_setkeycode = pckbd_setkeycode;
1203 ppc_md.kbd_getkeycode = pckbd_getkeycode;
1204 ppc_md.kbd_translate = pckbd_translate;
1205 ppc_md.kbd_unexpected_up = pckbd_unexpected_up;
1206 ppc_md.kbd_leds = pckbd_leds;
1207 ppc_md.kbd_init_hw = pckbd_init_hw;
1208 #ifdef CONFIG_MAGIC_SYSRQ
1209 ppc_md.ppc_kbd_sysrq_xlate = pckbd_sysrq_xlate;
1210 SYSRQ_KEY = 0x54;
1211 #endif
1212 #endif
1213
1214 #ifdef CONFIG_SMP
1215 ppc_md.smp_ops = &prep_smp_ops;
1216 #endif /* CONFIG_SMP */
1217 }
1218