1 #include <linux/stddef.h>
2 #include <linux/init.h>
3 #include <linux/irq.h>
4 #include <linux/ioport.h>
5 #include <linux/sched.h>
6 #include <linux/signal.h>
7 #include <asm/io.h>
8 #include <asm/i8259.h>
9
10 static volatile unsigned char *pci_intack; /* RO, gives us the irq vector */
11
12 unsigned char cached_8259[2] = { 0xff, 0xff };
13 #define cached_A1 (cached_8259[0])
14 #define cached_21 (cached_8259[1])
15
16 static spinlock_t i8259_lock = SPIN_LOCK_UNLOCKED;
17
18 int i8259_pic_irq_offset;
19
20 /*
21 * Acknowledge the IRQ using either the PCI host bridge's interrupt
22 * acknowledge feature or poll. How i8259_init() is called determines
23 * which is called. It should be noted that polling is broken on some
24 * IBM and Motorola PReP boxes so we must use the int-ack feature on them.
25 */
26 int
i8259_irq(struct pt_regs * regs)27 i8259_irq(struct pt_regs *regs)
28 {
29 int irq;
30
31 spin_lock(&i8259_lock);
32
33 /* Either int-ack or poll for the IRQ */
34 if (pci_intack)
35 irq = *pci_intack;
36 else {
37 /* Perform an interrupt acknowledge cycle on controller 1. */
38 outb(0x0C, 0x20); /* prepare for poll */
39 irq = inb(0x20) & 7;
40 if (irq == 2 ) {
41 /*
42 * Interrupt is cascaded so perform interrupt
43 * acknowledge on controller 2.
44 */
45 outb(0x0C, 0xA0); /* prepare for poll */
46 irq = (inb(0xA0) & 7) + 8;
47 }
48 }
49
50 if (irq == 7) {
51 /*
52 * This may be a spurious interrupt.
53 *
54 * Read the interrupt status register (ISR). If the most
55 * significant bit is not set then there is no valid
56 * interrupt.
57 */
58 if (!pci_intack)
59 outb(0x0B, 0x20); /* ISR register */
60 if(~inb(0x20) & 0x80)
61 irq = -1;
62 }
63
64 spin_unlock(&i8259_lock);
65 return irq;
66 }
67
i8259_mask_and_ack_irq(unsigned int irq_nr)68 static void i8259_mask_and_ack_irq(unsigned int irq_nr)
69 {
70 unsigned long flags;
71
72 spin_lock_irqsave(&i8259_lock, flags);
73 if ( irq_nr >= i8259_pic_irq_offset )
74 irq_nr -= i8259_pic_irq_offset;
75
76 if (irq_nr > 7) {
77 cached_A1 |= 1 << (irq_nr-8);
78 inb(0xA1); /* DUMMY */
79 outb(cached_A1,0xA1);
80 outb(0x20,0xA0); /* Non-specific EOI */
81 outb(0x20,0x20); /* Non-specific EOI to cascade */
82 } else {
83 cached_21 |= 1 << irq_nr;
84 inb(0x21); /* DUMMY */
85 outb(cached_21,0x21);
86 outb(0x20,0x20); /* Non-specific EOI */
87 }
88 spin_unlock_irqrestore(&i8259_lock, flags);
89 }
90
i8259_set_irq_mask(int irq_nr)91 static void i8259_set_irq_mask(int irq_nr)
92 {
93 outb(cached_A1,0xA1);
94 outb(cached_21,0x21);
95 }
96
i8259_mask_irq(unsigned int irq_nr)97 static void i8259_mask_irq(unsigned int irq_nr)
98 {
99 unsigned long flags;
100
101 spin_lock_irqsave(&i8259_lock, flags);
102 if ( irq_nr >= i8259_pic_irq_offset )
103 irq_nr -= i8259_pic_irq_offset;
104 if ( irq_nr < 8 )
105 cached_21 |= 1 << irq_nr;
106 else
107 cached_A1 |= 1 << (irq_nr-8);
108 i8259_set_irq_mask(irq_nr);
109 spin_unlock_irqrestore(&i8259_lock, flags);
110 }
111
i8259_unmask_irq(unsigned int irq_nr)112 static void i8259_unmask_irq(unsigned int irq_nr)
113 {
114 unsigned long flags;
115
116 spin_lock_irqsave(&i8259_lock, flags);
117 if ( irq_nr >= i8259_pic_irq_offset )
118 irq_nr -= i8259_pic_irq_offset;
119 if ( irq_nr < 8 )
120 cached_21 &= ~(1 << irq_nr);
121 else
122 cached_A1 &= ~(1 << (irq_nr-8));
123 i8259_set_irq_mask(irq_nr);
124 spin_unlock_irqrestore(&i8259_lock, flags);
125 }
126
i8259_end_irq(unsigned int irq)127 static void i8259_end_irq(unsigned int irq)
128 {
129 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
130 i8259_unmask_irq(irq);
131 }
132
133 struct hw_interrupt_type i8259_pic = {
134 " i8259 ",
135 NULL,
136 NULL,
137 i8259_unmask_irq,
138 i8259_mask_irq,
139 i8259_mask_and_ack_irq,
140 i8259_end_irq,
141 NULL
142 };
143
144 #if 0 /* Do not request these before the host bridge resource have been setup */
145 static struct resource pic1_iores = {
146 "8259 (master)", 0x20, 0x21, IORESOURCE_BUSY
147 };
148
149 static struct resource pic2_iores = {
150 "8259 (slave)", 0xa0, 0xa1, IORESOURCE_BUSY
151 };
152
153 static struct resource pic_edgectrl_iores = {
154 "8259 edge control", 0x4d0, 0x4d1, IORESOURCE_BUSY
155 };
156 #endif
157
i8259_init(unsigned long intack_addr)158 void __init i8259_init(unsigned long intack_addr)
159 {
160 unsigned long flags;
161
162 spin_lock_irqsave(&i8259_lock, flags);
163 /* init master interrupt controller */
164 outb(0x11, 0x20); /* Start init sequence */
165 outb(0x00, 0x21); /* Vector base */
166 outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */
167 outb(0x01, 0x21); /* Select 8086 mode */
168
169 /* init slave interrupt controller */
170 outb(0x11, 0xA0); /* Start init sequence */
171 outb(0x08, 0xA1); /* Vector base */
172 outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */
173 outb(0x01, 0xA1); /* Select 8086 mode */
174
175 /* always read ISR */
176 outb(0x0B, 0x20);
177 outb(0x0B, 0xA0);
178
179 /* Mask all interrupts */
180 outb(cached_A1, 0xA1);
181 outb(cached_21, 0x21);
182
183 spin_unlock_irqrestore(&i8259_lock, flags);
184
185 /* reserve our resources */
186 request_irq( i8259_pic_irq_offset + 2, no_action, SA_INTERRUPT,
187 "82c59 secondary cascade", NULL );
188 #if 0 /* Do not request these before the host bridge resource have been setup */
189 request_resource(&ioport_resource, &pic1_iores);
190 request_resource(&ioport_resource, &pic2_iores);
191 request_resource(&ioport_resource, &pic_edgectrl_iores);
192 #endif
193 if (intack_addr)
194 pci_intack = ioremap(intack_addr, 1);
195 }
196