1 /* 2 * arch/ppc/boot/include/mpc10.h 3 * 4 * Common defines for the Motorola SPS MPC106/8240/107 Host bridge/Mem 5 * ctrl/EPIC/etc. 6 * 7 * Author: Tom Rini <trini@mvista.com> 8 * 9 * This is a heavily stripped down version of: 10 * include/asm-ppc/mpc10x.h 11 * 12 * Author: Mark A. Greer 13 * mgreer@mvista.com 14 * 15 * Copyright 2001-2002 MontaVista Software Inc. 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the 19 * Free Software Foundation; either version 2 of the License, or (at your 20 * option) any later version. 21 */ 22 #ifndef __BOOT_MPC10X_H__ 23 #define __BOOT_MPC10X_H__ 24 25 /* 26 * The values here don't completely map everything but should work in most 27 * cases. 28 * 29 * MAP A (PReP Map) 30 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff 31 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff 32 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 33 * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) 34 * 35 * MAP B (CHRP Map) 36 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff 37 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff 38 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 39 * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) 40 */ 41 42 /* Define the type of map to use */ 43 #define MPC10X_MEM_MAP_A 1 44 #define MPC10X_MEM_MAP_B 2 45 46 /* Map A (PReP Map) Defines */ 47 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 48 #define MPC10X_MAPA_CNFG_DATA 0x80000cfc 49 50 /* Map B (CHRP Map) Defines */ 51 #define MPC10X_MAPB_CNFG_ADDR 0xfec00000 52 #define MPC10X_MAPB_CNFG_DATA 0xfee00000 53 54 /* Define offsets for the memory controller registers in the config space */ 55 #define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ 56 #define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ 57 #define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ 58 #define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ 59 60 #define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ 61 #define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */ 62 #define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ 63 #define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ 64 65 #define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 66 67 #endif /* __BOOT_MPC10X_H__ */ 68