1 /*
2 * General Purpose functions for the global management of the
3 * Communication Processor Module.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 *
6 * In addition to the individual control of the communication
7 * channels, there are a few functions that globally affect the
8 * communication processor.
9 *
10 * Buffer descriptors must be allocated from the dual ported memory
11 * space. The allocator for that is here. When the communication
12 * process is reset, we reclaim the memory available. There is
13 * currently no deallocator for this memory.
14 * The amount of space available is platform dependent. On the
15 * MBX, the EPPC software loads additional microcode into the
16 * communication processor, and uses some of the DP ram for this
17 * purpose. Current, the first 512 bytes and the last 256 bytes of
18 * memory are used. Right now I am conservative and only use the
19 * memory that can never be used for microcode. If there are
20 * applications that require more DP ram, we can expand the boundaries
21 * but then we have to be careful of any downloaded microcode.
22 */
23 #include <linux/errno.h>
24 #include <linux/sched.h>
25 #include <linux/kernel.h>
26 #include <linux/param.h>
27 #include <linux/string.h>
28 #include <linux/mm.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <asm/mpc8xx.h>
32 #include <asm/page.h>
33 #include <asm/pgtable.h>
34 #include <asm/8xx_immap.h>
35 #include <asm/commproc.h>
36
37 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep);
38
39 static uint dp_alloc_base; /* Starting offset in DP ram */
40 static uint dp_alloc_top; /* Max offset + 1 */
41 static uint host_buffer; /* One page of host buffer */
42 static uint host_end; /* end + 1 */
43 cpm8xx_t *cpmp; /* Pointer to comm processor space */
44
45 /* CPM interrupt vector functions.
46 *
47 * The cpm_vecs structure is only needed to support the cpm_install_handler()
48 * mechanism of installing CPM interrupt handlers.
49 */
50 struct cpm_action {
51 void (*handler)(void *, struct pt_regs * regs);
52 void *dev_id;
53 };
54 static struct cpm_action cpm_vecs[CPMVEC_NR];
55 static void cpm_interrupt(int irq, void * dev, struct pt_regs * regs);
56 static void cpm_error_interrupt(int irq, void *, struct pt_regs * regs);
57 static void alloc_host_memory(void);
58
59 /* Define a table of names to identify CPM interrupt handlers in
60 * /proc/interrupts.
61 */
62 const char *cpm_int_name[] =
63 { "error", "PC4", "PC5", "SMC2",
64 "SMC1", "SPI", "PC6", "Timer 4",
65 "", "PC7", "PC8", "PC9",
66 "Timer 3", "", "PC10", "PC11",
67 "I2C", "RISC Timer", "Timer 2", "",
68 "IDMA2", "IDMA1", "SDMA error", "PC12",
69 "PC13", "Timer 1", "PC14", "SCC4",
70 "SCC3", "SCC2", "SCC1", "PC15"
71 };
72
73 static void
cpm_mask_irq(unsigned int irq)74 cpm_mask_irq(unsigned int irq)
75 {
76 int cpm_vec = irq - CPM_IRQ_OFFSET;
77
78 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << cpm_vec);
79 }
80
81 static void
cpm_unmask_irq(unsigned int irq)82 cpm_unmask_irq(unsigned int irq)
83 {
84 int cpm_vec = irq - CPM_IRQ_OFFSET;
85
86 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << cpm_vec);
87 }
88
89 static void
cpm_eoi(unsigned int irq)90 cpm_eoi(unsigned int irq)
91 {
92 int cpm_vec = irq - CPM_IRQ_OFFSET;
93
94 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr = (1 << cpm_vec);
95 }
96
97 struct hw_interrupt_type cpm_pic = {
98 " CPM ",
99 NULL,
100 NULL,
101 cpm_unmask_irq,
102 cpm_mask_irq,
103 NULL,
104 cpm_eoi
105 };
106
107 void
m8xx_cpm_reset()108 m8xx_cpm_reset()
109 {
110 volatile immap_t *imp;
111 volatile cpm8xx_t *commproc;
112 pte_t *pte;
113
114 imp = (immap_t *)IMAP_ADDR;
115 commproc = (cpm8xx_t *)&imp->im_cpm;
116
117 #ifdef CONFIG_UCODE_PATCH
118 /* Perform a reset.
119 */
120 commproc->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG);
121
122 /* Wait for it.
123 */
124 while (commproc->cp_cpcr & CPM_CR_FLG);
125
126 cpm_load_patch(imp);
127 #endif
128
129 /* Set SDMA Bus Request priority 5.
130 * On 860T, this also enables FEC priority 6. I am not sure
131 * this is what we realy want for some applications, but the
132 * manual recommends it.
133 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
134 */
135 imp->im_siu_conf.sc_sdcr = 1;
136
137 /* Reclaim the DP memory for our use.
138 */
139 dp_alloc_base = CPM_DATAONLY_BASE;
140 dp_alloc_top = dp_alloc_base + CPM_DATAONLY_SIZE;
141
142 /* Tell everyone where the comm processor resides.
143 */
144 cpmp = (cpm8xx_t *)commproc;
145 }
146
147 /* We used to do this earlier, but have to postpone as long as possible
148 * to ensure the kernel VM is now running.
149 */
150 static void
alloc_host_memory()151 alloc_host_memory()
152 {
153 uint physaddr;
154
155 /* Set the host page for allocation.
156 */
157 host_buffer = (uint)consistent_alloc(GFP_KERNEL, PAGE_SIZE, &physaddr);
158 host_end = host_buffer + PAGE_SIZE;
159 }
160
161 /* This is called during init_IRQ. We used to do it above, but this
162 * was too early since init_IRQ was not yet called.
163 */
164 void
cpm_interrupt_init(void)165 cpm_interrupt_init(void)
166 {
167 int i;
168
169 /* Initialize the CPM interrupt controller.
170 */
171 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr =
172 (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
173 ((CPM_INTERRUPT/2) << 13) | CICR_HP_MASK;
174 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr = 0;
175
176 /* install the CPM interrupt controller routines for the CPM
177 * interrupt vectors
178 */
179 for ( i = CPM_IRQ_OFFSET ; i < CPM_IRQ_OFFSET + NR_CPM_INTS ; i++ )
180 irq_desc[i].handler = &cpm_pic;
181
182 /* Set our interrupt handler with the core CPU.
183 */
184 if (request_irq(CPM_INTERRUPT, cpm_interrupt, 0, "CPM cascade",
185 NULL) != 0)
186 panic("Could not allocate CPM IRQ!");
187
188 /* Install our own error handler.
189 */
190 if (request_irq(CPM_IRQ_OFFSET + CPMVEC_ERROR, cpm_error_interrupt,
191 0, cpm_int_name[CPMVEC_ERROR], NULL) != 0)
192 panic("Could not allocate CPM error IRQ!");
193
194 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN;
195 }
196
197 /*
198 * Get the CPM interrupt vector.
199 */
200 int
cpm_get_irq(struct pt_regs * regs)201 cpm_get_irq(struct pt_regs *regs)
202 {
203 int cpm_vec;
204
205 /* Get the vector by setting the ACK bit and then reading
206 * the register.
207 */
208 ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr = 1;
209 cpm_vec = ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr;
210 cpm_vec >>= 11;
211
212 return cpm_vec;
213 }
214
215 /* CPM interrupt controller cascade interrupt.
216 */
217 static void
cpm_interrupt(int irq,void * dev,struct pt_regs * regs)218 cpm_interrupt(int irq, void * dev, struct pt_regs * regs)
219 {
220 /* This interrupt handler never actually gets called. It is
221 * installed only to unmask the CPM cascade interrupt in the SIU
222 * and to make the CPM cascade interrupt visible in /proc/interrupts.
223 */
224 }
225
226 /* The CPM can generate the error interrupt when there is a race condition
227 * between generating and masking interrupts. All we have to do is ACK it
228 * and return. This is a no-op function so we don't need any special
229 * tests in the interrupt handler.
230 */
231 static void
cpm_error_interrupt(int irq,void * dev,struct pt_regs * regs)232 cpm_error_interrupt(int irq, void *dev, struct pt_regs *regs)
233 {
234 }
235
236 /* A helper function to translate the handler prototype required by
237 * request_irq() to the handler prototype required by cpm_install_handler().
238 */
239 static void
cpm_handler_helper(int irq,void * dev_id,struct pt_regs * regs)240 cpm_handler_helper(int irq, void *dev_id, struct pt_regs *regs)
241 {
242 int cpm_vec = irq - CPM_IRQ_OFFSET;
243
244 (*cpm_vecs[cpm_vec].handler)(dev_id, regs);
245 }
246
247 /* Install a CPM interrupt handler.
248 * This routine accepts a CPM interrupt vector in the range 0 to 31.
249 * This routine is retained for backward compatibility. Rather than using
250 * this routine to install a CPM interrupt handler, you can now use
251 * request_irq() with an IRQ in the range CPM_IRQ_OFFSET to
252 * CPM_IRQ_OFFSET + NR_CPM_INTS - 1 (16 to 47).
253 *
254 * Notice that the prototype of the interrupt handler function must be
255 * different depending on whether you install the handler with
256 * request_irq() or cpm_install_handler().
257 */
258 void
cpm_install_handler(int cpm_vec,void (* handler)(void *,struct pt_regs * regs),void * dev_id)259 cpm_install_handler(int cpm_vec, void (*handler)(void *, struct pt_regs *regs),
260 void *dev_id)
261 {
262 int err;
263
264 /* If null handler, assume we are trying to free the IRQ.
265 */
266 if (!handler) {
267 free_irq(CPM_IRQ_OFFSET + cpm_vec, dev_id);
268 return;
269 }
270
271 if (cpm_vecs[cpm_vec].handler != 0)
272 printk(KERN_INFO "CPM interrupt %x replacing %x\n",
273 (uint)handler, (uint)cpm_vecs[cpm_vec].handler);
274 cpm_vecs[cpm_vec].handler = handler;
275 cpm_vecs[cpm_vec].dev_id = dev_id;
276
277 if ((err = request_irq(CPM_IRQ_OFFSET + cpm_vec, cpm_handler_helper,
278 0, cpm_int_name[cpm_vec], dev_id)))
279 printk(KERN_ERR "request_irq() returned %d for CPM vector %d\n",
280 err, cpm_vec);
281 }
282
283 /* Free a CPM interrupt handler.
284 * This routine accepts a CPM interrupt vector in the range 0 to 31.
285 * This routine is retained for backward compatibility.
286 */
287 void
cpm_free_handler(int cpm_vec)288 cpm_free_handler(int cpm_vec)
289 {
290 request_irq(CPM_IRQ_OFFSET + cpm_vec, NULL, 0, 0,
291 cpm_vecs[cpm_vec].dev_id);
292
293 cpm_vecs[cpm_vec].handler = NULL;
294 cpm_vecs[cpm_vec].dev_id = NULL;
295 }
296
297 /* Allocate some memory from the dual ported ram. We may want to
298 * enforce alignment restrictions, but right now everyone is a good
299 * citizen.
300 */
301 uint
m8xx_cpm_dpalloc(uint size)302 m8xx_cpm_dpalloc(uint size)
303 {
304 uint retloc;
305
306 if ((dp_alloc_base + size) >= dp_alloc_top)
307 return(CPM_DP_NOSPACE);
308
309 retloc = dp_alloc_base;
310 dp_alloc_base += size;
311
312 return(retloc);
313 }
314
315 /* We also own one page of host buffer space for the allocation of
316 * UART "fifos" and the like.
317 */
318 uint
m8xx_cpm_hostalloc(uint size)319 m8xx_cpm_hostalloc(uint size)
320 {
321 uint retloc;
322
323 if (host_buffer == 0)
324 alloc_host_memory();
325
326 if ((host_buffer + size) >= host_end)
327 return(0);
328
329 retloc = host_buffer;
330 host_buffer += size;
331
332 return(retloc);
333 }
334
335 /* Set a baud rate generator. This needs lots of work. There are
336 * four BRGs, any of which can be wired to any channel.
337 * The internal baud rate clock is the system clock divided by 16.
338 * This assumes the baudrate is 16x oversampled by the uart.
339 */
340 #define BRG_INT_CLK (((bd_t *)__res)->bi_intfreq)
341 #define BRG_UART_CLK (BRG_INT_CLK/16)
342 #define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16)
343
344 void
m8xx_cpm_setbrg(uint brg,uint rate)345 m8xx_cpm_setbrg(uint brg, uint rate)
346 {
347 volatile uint *bp;
348
349 /* This is good enough to get SMCs running.....
350 */
351 bp = (uint *)&cpmp->cp_brgc1;
352 bp += brg;
353 /* The BRG has a 12-bit counter. For really slow baud rates (or
354 * really fast processors), we may have to further divide by 16.
355 */
356 if (((BRG_UART_CLK / rate) - 1) < 4096)
357 *bp = (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN;
358 else
359 *bp = (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
360 CPM_BRG_EN | CPM_BRG_DIV16;
361 }
362