1 /* $Id: unaligned.c,v 1.10 2002/09/22 02:21:05 tausq Exp $
2 *
3 * Unaligned memory access handler
4 *
5 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
6 * Significantly tweaked by LaMont Jones <lamont@debian.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24 #include <linux/config.h>
25 #include <linux/sched.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/errno.h>
29 #include <linux/ptrace.h>
30 #include <linux/timer.h>
31 #include <linux/mm.h>
32 #include <linux/smp.h>
33 #include <linux/smp_lock.h>
34 #include <linux/spinlock.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <asm/system.h>
38 #include <asm/uaccess.h>
39 #include <asm/io.h>
40 #include <asm/irq.h>
41 #include <asm/atomic.h>
42
43 #include <asm/smp.h>
44 #include <asm/pdc.h>
45
46 /* #define DEBUG_UNALIGNED 1 */
47
48 #ifdef DEBUG_UNALIGNED
49 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __FUNCTION__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
50 #else
51 #define DPRINTF(fmt, args...)
52 #endif
53
54 #ifdef __LP64__
55 #define RFMT "%016lx"
56 #else
57 #define RFMT "%08lx"
58 #endif
59
60 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
61 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
62 #define OPCODE2(a,b) ((a)<<26|(b)<<1)
63 #define OPCODE3(a,b) ((a)<<26|(b)<<2)
64 #define OPCODE4(a) ((a)<<26)
65 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
66 #define OPCODE2_MASK OPCODE2(0x3f,1)
67 #define OPCODE3_MASK OPCODE3(0x3f,1)
68 #define OPCODE4_MASK OPCODE4(0x3f)
69
70 /* skip LDB - never unaligned (index) */
71 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
72 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
73 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
74 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
75 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
76 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
77 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
78 /* skip LDB - never unaligned (short) */
79 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
80 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
81 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
82 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
83 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
84 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
85 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
86 /* skip STB - never unaligned */
87 #define OPCODE_STH OPCODE1(0x03,1,0x9)
88 #define OPCODE_STW OPCODE1(0x03,1,0xa)
89 #define OPCODE_STD OPCODE1(0x03,1,0xb)
90 /* skip STBY - never unaligned */
91 /* skip STDBY - never unaligned */
92 #define OPCODE_STWA OPCODE1(0x03,1,0xe)
93 #define OPCODE_STDA OPCODE1(0x03,1,0xf)
94
95 #define OPCODE_LDD_L OPCODE2(0x14,0)
96 #define OPCODE_FLDD_L OPCODE2(0x14,1)
97 #define OPCODE_STD_L OPCODE2(0x1c,0)
98 #define OPCODE_FSTD_L OPCODE2(0x1c,1)
99
100 #define OPCODE_LDW_M OPCODE3(0x17,1)
101 #define OPCODE_FLDW_L OPCODE3(0x17,0)
102 #define OPCODE_FSTW_L OPCODE3(0x1f,0)
103 #define OPCODE_STW_M OPCODE3(0x1f,1)
104
105 #define OPCODE_LDH_L OPCODE4(0x11)
106 #define OPCODE_LDW_L OPCODE4(0x12)
107 #define OPCODE_LDWM OPCODE4(0x13)
108 #define OPCODE_STH_L OPCODE4(0x19)
109 #define OPCODE_STW_L OPCODE4(0x1A)
110 #define OPCODE_STWM OPCODE4(0x1B)
111
112 #define MAJOR_OP(i) (((i)>>26)&0x3f)
113 #define R1(i) (((i)>>21)&0x1f)
114 #define R2(i) (((i)>>16)&0x1f)
115 #define R3(i) ((i)&0x1f)
116 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
117 #define IM5_2(i) IM((i)>>16,5)
118 #define IM5_3(i) IM((i),5)
119 #define IM14(i) IM((i),14)
120
121 int unaligned_enabled = 1;
122
123 void die_if_kernel (char *str, struct pt_regs *regs, long err);
124
emulate_ldh(struct pt_regs * regs,int toreg)125 static int emulate_ldh(struct pt_regs *regs, int toreg)
126 {
127 unsigned long saddr = regs->ior;
128 unsigned long val = 0;
129
130 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
131 regs->isr, regs->ior, toreg);
132
133 __asm__ __volatile__ (
134 " mtsp %3, %%sr1\n"
135 " ldbs 0(%%sr1,%2), %%r20\n"
136 " ldbs 1(%%sr1,%2), %0\n"
137 "depw %%r20, 23, 24, %0\n"
138 : "=r" (val)
139 : "0" (val), "r" (saddr), "r" (regs->isr)
140 : "r20" );
141
142 DPRINTF("val = 0x" RFMT "\n", val);
143
144 if (toreg)
145 regs->gr[toreg] = val;
146
147 return 0;
148 }
emulate_ldw(struct pt_regs * regs,int toreg)149 static int emulate_ldw(struct pt_regs *regs, int toreg)
150 {
151 unsigned long saddr = regs->ior;
152 unsigned long val = 0;
153
154 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
155 regs->isr, regs->ior, toreg);
156
157 __asm__ __volatile__ (
158 " zdep %2,28,2,%%r19\n" /* r19=(ofs&3)*8 */
159 " mtsp %3, %%sr1\n"
160 " depw %%r0,31,2,%2\n"
161 " ldw 0(%%sr1,%2),%0\n"
162 " ldw 4(%%sr1,%2),%%r20\n"
163 " subi 32,%%r19,%%r19\n"
164 " mtctl %%r19,11\n"
165 " vshd %0,%%r20,%0\n"
166 : "=r" (val)
167 : "0" (val), "r" (saddr), "r" (regs->isr)
168 : "r19", "r20" );
169
170 DPRINTF("val = 0x" RFMT "\n", val);
171
172 if (toreg)
173 regs->gr[toreg] = val;
174
175 return 0;
176 }
177 #ifdef __LP64__
emulate_ldd(struct pt_regs * regs,int toreg)178 static int emulate_ldd(struct pt_regs *regs, int toreg)
179 {
180 unsigned long saddr = regs->ior;
181 unsigned long val = 0;
182
183 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
184 regs->isr, regs->ior, toreg);
185
186 __asm__ __volatile__ (
187 " depd,z %2,60,3,%%r19\n" /* r19=(ofs&7)*8 */
188 " mtsp %3, %%sr1\n"
189 " depd %%r0,63,3,%2\n"
190 " ldd 0(%%sr1,%2),%0\n"
191 " ldd 8(%%sr1,%2),%%r20\n"
192 " subi 64,%%r19,%%r19\n"
193 " mtsar %%r19\n"
194 " shrpd %0,%%r20,%%sar,%0\n"
195 : "=r" (val)
196 : "0" (val), "r" (saddr), "r" (regs->isr)
197 : "r19", "r20" );
198
199 DPRINTF("val = 0x" RFMT "\n", val);
200
201 if (toreg)
202 regs->gr[toreg] = val;
203
204 return 0;
205 }
206 #endif
207
emulate_sth(struct pt_regs * regs,int frreg)208 static int emulate_sth(struct pt_regs *regs, int frreg)
209 {
210 unsigned long val = regs->gr[frreg];
211 if (!frreg)
212 val = 0;
213
214 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
215 regs->gr[frreg], regs->isr, regs->ior);
216
217 __asm__ __volatile__ (
218 " mtsp %2, %%sr1\n"
219 " extrw,u %0, 23, 8, %%r19\n"
220 " stb %0, 1(%%sr1, %1)\n"
221 " stb %%r19, 0(%%sr1, %1)\n"
222 :
223 : "r" (val), "r" (regs->ior), "r" (regs->isr)
224 : "r19" );
225
226 return 0;
227 }
emulate_stw(struct pt_regs * regs,int frreg)228 static int emulate_stw(struct pt_regs *regs, int frreg)
229 {
230 unsigned long val = regs->gr[frreg];
231 if (!frreg)
232 val = 0;
233
234 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
235 regs->gr[frreg], regs->isr, regs->ior);
236
237
238 __asm__ __volatile__ (
239 " mtsp %2, %%sr1\n"
240 " zdep %1, 28, 2, %%r19\n"
241 " dep %%r0, 31, 2, %1\n"
242 " mtsar %%r19\n"
243 " depwi,z -2, %%sar, 32, %%r19\n"
244 " ldw 0(%%sr1,%1),%%r20\n"
245 " ldw 4(%%sr1,%1),%%r21\n"
246 " vshd %%r0, %0, %%r22\n"
247 " vshd %0, %%r0, %%r1\n"
248 " and %%r20, %%r19, %%r20\n"
249 " andcm %%r21, %%r19, %%r21\n"
250 " or %%r22, %%r20, %%r20\n"
251 " or %%r1, %%r21, %%r21\n"
252 " stw %%r20,0(%%sr1,%1)\n"
253 " stw %%r21,4(%%sr1,%1)\n"
254 :
255 : "r" (val), "r" (regs->ior), "r" (regs->isr)
256 : "r19", "r20", "r21", "r22", "r1" );
257
258 return 0;
259 }
260 #ifdef __LP64__
emulate_std(struct pt_regs * regs,int frreg)261 static int emulate_std(struct pt_regs *regs, int frreg)
262 {
263 unsigned long val = regs->gr[frreg];
264 if (!frreg)
265 val = 0;
266
267 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 8 bytes\n", frreg,
268 regs->gr[frreg], regs->isr, regs->ior);
269
270
271 __asm__ __volatile__ (
272 " mtsp %2, %%sr1\n"
273 " depd,z %1, 60, 3, %%r19\n"
274 " depd %%r0, 63, 3, %1\n"
275 " mtsar %%r19\n"
276 " depdi,z -2, %%sar, 64, %%r19\n"
277 " ldd 0(%%sr1,%1),%%r20\n"
278 " ldd 8(%%sr1,%1),%%r21\n"
279 " shrpd %%r0, %0, %%sar, %%r22\n"
280 " shrpd %0, %%r0, %%sar, %%r1\n"
281 " and %%r20, %%r19, %%r20\n"
282 " andcm %%r21, %%r19, %%r21\n"
283 " or %%r22, %%r20, %%r20\n"
284 " or %%r1, %%r21, %%r21\n"
285 " std %%r20,0(%%sr1,%1)\n"
286 " std %%r21,8(%%sr1,%1)\n"
287 :
288 : "r" (val), "r" (regs->ior), "r" (regs->isr)
289 : "r19", "r20", "r21", "r22", "r1" );
290
291 return 0;
292 }
293 #endif
294
handle_unaligned(struct pt_regs * regs)295 void handle_unaligned(struct pt_regs *regs)
296 {
297 unsigned long unaligned_count = 0;
298 unsigned long last_time = 0;
299 unsigned long newbase = regs->gr[R1(regs->iir)];
300 int modify = 0;
301 int ret = -1;
302 struct siginfo si;
303
304 /* if the unaligned access is inside the kernel:
305 * if the access is caused by a syscall, then we fault the calling
306 * user process
307 * otherwise we halt the kernel
308 */
309 if (!user_mode(regs))
310 {
311 const struct exception_table_entry *fix;
312
313 /* see if the offending code have its own
314 * exception handler
315 */
316
317 fix = search_exception_table(regs->iaoq[0]);
318 if (fix)
319 {
320 /* lower bits of fix->skip are flags
321 * upper bits are the handler addr
322 */
323 if (fix->skip & 1)
324 regs->gr[8] = -EFAULT;
325 if (fix->skip & 2)
326 regs->gr[9] = 0;
327
328 regs->iaoq[0] += ((fix->skip) & ~3);
329 regs->iaoq[1] = regs->iaoq[0] + 4;
330 regs->gr[0] &= ~PSW_B;
331
332 return;
333 }
334 }
335
336 /* log a message with pacing */
337 if (user_mode(regs))
338 {
339 if (unaligned_count > 5 && jiffies - last_time > 5*HZ)
340 {
341 unaligned_count = 0;
342 last_time = jiffies;
343 }
344 if (++unaligned_count < 5)
345 {
346 char buf[256];
347 sprintf(buf, "%s(%d): unaligned access to 0x" RFMT " at ip=0x" RFMT "\n",
348 current->comm, current->pid, regs->ior, regs->iaoq[0]);
349 printk(KERN_WARNING "%s", buf);
350 #ifdef DEBUG_UNALIGNED
351 show_regs(regs);
352 #endif
353 }
354 }
355
356 if (!unaligned_enabled)
357 goto force_sigbus;
358
359 /* handle modification - OK, it's ugly, see the instruction manual */
360 switch (MAJOR_OP(regs->iir))
361 {
362 case 0x03:
363 case 0x09:
364 case 0x0b:
365 if (regs->iir&0x20)
366 {
367 modify = 1;
368 if (regs->iir&0x1000) /* short loads */
369 if (regs->iir&0x200)
370 newbase += IM5_3(regs->iir);
371 else
372 newbase += IM5_2(regs->iir);
373 else if (regs->iir&0x2000) /* scaled indexed */
374 {
375 int shift=0;
376 switch (regs->iir & OPCODE1_MASK)
377 {
378 case OPCODE_LDH_I:
379 shift= 1; break;
380 case OPCODE_LDW_I:
381 shift= 2; break;
382 case OPCODE_LDD_I:
383 case OPCODE_LDDA_I:
384 shift= 3; break;
385 }
386 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
387 } else /* simple indexed */
388 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
389 }
390 break;
391 case 0x13:
392 case 0x1b:
393 modify = 1;
394 newbase += IM14(regs->iir);
395 break;
396 case 0x14:
397 case 0x1c:
398 if (regs->iir&8)
399 {
400 modify = 1;
401 newbase += IM14(regs->iir&~0xe);
402 }
403 break;
404 case 0x16:
405 case 0x1e:
406 modify = 1;
407 newbase += IM14(regs->iir&6);
408 break;
409 case 0x17:
410 case 0x1f:
411 if (regs->iir&4)
412 {
413 modify = 1;
414 newbase += IM14(regs->iir&~4);
415 }
416 break;
417 }
418
419 if (regs->isr != regs->sr[7])
420 {
421 printk(KERN_CRIT "isr verification failed (isr: " RFMT ", sr7: " RFMT "\n",
422 regs->isr, regs->sr[7]);
423
424 /* don't kill him though, since he has appropriate access to the page, or we
425 * would never have gotten here.
426 */
427 }
428
429 /* TODO: make this cleaner... */
430 switch (regs->iir & OPCODE1_MASK)
431 {
432 case OPCODE_LDH_I:
433 case OPCODE_LDH_S:
434 ret = emulate_ldh(regs, R3(regs->iir));
435 break;
436
437 case OPCODE_LDW_I:
438 case OPCODE_LDWA_I:
439 case OPCODE_LDW_S:
440 case OPCODE_LDWA_S:
441 ret = emulate_ldw(regs, R3(regs->iir));
442 break;
443
444 case OPCODE_STH:
445 ret = emulate_sth(regs, R2(regs->iir));
446 break;
447
448 case OPCODE_STW:
449 case OPCODE_STWA:
450 ret = emulate_stw(regs, R2(regs->iir));
451 break;
452
453 #ifdef __LP64__
454 case OPCODE_LDD_I:
455 case OPCODE_LDDA_I:
456 case OPCODE_LDD_S:
457 case OPCODE_LDDA_S:
458 ret = emulate_ldd(regs, R3(regs->iir));
459 break;
460
461 case OPCODE_STD:
462 case OPCODE_STDA:
463 ret = emulate_std(regs, R2(regs->iir));
464 break;
465 #endif
466
467 case OPCODE_LDCD_I:
468 case OPCODE_LDCW_I:
469 case OPCODE_LDCD_S:
470 case OPCODE_LDCW_S:
471 ret = -1; /* "undefined", but lets kill them. */
472 break;
473 }
474 #ifdef __LP64__
475 switch (regs->iir & OPCODE2_MASK)
476 {
477 case OPCODE_LDD_L:
478 case OPCODE_FLDD_L:
479 ret = emulate_ldd(regs, R2(regs->iir));
480 break;
481
482 case OPCODE_STD_L:
483 case OPCODE_FSTD_L:
484 ret = emulate_std(regs, R2(regs->iir));
485 break;
486 }
487 #endif
488 switch (regs->iir & OPCODE3_MASK)
489 {
490 case OPCODE_LDW_M:
491 case OPCODE_FLDW_L:
492 ret = emulate_ldw(regs, R2(regs->iir));
493 break;
494
495 case OPCODE_FSTW_L:
496 case OPCODE_STW_M:
497 ret = emulate_stw(regs, R2(regs->iir));
498 break;
499 }
500 switch (regs->iir & OPCODE4_MASK)
501 {
502 case OPCODE_LDH_L:
503 ret = emulate_ldh(regs, R2(regs->iir));
504 break;
505 case OPCODE_LDW_L:
506 case OPCODE_LDWM:
507 ret = emulate_ldw(regs, R2(regs->iir));
508 break;
509 case OPCODE_STH_L:
510 ret = emulate_sth(regs, R2(regs->iir));
511 break;
512 case OPCODE_STW_L:
513 case OPCODE_STWM:
514 ret = emulate_stw(regs, R2(regs->iir));
515 break;
516 }
517 /* XXX LJ - need to handle float load/store */
518
519 if (modify && R1(regs->iir))
520 regs->gr[R1(regs->iir)] = newbase;
521
522
523 if (ret < 0)
524 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
525
526 DPRINTF("ret = %d\n", ret);
527
528 if (ret)
529 {
530 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
531 die_if_kernel("Unaligned data reference", regs, 28);
532 force_sigbus:
533 /* couldn't handle it ... */
534 si.si_signo = SIGBUS;
535 si.si_errno = 0;
536 si.si_code = BUS_ADRALN;
537 si.si_addr = (void *)regs->ior;
538 force_sig_info(SIGBUS, &si, current);
539
540 return;
541 }
542
543 /* else we handled it, advance the PC.... */
544 regs->iaoq[0] = regs->iaoq[1];
545 regs->iaoq[1] = regs->iaoq[0] + 4;
546 }
547
548 /*
549 * NB: check_unaligned() is only used for PCXS processors right
550 * now, so we only check for PA1.1 encodings at this point.
551 */
552
553 int
check_unaligned(struct pt_regs * regs)554 check_unaligned(struct pt_regs *regs)
555 {
556 unsigned long align_mask;
557
558 /* Get alignment mask */
559
560 align_mask = 0UL;
561 switch (regs->iir & OPCODE1_MASK) {
562
563 case OPCODE_LDH_I:
564 case OPCODE_LDH_S:
565 case OPCODE_STH:
566 align_mask = 1UL;
567 break;
568
569 case OPCODE_LDW_I:
570 case OPCODE_LDWA_I:
571 case OPCODE_LDW_S:
572 case OPCODE_LDWA_S:
573 case OPCODE_STW:
574 case OPCODE_STWA:
575 align_mask = 3UL;
576 break;
577
578 default:
579 switch (regs->iir & OPCODE4_MASK) {
580 case OPCODE_LDH_L:
581 case OPCODE_STH_L:
582 align_mask = 1UL;
583 break;
584 case OPCODE_LDW_L:
585 case OPCODE_LDWM:
586 case OPCODE_STW_L:
587 case OPCODE_STWM:
588 align_mask = 3UL;
589 break;
590 }
591 break;
592 }
593
594 return (int)(regs->ior & align_mask);
595 }
596
597