1 /* 2 ** This file is private to iosapic driver. 3 ** If stuff needs to be used by another driver, move it to a common file. 4 ** 5 ** WARNING: fields most data structures here are ordered to make sure 6 ** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8) 7 */ 8 9 10 /* 11 ** Interrupt Routing Stuff 12 ** ----------------------- 13 ** The interrupt routing table consists of entries derived from 14 ** MP Specification Draft 1.5. There is one interrupt routing 15 ** table per cell. N- and L-class consist of a single cell. 16 */ 17 struct irt_entry { 18 19 /* Entry Type 139 identifies an I/O SAPIC interrupt entry */ 20 u8 entry_type; 21 22 /* Entry Length 16 indicates entry is 16 bytes long */ 23 u8 entry_length; 24 25 /* 26 ** Interrupt Type of 0 indicates a vectored interrupt, 27 ** all other values are reserved 28 */ 29 u8 interrupt_type; 30 31 /* 32 ** PO and EL 33 ** Polarity of SAPIC I/O input signals: 34 ** 00 = Reserved 35 ** 01 = Active high 36 ** 10 = Reserved 37 ** 11 = Active low 38 ** Trigger mode of SAPIC I/O input signals: 39 ** 00 = Reserved 40 ** 01 = Edge-triggered 41 ** 10 = Reserved 42 ** 11 = Level-triggered 43 */ 44 u8 polarity_trigger; 45 46 /* 47 ** IRQ and DEVNO 48 ** irq identifies PCI interrupt signal where 49 ** 0x0 corresponds to INT_A#, 50 ** 0x1 corresponds to INT_B#, 51 ** 0x2 corresponds to INT_C# 52 ** 0x3 corresponds to INT_D# 53 ** PCI device number where interrupt originates 54 */ 55 u8 src_bus_irq_devno; 56 57 /* Source Bus ID identifies the bus where interrupt signal comes from */ 58 u8 src_bus_id; 59 60 /* 61 ** Segment ID is unique across a protection domain and 62 ** identifies a segment of PCI buses (reserved in 63 ** MP Specification Draft 1.5) 64 */ 65 u8 src_seg_id; 66 67 /* 68 ** Destination I/O SAPIC INTIN# identifies the INTIN n pin 69 ** to which the signal is connected 70 */ 71 u8 dest_iosapic_intin; 72 73 /* 74 ** Destination I/O SAPIC Address identifies the I/O SAPIC 75 ** to which the signal is connected 76 */ 77 u64 dest_iosapic_addr; 78 }; 79 80 #define IRT_IOSAPIC_TYPE 139 81 #define IRT_IOSAPIC_LENGTH 16 82 83 #define IRT_VECTORED_INTR 0 84 85 #define IRT_PO_MASK 0x3 86 #define IRT_ACTIVE_HI 1 87 #define IRT_ACTIVE_LO 3 88 89 #define IRT_EL_MASK 0x3 90 #define IRT_EL_SHIFT 2 91 #define IRT_EDGE_TRIG 1 92 #define IRT_LEVEL_TRIG 3 93 94 #define IRT_IRQ_MASK 0x3 95 #define IRT_DEV_MASK 0x1f 96 #define IRT_DEV_SHIFT 2 97 98 #define IRT_IRQ_DEVNO_MASK ((IRT_DEV_MASK << IRT_DEV_SHIFT) | IRT_IRQ_MASK) 99 100 #ifdef SUPPORT_MULTI_CELL 101 struct iosapic_irt { 102 struct iosapic_irt *irt_next; /* next routing table */ 103 struct irt_entry *irt_base; /* intr routing table address */ 104 size_t irte_count; /* number of entries in the table */ 105 size_t irte_size; /* size (bytes) of each entry */ 106 }; 107 #endif 108 109 struct vector_info { 110 struct iosapic_info *vi_ios; /* I/O SAPIC this vector is on */ 111 struct irt_entry *vi_irte; /* IRT entry */ 112 u32 *vi_eoi_addr; /* precalculate EOI reg address */ 113 u32 vi_eoi_data; /* IA64: ? PA: swapped txn_data */ 114 int vi_txn_irq; /* virtual IRQ number for processor */ 115 ulong vi_txn_addr; /* IA64: id_eid PA: partial HPA */ 116 ulong vi_txn_data; /* IA64: vector PA: EIR bit */ 117 u8 vi_status; /* status/flags */ 118 u8 vi_irqline; /* INTINn(IRQ) */ 119 char vi_name[32]; /* user visible identity */ 120 }; 121 122 123 struct iosapic_info { 124 struct iosapic_info *isi_next; /* list of I/O SAPIC */ 125 unsigned long isi_hpa; /* physical base address */ 126 struct irq_region *isi_region; /* each I/O SAPIC is one region */ 127 struct vector_info *isi_vector; /* IRdT (IRQ line) array */ 128 int isi_num_vectors; /* size of IRdT array */ 129 int isi_status; /* status/flags */ 130 unsigned int isi_version; /* DEBUG: data fr version reg */ 131 /* round up to next cacheline */ 132 char isi_name[20]; /* identify region for users */ 133 }; 134 135 136 137 #ifdef __IA64__ 138 /* 139 ** PA risc does NOT have any local sapics. IA64 does. 140 ** PIB (Processor Interrupt Block) is handled by Astro or Dew (Stretch CEC). 141 ** 142 ** PA: Get id_eid from IRT and hardcode PIB to 0xfeeNNNN0 143 ** Emulate the data on PAT platforms. 144 */ 145 struct local_sapic_info { 146 struct local_sapic_info *lsi_next; /* point to next CPU info */ 147 int *lsi_cpu_id; /* point to logical CPU id */ 148 unsigned long *lsi_id_eid; /* point to IA-64 CPU id */ 149 int *lsi_status; /* point to CPU status */ 150 void *lsi_private; /* point to special info */ 151 }; 152 153 /* 154 ** "root" data structure which ties everything together. 155 ** Should always be able to start with sapic_root and locate 156 ** the desired information. 157 */ 158 struct sapic_info { 159 struct sapic_info *si_next; /* info is per cell */ 160 int si_cellid; /* cell id */ 161 unsigned int si_status; /* status */ 162 char *si_pib_base; /* intr blk base address */ 163 local_sapic_info_t *si_local_info; 164 io_sapic_info_t *si_io_info; 165 extint_info_t *si_extint_info;/* External Intr info */ 166 }; 167 #endif 168 169