1 /* $Id: cache.c,v 1.4 2000/01/25 00:11:38 prumpf Exp $
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 1999 Helge Deller (07-13-1999)
8 * Copyright (C) 1999 SuSE GmbH Nuernberg
9 * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
10 *
11 * Cache and TLB management
12 *
13 */
14
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/mm.h>
18 #include <linux/seq_file.h>
19
20 #include <asm/pdc.h>
21 #include <asm/cache.h>
22 #include <asm/system.h>
23 #include <asm/page.h>
24 #include <asm/pgalloc.h>
25 #include <asm/processor.h>
26
27 int split_tlb;
28 int dcache_stride;
29 int icache_stride;
30
31 struct pdc_cache_info cache_info;
32 #ifndef CONFIG_PA20
33 static struct pdc_btlb_info btlb_info;
34 #endif
35
36 #ifdef CONFIG_SMP
37 void
flush_data_cache(void)38 flush_data_cache(void)
39 {
40 smp_call_function((void (*)(void *))flush_data_cache_local, NULL, 1, 1);
41 flush_data_cache_local();
42 }
43 #endif
44
45 void
flush_cache_all_local(void)46 flush_cache_all_local(void)
47 {
48 flush_instruction_cache_local();
49 flush_data_cache_local();
50 }
51
52 /* flushes EVERYTHING (tlb & cache) */
53
54 void
flush_all_caches(void)55 flush_all_caches(void)
56 {
57 flush_cache_all();
58 flush_tlb_all();
59 }
60
61 void
update_mmu_cache(struct vm_area_struct * vma,unsigned long address,pte_t pte)62 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
63 {
64 struct page *page = pte_page(pte);
65
66 if (VALID_PAGE(page) && page->mapping &&
67 test_bit(PG_dcache_dirty, &page->flags)) {
68
69 flush_kernel_dcache_page(page_address(page));
70 clear_bit(PG_dcache_dirty, &page->flags);
71 }
72 }
73
74 void
show_cache_info(struct seq_file * m)75 show_cache_info(struct seq_file *m)
76 {
77 seq_printf(m, "I-cache\t\t: %ld KB\n",
78 cache_info.ic_size/1024 );
79 seq_printf(m, "D-cache\t\t: %ld KB (%s)%s\n",
80 cache_info.dc_size/1024,
81 (cache_info.dc_conf.cc_wt ? "WT":"WB"),
82 (cache_info.dc_conf.cc_sh ? " - shared I/D":"")
83 );
84
85 seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
86 cache_info.it_size,
87 cache_info.dt_size,
88 cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
89 );
90
91 #ifndef CONFIG_PA20
92 /* BTLB - Block TLB */
93 if (btlb_info.max_size==0) {
94 seq_printf(m, "BTLB\t\t: not supported\n" );
95 } else {
96 seq_printf(m,
97 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
98 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
99 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
100 btlb_info.max_size, (int)4096,
101 btlb_info.max_size>>8,
102 btlb_info.fixed_range_info.num_i,
103 btlb_info.fixed_range_info.num_d,
104 btlb_info.fixed_range_info.num_comb,
105 btlb_info.variable_range_info.num_i,
106 btlb_info.variable_range_info.num_d,
107 btlb_info.variable_range_info.num_comb
108 );
109 }
110 #endif
111 }
112
113 void __init
cache_init(void)114 cache_init(void)
115 {
116 if(pdc_cache_info(&cache_info)<0)
117 panic("cache_init: pdc_cache_info failed");
118
119 #if 0
120 printk(KERN_DEBUG "ic_size %lx dc_size %lx it_size %lx pdc_cache_info %d*long pdc_cache_cf %d\n",
121 cache_info.ic_size,
122 cache_info.dc_size,
123 cache_info.it_size,
124 sizeof (struct pdc_cache_info) / sizeof (long),
125 sizeof (struct pdc_cache_cf)
126 );
127
128 printk(KERN_DEBUG "dc base %x dc stride %x dc count %x dc loop %d\n",
129 cache_info.dc_base,
130 cache_info.dc_stride,
131 cache_info.dc_count,
132 cache_info.dc_loop);
133
134 printk(KERN_DEBUG "dc conf: alias %d block %d line %d wt %d sh %d cst %d assoc %d\n",
135 cache_info.dc_conf.cc_alias,
136 cache_info.dc_conf.cc_block,
137 cache_info.dc_conf.cc_line,
138 cache_info.dc_conf.cc_wt,
139 cache_info.dc_conf.cc_sh,
140 cache_info.dc_conf.cc_cst,
141 cache_info.dc_conf.cc_assoc);
142
143 printk(KERN_DEBUG "ic conf: alias %d block %d line %d wt %d sh %d cst %d assoc %d\n",
144 cache_info.ic_conf.cc_alias,
145 cache_info.ic_conf.cc_block,
146 cache_info.ic_conf.cc_line,
147 cache_info.ic_conf.cc_wt,
148 cache_info.ic_conf.cc_sh,
149 cache_info.ic_conf.cc_cst,
150 cache_info.ic_conf.cc_assoc);
151
152 printk(KERN_DEBUG "dt conf: sh %d page %d cst %d aid %d pad1 %d \n",
153 cache_info.dt_conf.tc_sh,
154 cache_info.dt_conf.tc_page,
155 cache_info.dt_conf.tc_cst,
156 cache_info.dt_conf.tc_aid,
157 cache_info.dt_conf.tc_pad1);
158
159 printk(KERN_DEBUG "it conf: sh %d page %d cst %d aid %d pad1 %d \n",
160 cache_info.it_conf.tc_sh,
161 cache_info.it_conf.tc_page,
162 cache_info.it_conf.tc_cst,
163 cache_info.it_conf.tc_aid,
164 cache_info.it_conf.tc_pad1);
165 #endif
166
167 split_tlb = 0;
168 if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
169
170 if (cache_info.dt_conf.tc_sh == 2)
171 printk(KERN_WARNING "Unexpected TLB configuration. "
172 "Will flush I/D separately (could be optimized).\n");
173
174 split_tlb = 1;
175 }
176
177 dcache_stride = ( (1<<(cache_info.dc_conf.cc_block+3)) *
178 cache_info.dc_conf.cc_line );
179 icache_stride = ( (1<<(cache_info.ic_conf.cc_block+3)) *
180 cache_info.ic_conf.cc_line );
181 #ifndef CONFIG_PA20
182 if(pdc_btlb_info(&btlb_info)<0) {
183 memset(&btlb_info, 0, sizeof btlb_info);
184 }
185 #endif
186
187 if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) == PDC_MODEL_NVA_UNSUPPORTED) {
188 printk(KERN_WARNING "Only equivalent aliasing supported\n");
189 #ifndef CONFIG_SMP
190 panic("SMP kernel required to avoid non-equivalent aliasing");
191 #endif
192 }
193 }
194
disable_sr_hashing(void)195 void disable_sr_hashing(void)
196 {
197 int srhash_type;
198
199 switch (boot_cpu_data.cpu_type) {
200 case pcx: /* We shouldn't get this far. setup.c should prevent it. */
201 BUG();
202 return;
203
204 case pcxs:
205 case pcxt:
206 case pcxt_:
207 srhash_type = SRHASH_PCXST;
208 break;
209
210 case pcxl:
211 srhash_type = SRHASH_PCXL;
212 break;
213
214 case pcxl2: /* pcxl2 doesn't support space register hashing */
215 return;
216
217 default: /* Currently all PA2.0 machines use the same ins. sequence */
218 srhash_type = SRHASH_PA20;
219 break;
220 }
221
222 disable_sr_hashing_asm(srhash_type);
223 }
224
__flush_dcache_page(struct page * page)225 void __flush_dcache_page(struct page *page)
226 {
227 struct mm_struct *mm = current->active_mm;
228 struct vm_area_struct *mpnt;
229
230 flush_kernel_dcache_page(page_address(page));
231
232 if (!page->mapping)
233 return;
234
235 for (mpnt = page->mapping->i_mmap_shared;
236 mpnt != NULL;
237 mpnt = mpnt->vm_next_share)
238 {
239 unsigned long off;
240
241 /*
242 * If this VMA is not in our MM, we can ignore it.
243 */
244 if (mpnt->vm_mm != mm)
245 continue;
246
247 if (page->index < mpnt->vm_pgoff)
248 continue;
249
250 off = page->index - mpnt->vm_pgoff;
251 if (off >= (mpnt->vm_end - mpnt->vm_start) >> PAGE_SHIFT)
252 continue;
253
254 flush_cache_page(mpnt, mpnt->vm_start + (off << PAGE_SHIFT));
255
256 /* All user shared mappings should be equivalently mapped,
257 * so once we've flushed one we should be ok
258 */
259 break;
260 }
261 }
262
263