1/*
2 * Copyright (C) 2001,2002,2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
17 */
18#include <linux/config.h>
19#include <linux/init.h>
20
21#include <asm/asm.h>
22#include <asm/regdef.h>
23#include <asm/mipsregs.h>
24#include <asm/stackframe.h>
25#include <asm/cacheops.h>
26#include <asm/processor.h>
27#include <asm/sibyte/board.h>
28
29#define C0_ERRCTL     $26             /* CP0: Error info */
30#define C0_CERR_I     $27             /* CP0: Icache error */
31#define C0_CERR_D     $27,1           /* CP0: Dcache error */
32
33	/*
34	 * Based on SiByte sample software cache-err/cerr.S
35	 * CVS revision 1.8.  Only the 'unrecoverable' case
36	 * is changed.
37	 */
38
39        __INIT
40
41	.set	mips64
42	.set	noreorder
43	.set	noat
44
45	/*
46	 * sb1_cerr_vec: code to be copied to the Cache Error
47	 * Exception vector.  The code must be pushed out to memory
48	 * (either by copying to Kseg0 and Kseg1 both, or by flushing
49	 * the L1 and L2) since it is fetched as 0xa0000100.
50	 *
51	 * NOTE: Be sure this handler is at most 28 instructions long
52	 * since the final 16 bytes of the exception vector memory
53	 * (0x170-0x17f) are used to preserve k0, k1, and ra.
54	 */
55
56LEAF(except_vec2_sb1)
57	/*
58	 * If this error is recoverable, we need to exit the handler
59	 * without having dirtied any registers.  To do this,
60	 * save/restore k0 and k1 from low memory (Useg is direct
61	 * mapped while ERL=1). Note that we can't save to a
62	 * CPU-specific location without ruining a register in the
63	 * process.  This means we are vulnerable to data corruption
64	 * whenever the handler is reentered by a second CPU.
65	 */
66	sd	k0,0x170($0)
67	sd	k1,0x178($0)
68
69	/*
70	 * M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell
71	 * if we can fast-path out of here for a h/w-recovered error.
72	 */
73	mfc0	k1,C0_ERRCTL
74	bgtz	k1,attempt_recovery
75	 sll	k0,k1,1
76
77recovered_dcache:
78	/*
79	 * Unlock CacheErr-D (which in turn unlocks CacheErr-DPA).
80	 * Ought to log the occurence of this recovered dcache error.
81	 */
82	b	recovered
83	 .word   0x4080d801		# mtc0  zero, $27, 1
84
85attempt_recovery:
86	/*
87	 * k0 has C0_ERRCTL << 1, which puts 'DC' at bit 31.  Any
88	 * Dcache errors we can recover from will take more extensive
89	 * processing.  For now, they are considered "unrecoverable".
90	 * Note that 'DC' becoming set (outside of ERL mode) will
91	 * cause 'IC' to clear; so if there's an Icache error, we'll
92	 * only find out about it if we recover from this error and
93	 * continue executing.
94	 */
95	bltz	k0,unrecoverable
96	 sll	k0,1
97
98	/*
99	 * k0 has C0_ERRCTL << 2, which puts 'IC' at bit 31.  If an
100	 * Icache error isn't indicated, I'm not sure why we got here.
101	 * Consider that case "unrecoverable" for now.
102	 */
103	bgez	k0,unrecoverable
104
105attempt_icache_recovery:
106	/*
107	 * External icache errors are due to uncorrectable ECC errors
108	 * in the L2 cache or Memory Controller and cannot be
109	 * recovered here.
110	 */
111	 mfc0	k0,C0_CERR_I		/* delay slot */
112	li	k1,1 << 26		/* ICACHE_EXTERNAL */
113	and	k1,k0
114	bnez	k1,unrecoverable
115	 andi	k0,0x1fe0
116
117	/*
118	 * Since the error is internal, the 'IDX' field from
119	 * CacheErr-I is valid and we can just invalidate all blocks
120	 * in that set.
121	 */
122	cache	Index_Invalidate_I,(0<<13)(k0)
123	cache	Index_Invalidate_I,(1<<13)(k0)
124	cache	Index_Invalidate_I,(2<<13)(k0)
125	cache	Index_Invalidate_I,(3<<13)(k0)
126
127	/* Ought to log this recovered icache error */
128
129recovered:
130	/* Restore the saved registers */
131	ld	k0,0x170($0)
132	ld	k1,0x178($0)
133	eret
134
135unrecoverable:
136	/* Unrecoverable Icache or Dcache error; log it and/or fail */
137	j	handle_vec2_sb1
138	 nop
139
140END(except_vec2_sb1)
141
142	__FINIT
143
144	LEAF(handle_vec2_sb1)
145	mfc0	k0,CP0_CONFIG
146	li	k1,~CONF_CM_CMASK
147	and	k0,k0,k1
148	ori	k0,k0,CONF_CM_UNCACHED
149	mtc0	k0,CP0_CONFIG
150
151	SSNOP
152	SSNOP
153	SSNOP
154	SSNOP
155	bnezl	$0, 1f
1561:
157	mfc0	k0, CP0_STATUS
158	sll	k0, k0, 3			# check CU0 (kernel?)
159	bltz	k0, 2f
160	 nop
161
162	/* Get a valid Kseg0 stack pointer.  Any task's stack pointer
163	 * will do, although if we ever want to resume execution we
164	 * better not have corrupted any state. */
165	get_saved_sp
166	move	sp, k1
167
1682:
169	j	sb1_cache_error
170	 nop
171
172	END(handle_vec2_sb1)
173