1 /*
2 * Copyright (C) 2001 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19 #include <linux/sched.h>
20 #include <asm/mipsregs.h>
21 #include <asm/sibyte/sb1250.h>
22
23 #ifndef CONFIG_SIBYTE_BUS_WATCHER
24 #include <asm/io.h>
25 #include <asm/sibyte/sb1250_regs.h>
26 #include <asm/sibyte/sb1250_scd.h>
27 #include <asm/sibyte/64bit.h>
28 #endif
29
30 /* SB1 definitions */
31
32 /* XXX should come from config1 XXX */
33 #define SB1_CACHE_INDEX_MASK 0x1fe0
34
35 #define CP0_ERRCTL_RECOVERABLE (1 << 31)
36 #define CP0_ERRCTL_DCACHE (1 << 30)
37 #define CP0_ERRCTL_ICACHE (1 << 29)
38 #define CP0_ERRCTL_MULTIBUS (1 << 23)
39 #define CP0_ERRCTL_MC_TLB (1 << 15)
40 #define CP0_ERRCTL_MC_TIMEOUT (1 << 14)
41
42 #define CP0_CERRI_TAG_PARITY (1 << 29)
43 #define CP0_CERRI_DATA_PARITY (1 << 28)
44 #define CP0_CERRI_EXTERNAL (1 << 26)
45
46 #define CP0_CERRI_IDX_VALID(c) (!((c) & CP0_CERRI_EXTERNAL))
47 #define CP0_CERRI_DATA (CP0_CERRI_DATA_PARITY)
48
49 #define CP0_CERRD_MULTIPLE (1 << 31)
50 #define CP0_CERRD_TAG_STATE (1 << 30)
51 #define CP0_CERRD_TAG_ADDRESS (1 << 29)
52 #define CP0_CERRD_DATA_SBE (1 << 28)
53 #define CP0_CERRD_DATA_DBE (1 << 27)
54 #define CP0_CERRD_EXTERNAL (1 << 26)
55 #define CP0_CERRD_LOAD (1 << 25)
56 #define CP0_CERRD_STORE (1 << 24)
57 #define CP0_CERRD_FILLWB (1 << 23)
58 #define CP0_CERRD_COHERENCY (1 << 22)
59 #define CP0_CERRD_DUPTAG (1 << 21)
60
61 #define CP0_CERRD_DPA_VALID(c) (!((c) & CP0_CERRD_EXTERNAL))
62 #define CP0_CERRD_IDX_VALID(c) \
63 (((c) & (CP0_CERRD_LOAD | CP0_CERRD_STORE)) ? (!((c) & CP0_CERRD_EXTERNAL)) : 0)
64 #define CP0_CERRD_CAUSES \
65 (CP0_CERRD_LOAD | CP0_CERRD_STORE | CP0_CERRD_FILLWB | CP0_CERRD_COHERENCY | CP0_CERRD_DUPTAG)
66 #define CP0_CERRD_TYPES \
67 (CP0_CERRD_TAG_STATE | CP0_CERRD_TAG_ADDRESS | CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE | CP0_CERRD_EXTERNAL)
68 #define CP0_CERRD_DATA (CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE)
69
70 static uint32_t extract_ic(unsigned short addr, int data);
71 static uint32_t extract_dc(unsigned short addr, int data);
72
breakout_errctl(unsigned int val)73 static inline void breakout_errctl(unsigned int val)
74 {
75 if (val & CP0_ERRCTL_RECOVERABLE)
76 prom_printf(" recoverable");
77 if (val & CP0_ERRCTL_DCACHE)
78 prom_printf(" dcache");
79 if (val & CP0_ERRCTL_ICACHE)
80 prom_printf(" icache");
81 if (val & CP0_ERRCTL_MULTIBUS)
82 prom_printf(" multiple-buserr");
83 prom_printf("\n");
84 }
85
breakout_cerri(unsigned int val)86 static inline void breakout_cerri(unsigned int val)
87 {
88 if (val & CP0_CERRI_TAG_PARITY)
89 prom_printf(" tag-parity");
90 if (val & CP0_CERRI_DATA_PARITY)
91 prom_printf(" data-parity");
92 if (val & CP0_CERRI_EXTERNAL)
93 prom_printf(" external");
94 prom_printf("\n");
95 }
96
breakout_cerrd(unsigned int val)97 static inline void breakout_cerrd(unsigned int val)
98 {
99 switch (val & CP0_CERRD_CAUSES) {
100 case CP0_CERRD_LOAD:
101 prom_printf(" load,");
102 break;
103 case CP0_CERRD_STORE:
104 prom_printf(" store,");
105 break;
106 case CP0_CERRD_FILLWB:
107 prom_printf(" fill/wb,");
108 break;
109 case CP0_CERRD_COHERENCY:
110 prom_printf(" coherency,");
111 break;
112 case CP0_CERRD_DUPTAG:
113 prom_printf(" duptags,");
114 break;
115 default:
116 prom_printf(" NO CAUSE,");
117 break;
118 }
119 if (!(val & CP0_CERRD_TYPES))
120 prom_printf(" NO TYPE");
121 else {
122 if (val & CP0_CERRD_MULTIPLE)
123 prom_printf(" multi-err");
124 if (val & CP0_CERRD_TAG_STATE)
125 prom_printf(" tag-state");
126 if (val & CP0_CERRD_TAG_ADDRESS)
127 prom_printf(" tag-address");
128 if (val & CP0_CERRD_DATA_SBE)
129 prom_printf(" data-SBE");
130 if (val & CP0_CERRD_DATA_DBE)
131 prom_printf(" data-DBE");
132 if (val & CP0_CERRD_EXTERNAL)
133 prom_printf(" external");
134 }
135 prom_printf("\n");
136 }
137
138 #ifndef CONFIG_SIBYTE_BUS_WATCHER
139
check_bus_watcher(void)140 static void check_bus_watcher(void)
141 {
142 uint32_t status, l2_err, memio_err;
143
144 /* Destructive read, clears register and interrupt */
145 status = csr_in32(IO_SPACE_BASE | A_SCD_BUS_ERR_STATUS);
146 /* Bit 31 is always on, but there's no #define for that */
147 if (status & ~(1UL << 31)) {
148 l2_err = csr_in32(IO_SPACE_BASE | A_BUS_L2_ERRORS);
149 memio_err = csr_in32(IO_SPACE_BASE | A_BUS_MEM_IO_ERRORS);
150 prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
151 prom_printf("\nLast recorded signature:\n");
152 prom_printf("Request %02x from %d, answered by %d with Dcode %d\n",
153 (unsigned int)(G_SCD_BERR_TID(status) & 0x3f),
154 (int)(G_SCD_BERR_TID(status) >> 6),
155 (int)G_SCD_BERR_RID(status),
156 (int)G_SCD_BERR_DCODE(status));
157 } else {
158 prom_printf("Bus watcher indicates no error\n");
159 }
160 }
161 #else
162 extern void check_bus_watcher(void);
163 #endif
164
sb1_cache_error(void)165 asmlinkage void sb1_cache_error(void)
166 {
167 uint64_t cerr_dpa;
168 uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res;
169
170 prom_printf("Cache error exception on CPU %x:\n",
171 (read_c0_prid() >> 25) & 0x7);
172
173 __asm__ __volatile__ (
174 " .set push\n\t"
175 " .set mips64\n\t"
176 " .set noat\n\t"
177 " mfc0 %0, $26\n\t"
178 " mfc0 %1, $27\n\t"
179 " mfc0 %2, $27, 1\n\t"
180 " dmfc0 $1, $27, 3\n\t"
181 " dsrl32 %3, $1, 0 \n\t"
182 " sll %4, $1, 0 \n\t"
183 " mfc0 %5, $30\n\t"
184 " .set pop"
185 : "=r" (errctl), "=r" (cerr_i), "=r" (cerr_d),
186 "=r" (dpahi), "=r" (dpalo), "=r" (eepc));
187
188 cerr_dpa = (((uint64_t)dpahi) << 32) | dpalo;
189 prom_printf(" c0_errorepc == %08x\n", eepc);
190 prom_printf(" c0_errctl == %08x", errctl);
191 breakout_errctl(errctl);
192 if (errctl & CP0_ERRCTL_ICACHE) {
193 prom_printf(" c0_cerr_i == %08x", cerr_i);
194 breakout_cerri(cerr_i);
195 if (CP0_CERRI_IDX_VALID(cerr_i)) {
196 /* Check index of EPC, allowing for delay slot */
197 if (((eepc & SB1_CACHE_INDEX_MASK) != (cerr_i & SB1_CACHE_INDEX_MASK)) &&
198 ((eepc & SB1_CACHE_INDEX_MASK) != ((cerr_i & SB1_CACHE_INDEX_MASK) - 4)))
199 prom_printf(" cerr_i idx doesn't match eepc\n");
200 else {
201 res = extract_ic(cerr_i & SB1_CACHE_INDEX_MASK,
202 (cerr_i & CP0_CERRI_DATA) != 0);
203 if (!(res & cerr_i))
204 prom_printf("...didn't see indicated icache problem\n");
205 }
206 }
207 }
208 if (errctl & CP0_ERRCTL_DCACHE) {
209 prom_printf(" c0_cerr_d == %08x", cerr_d);
210 breakout_cerrd(cerr_d);
211 if (CP0_CERRD_DPA_VALID(cerr_d)) {
212 prom_printf(" c0_cerr_dpa == %010llx\n", cerr_dpa);
213 if (!CP0_CERRD_IDX_VALID(cerr_d)) {
214 res = extract_dc(cerr_dpa & SB1_CACHE_INDEX_MASK,
215 (cerr_d & CP0_CERRD_DATA) != 0);
216 if (!(res & cerr_d))
217 prom_printf("...didn't see indicated dcache problem\n");
218 } else {
219 if ((cerr_dpa & SB1_CACHE_INDEX_MASK) != (cerr_d & SB1_CACHE_INDEX_MASK))
220 prom_printf(" cerr_d idx doesn't match cerr_dpa\n");
221 else {
222 res = extract_dc(cerr_d & SB1_CACHE_INDEX_MASK,
223 (cerr_d & CP0_CERRD_DATA) != 0);
224 if (!(res & cerr_d))
225 prom_printf("...didn't see indicated problem\n");
226 }
227 }
228 }
229 }
230
231 check_bus_watcher();
232
233 while (1);
234 /*
235 * This tends to make things get really ugly; let's just stall instead.
236 * panic("Can't handle the cache error!");
237 */
238 }
239
240
241 /* Parity lookup table. */
242 static const uint8_t parity[256] = {
243 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
244 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
245 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
246 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
247 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
248 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
249 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
250 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0
251 };
252
253 /* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */
254 static const uint64_t mask_72_64[8] = {
255 0x0738C808099264FFL,
256 0x38C808099264FF07L,
257 0xC808099264FF0738L,
258 0x08099264FF0738C8L,
259 0x099264FF0738C808L,
260 0x9264FF0738C80809L,
261 0x64FF0738C8080992L,
262 0xFF0738C808099264L
263 };
264
265 /* Calculate the parity on a range of bits */
range_parity(uint64_t dword,int max,int min)266 static char range_parity(uint64_t dword, int max, int min)
267 {
268 char parity = 0;
269 int i;
270 dword >>= min;
271 for (i=max-min; i>=0; i--) {
272 if (dword & 0x1)
273 parity = !parity;
274 dword >>= 1;
275 }
276 return parity;
277 }
278
279 /* Calculate the 4-bit even byte-parity for an instruction */
inst_parity(uint32_t word)280 static unsigned char inst_parity(uint32_t word)
281 {
282 int i, j;
283 char parity = 0;
284 for (j=0; j<4; j++) {
285 char byte_parity = 0;
286 for (i=0; i<8; i++) {
287 if (word & 0x80000000)
288 byte_parity = !byte_parity;
289 word <<= 1;
290 }
291 parity <<= 1;
292 parity |= byte_parity;
293 }
294 return parity;
295 }
296
extract_ic(unsigned short addr,int data)297 static uint32_t extract_ic(unsigned short addr, int data)
298 {
299 unsigned short way;
300 int valid;
301 uint64_t taglo, va, tlo_tmp;
302 uint32_t taghi, taglolo, taglohi;
303 uint8_t lru;
304 int res = 0;
305
306 prom_printf("Icache index 0x%04x ", addr);
307 for (way = 0; way < 4; way++) {
308 /* Index-load-tag-I */
309 __asm__ __volatile__ (
310 " .set push \n\t"
311 " .set noreorder \n\t"
312 " .set mips64 \n\t"
313 " .set noat \n\t"
314 " cache 4, 0(%3) \n\t"
315 " mfc0 %0, $29 \n\t"
316 " dmfc0 $1, $28 \n\t"
317 " dsrl32 %1, $1, 0 \n\t"
318 " sll %2, $1, 0 \n\t"
319 " .set pop"
320 : "=r" (taghi), "=r" (taglohi), "=r" (taglolo)
321 : "r" ((way << 13) | addr));
322
323 taglo = ((unsigned long long)taglohi << 32) | taglolo;
324 if (way == 0) {
325 lru = (taghi >> 14) & 0xff;
326 prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n",
327 ((addr >> 5) & 0x3), /* bank */
328 ((addr >> 7) & 0x3f), /* index */
329 (lru & 0x3),
330 ((lru >> 2) & 0x3),
331 ((lru >> 4) & 0x3),
332 ((lru >> 6) & 0x3));
333 }
334 va = (taglo & 0xC0000FFFFFFFE000) | addr;
335 if ((taglo & (1 << 31)) && (((taglo >> 62) & 0x3) == 3))
336 va |= 0x3FFFF00000000000;
337 valid = ((taghi >> 29) & 1);
338 if (valid) {
339 tlo_tmp = taglo & 0xfff3ff;
340 if (((taglo >> 10) & 1) ^ range_parity(tlo_tmp, 23, 0)) {
341 prom_printf(" ** bad parity in VTag0/G/ASID\n");
342 res |= CP0_CERRI_TAG_PARITY;
343 }
344 if (((taglo >> 11) & 1) ^ range_parity(taglo, 63, 24)) {
345 prom_printf(" ** bad parity in R/VTag1\n");
346 res |= CP0_CERRI_TAG_PARITY;
347 }
348 }
349 if (valid ^ ((taghi >> 27) & 1)) {
350 prom_printf(" ** bad parity for valid bit\n");
351 res |= CP0_CERRI_TAG_PARITY;
352 }
353 prom_printf(" %d [VA %016llx] [Vld? %d] raw tags: %08X-%016llX\n",
354 way, va, valid, taghi, taglo);
355
356 if (data) {
357 uint32_t datahi, insta, instb;
358 uint8_t predecode;
359 int offset;
360
361 /* (hit all banks and ways) */
362 for (offset = 0; offset < 4; offset++) {
363 /* Index-load-data-I */
364 __asm__ __volatile__ (
365 " .set push\n\t"
366 " .set noreorder\n\t"
367 " .set mips64\n\t"
368 " .set noat\n\t"
369 " cache 6, 0(%3) \n\t"
370 " mfc0 %0, $29, 1\n\t"
371 " dmfc0 $1, $28, 1\n\t"
372 " dsrl32 %1, $1, 0 \n\t"
373 " sll %2, $1, 0 \n\t"
374 " .set pop \n"
375 : "=r" (datahi), "=r" (insta), "=r" (instb)
376 : "r" ((way << 13) | addr | (offset << 3)));
377 predecode = (datahi >> 8) & 0xff;
378 if (((datahi >> 16) & 1) != (uint32_t)range_parity(predecode, 7, 0)) {
379 prom_printf(" ** bad parity in predecode\n");
380 res |= CP0_CERRI_DATA_PARITY;
381 }
382 /* XXXKW should/could check predecode bits themselves */
383 if (((datahi >> 4) & 0xf) ^ inst_parity(insta)) {
384 prom_printf(" ** bad parity in instruction a\n");
385 res |= CP0_CERRI_DATA_PARITY;
386 }
387 if ((datahi & 0xf) ^ inst_parity(instb)) {
388 prom_printf(" ** bad parity in instruction b\n");
389 res |= CP0_CERRI_DATA_PARITY;
390 }
391 prom_printf(" %05X-%08X%08X", datahi, insta, instb);
392 }
393 prom_printf("\n");
394 }
395 }
396 return res;
397 }
398
399 /* Compute the ECC for a data doubleword */
dc_ecc(uint64_t dword)400 static uint8_t dc_ecc(uint64_t dword)
401 {
402 uint64_t t;
403 uint32_t w;
404 uint8_t p;
405 int i;
406
407 p = 0;
408 for (i = 7; i >= 0; i--)
409 {
410 p <<= 1;
411 t = dword & mask_72_64[i];
412 w = (uint32_t)(t >> 32);
413 p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF]
414 ^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]);
415 w = (uint32_t)(t & 0xFFFFFFFF);
416 p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF]
417 ^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]);
418 }
419 return p;
420 }
421
422 struct dc_state {
423 unsigned char val;
424 char *name;
425 };
426
427 static struct dc_state dc_states[] = {
428 { 0x00, "INVALID" },
429 { 0x0f, "COH-SHD" },
430 { 0x13, "NCO-E-C" },
431 { 0x19, "NCO-E-D" },
432 { 0x16, "COH-E-C" },
433 { 0x1c, "COH-E-D" },
434 { 0xff, "*ERROR*" }
435 };
436
437 #define DC_TAG_VALID(state) \
438 (((state) == 0xf) || ((state) == 0x13) || ((state) == 0x19) || ((state == 0x16)) || ((state) == 0x1c))
439
dc_state_str(unsigned char state)440 static char *dc_state_str(unsigned char state)
441 {
442 struct dc_state *dsc = dc_states;
443 while (dsc->val != 0xff) {
444 if (dsc->val == state)
445 break;
446 dsc++;
447 }
448 return dsc->name;
449 }
450
extract_dc(unsigned short addr,int data)451 static uint32_t extract_dc(unsigned short addr, int data)
452 {
453 int valid, way;
454 unsigned char state;
455 uint64_t taglo, pa;
456 uint32_t taghi, taglolo, taglohi;
457 uint8_t ecc, lru;
458 int res = 0;
459
460 prom_printf("Dcache index 0x%04x ", addr);
461 for (way = 0; way < 4; way++) {
462 __asm__ __volatile__ (
463 " .set push\n\t"
464 " .set noreorder\n\t"
465 " .set mips64\n\t"
466 " .set noat\n\t"
467 " cache 5, 0(%3)\n\t" /* Index-load-tag-D */
468 " mfc0 %0, $29, 2\n\t"
469 " dmfc0 $1, $28, 2\n\t"
470 " dsrl32 %1, $1, 0\n\t"
471 " sll %2, $1, 0\n\t"
472 " .set pop"
473 : "=r" (taghi), "=r" (taglohi), "=r" (taglolo)
474 : "r" ((way << 13) | addr));
475
476 taglo = ((unsigned long long)taglohi << 32) | taglolo;
477 pa = (taglo & 0xFFFFFFE000) | addr;
478 if (way == 0) {
479 lru = (taghi >> 14) & 0xff;
480 prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n",
481 ((addr >> 11) & 0x2) | ((addr >> 5) & 1), /* bank */
482 ((addr >> 6) & 0x3f), /* index */
483 (lru & 0x3),
484 ((lru >> 2) & 0x3),
485 ((lru >> 4) & 0x3),
486 ((lru >> 6) & 0x3));
487 }
488 state = (taghi >> 25) & 0x1f;
489 valid = DC_TAG_VALID(state);
490 prom_printf(" %d [PA %010llx] [state %s (%02x)] raw tags: %08X-%016llX\n",
491 way, pa, dc_state_str(state), state, taghi, taglo);
492 if (valid) {
493 if (((taglo >> 11) & 1) ^ range_parity(taglo, 39, 26)) {
494 prom_printf(" ** bad parity in PTag1\n");
495 res |= CP0_CERRD_TAG_ADDRESS;
496 }
497 if (((taglo >> 10) & 1) ^ range_parity(taglo, 25, 13)) {
498 prom_printf(" ** bad parity in PTag0\n");
499 res |= CP0_CERRD_TAG_ADDRESS;
500 }
501 } else {
502 res |= CP0_CERRD_TAG_STATE;
503 }
504
505 if (data) {
506 uint64_t datalo;
507 uint32_t datalohi, datalolo, datahi;
508 int offset;
509
510 for (offset = 0; offset < 4; offset++) {
511 /* Index-load-data-D */
512 __asm__ __volatile__ (
513 " .set push\n\t"
514 " .set noreorder\n\t"
515 " .set mips64\n\t"
516 " .set noat\n\t"
517 " cache 7, 0(%3)\n\t" /* Index-load-data-D */
518 " mfc0 %0, $29, 3\n\t"
519 " dmfc0 $1, $28, 3\n\t"
520 " dsrl32 %1, $1, 0 \n\t"
521 " sll %2, $1, 0 \n\t"
522 " .set pop"
523 : "=r" (datahi), "=r" (datalohi), "=r" (datalolo)
524 : "r" ((way << 13) | addr | (offset << 3)));
525 datalo = ((unsigned long long)datalohi << 32) | datalolo;
526 ecc = dc_ecc(datalo);
527 if (ecc != datahi) {
528 int bits = 0;
529 prom_printf(" ** bad ECC (%02x %02x) ->",
530 datahi, ecc);
531 ecc ^= datahi;
532 while (ecc) {
533 if (ecc & 1) bits++;
534 ecc >>= 1;
535 }
536 res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE;
537 }
538 prom_printf(" %02X-%016llX", datahi, datalo);
539 }
540 prom_printf("\n");
541 }
542 }
543 return res;
544 }
545