1 /*
2 * Toshiba rbtx4927 specific setup
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2001-2002 MontaVista Software Inc.
8 *
9 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
13 *
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
16 *
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
19 *
20 * Copyright (C) 2000-2001 Toshiba Corporation
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
26 *
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
33 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
34 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
35 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
36 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
41 */
42 #include <linux/config.h>
43 #include <linux/init.h>
44 #include <linux/kernel.h>
45 #include <linux/types.h>
46 #include <linux/mm.h>
47 #include <linux/swap.h>
48 #include <linux/ioport.h>
49 #include <linux/sched.h>
50 #include <linux/interrupt.h>
51 #include <linux/pci.h>
52 #include <linux/timex.h>
53 #include <asm/bootinfo.h>
54 #include <asm/page.h>
55 #include <asm/bootinfo.h>
56 #include <asm/io.h>
57 #include <asm/irq.h>
58 #include <asm/pci.h>
59 #include <asm/processor.h>
60 #include <asm/ptrace.h>
61 #include <asm/reboot.h>
62 #include <asm/time.h>
63 #include <linux/version.h>
64 #include <linux/bootmem.h>
65 #include <linux/blk.h>
66 #include <linux/console.h>
67 #ifdef CONFIG_DS1742
68 #include <asm/mc146818rtc.h>
69 #endif
70 #ifdef CONFIG_TOSHIBA_FPCIB0
71 #include <asm/smsc_fdc37m81x.h>
72 #endif
73 #include <asm/tx4927/toshiba_rbtx4927.h>
74 #ifdef CONFIG_PCI
75 #include <asm/tx4927/tx4927_pci.h>
76 #include <linux/types.h>
77 #include <linux/pci.h>
78 #include <linux/kernel.h>
79 #include <linux/init.h>
80 #include <asm/pci_channel.h>
81 #endif
82 #ifdef CONFIG_PC_KEYB
83 #include <asm/keyboard.h>
84 #endif
85 #ifdef CONFIG_BLK_DEV_IDEPCI
86 #include <linux/hdreg.h>
87 #include <asm/ptrace.h>
88 #include <linux/ide.h>
89 extern struct ide_ops std_ide_ops;
90 #endif
91
92 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
93
94 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
95 #define TOSHIBA_RBTX4927_SETUP_NONE 0x00000000
96
97 #define TOSHIBA_RBTX4927_SETUP_INFO ( 1 << 0 )
98 #define TOSHIBA_RBTX4927_SETUP_WARN ( 1 << 1 )
99 #define TOSHIBA_RBTX4927_SETUP_EROR ( 1 << 2 )
100
101 #define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
102 #define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
103 #define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
104 #define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 << 6 )
105 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
106 #define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
107 #define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
108 #define TOSHIBA_RBTX4927_SETUP_PCI66 ( 1 << 10 )
109
110 #define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
111 #endif
112
113 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
114 static const u32 toshiba_rbtx4927_setup_debug_flag =
115 (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
116 TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
117 TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
118 TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
119 | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
120 TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
121 #endif
122
123 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
124 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
125 if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
126 { \
127 char tmp[100]; \
128 sprintf( tmp, str ); \
129 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
130 }
131 #else
132 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...)
133 #endif
134
135 /* These functions are used for rebooting or halting the machine*/
136 extern void toshiba_rbtx4927_restart(char *command);
137 extern void toshiba_rbtx4927_halt(void);
138 extern void toshiba_rbtx4927_power_off(void);
139
140 int tx4927_using_backplane = 0;
141
142 extern void gt64120_time_init(void);
143 extern void toshiba_rbtx4927_irq_setup(void);
144
145 #ifdef CONFIG_PCI
146 #define CONFIG_TX4927BUG_WORKAROUND
147 #undef TX4927_SUPPORT_COMMAND_IO
148 #undef TX4927_SUPPORT_PCI_66
149 int tx4927_cpu_clock = 100000000; /* 100MHz */
150 unsigned long mips_pci_io_base;
151 unsigned long mips_pci_io_size;
152 unsigned long mips_pci_mem_base;
153 unsigned long mips_pci_mem_size;
154 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
155 unsigned long mips_pci_io_pciaddr = 0;
156 unsigned long mips_memory_upper;
157 static int tx4927_ccfg_toeon = 1;
158 static int tx4927_pcic_trdyto = 0; /* default: disabled */
159 unsigned long tx4927_ce_base[8];
160 void tx4927_pci_setup(void);
161 void tx4927_reset_pci_pcic(void);
162 #ifdef TX4927_SUPPORT_PCI_66
163 void tx4927_pci66_setup(void);
164 extern int tx4927_pci66_check(void);
165 #endif
166 int tx4927_pci66 = 0; /* 0:auto */
167 #endif
168
169 char *toshiba_name = "";
170
171 #ifdef CONFIG_PCI
tx4927_dump_pcic_settings(void)172 void tx4927_dump_pcic_settings(void)
173 {
174 printk("%s pcic settings:",toshiba_name);
175 {
176 int i;
177 unsigned long *preg = (unsigned long *) tx4927_pcicptr;
178 for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4) {
179 if (i % 32 == 0)
180 printk("\n%04x:", i);
181 if (preg == &tx4927_pcicptr->g2pintack
182 || preg == &tx4927_pcicptr->g2pspc
183 #ifdef CONFIG_TX4927BUG_WORKAROUND
184 || preg == &tx4927_pcicptr->g2pcfgadrs
185 || preg == &tx4927_pcicptr->g2pcfgdata
186 #endif
187 ) {
188 printk(" XXXXXXXX");
189 preg++;
190 continue;
191 }
192 printk(" %08lx", *preg++);
193 if (preg == &tx4927_pcicptr->g2pcfgadrs)
194 break;
195 }
196 printk("\n");
197 }
198 }
199
tx4927_pcierr_interrupt(int irq,void * dev_id,struct pt_regs * regs)200 static void tx4927_pcierr_interrupt(int irq, void *dev_id,
201 struct pt_regs *regs)
202 {
203 extern void tx4927_dump_pcic_settings(void);
204
205 #ifdef CONFIG_BLK_DEV_IDEPCI
206 /* ignore MasterAbort for ide probing... */
207 if (irq == TX4927_IRQ_IRC_PCIERR &&
208 ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) ==
209 PCI_STATUS_REC_MASTER_ABORT) {
210 tx4927_pcicptr->pcistatus =
211 (tx4927_pcicptr->
212 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
213 << 16);
214
215 return;
216 }
217 #endif
218 printk("PCI error interrupt (irq 0x%x).\n", irq);
219 printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n",
220 (unsigned short) (tx4927_pcicptr->pcistatus >> 16),
221 tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus);
222 printk("ccfg:%08lx, tear:%02lx_%08lx\n",
223 (unsigned long) tx4927_ccfgptr->ccfg,
224 (unsigned long) (tx4927_ccfgptr->tear >> 32),
225 (unsigned long) tx4927_ccfgptr->tear);
226 show_regs(regs);
227 //tx4927_dump_pcic_settings();
228 panic("PCI error at PC:%08lx.", regs->cp0_epc);
229 }
230
231 static struct irqaction pcic_action = {
232 tx4927_pcierr_interrupt, 0, 0, "PCI-C", NULL, NULL
233 };
234
235 static struct irqaction pcierr_action = {
236 tx4927_pcierr_interrupt, 0, 0, "PCI-ERR", NULL, NULL
237 };
238
239
toshiba_rbtx4927_pci_irq_init(void)240 void __init toshiba_rbtx4927_pci_irq_init(void)
241 {
242 setup_irq(TX4927_IRQ_IRC_PCIC, &pcic_action);
243 setup_irq(TX4927_IRQ_IRC_PCIERR, &pcierr_action);
244 }
245
tx4927_reset_pci_pcic(void)246 void tx4927_reset_pci_pcic(void)
247 {
248 /* Reset PCI Bus */
249 *tx4927_pcireset_ptr = 1;
250 /* Reset PCIC */
251 tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST;
252 udelay(10000);
253 /* clear PCIC reset */
254 tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST;
255 *tx4927_pcireset_ptr = 0;
256 }
257 #endif /* CONFIG_PCI */
258
259 #ifdef CONFIG_PCI
260 #ifdef TX4927_SUPPORT_PCI_66
tx4927_pci66_setup(void)261 void tx4927_pci66_setup(void)
262 {
263 int pciclk, pciclkin = 1;
264
265 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI66,
266 "-\n");
267
268 if (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66)
269 return;
270
271 tx4927_reset_pci_pcic();
272
273 /* Assert M66EN */
274 tx4927_ccfgptr->ccfg |= TX4927_CCFG_PCI66;
275 /* set PCICLK 66MHz */
276 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
277 unsigned int pcidivmode = 0;
278 pcidivmode =
279 (unsigned long) tx4927_ccfgptr->
280 ccfg & TX4927_CCFG_PCIDIVMODE_MASK;
281 if (tx4927_cpu_clock >= 170000000) {
282 /* CPU 200MHz */
283 pcidivmode = TX4927_CCFG_PCIDIVMODE_3;
284 pciclk = tx4927_cpu_clock / 3;
285 } else {
286 /* CPU 166MHz */
287 pcidivmode = TX4927_CCFG_PCIDIVMODE_2_5;
288 pciclk = tx4927_cpu_clock * 2 / 5;
289 }
290 tx4927_ccfgptr->ccfg =
291 (tx4927_ccfgptr->ccfg & ~TX4927_CCFG_PCIDIVMODE_MASK)
292 | pcidivmode;
293 TOSHIBA_RBTX4927_SETUP_DPRINTK
294 (TOSHIBA_RBTX4927_SETUP_PCI66,
295 ":PCICLK: ccfg:0x%08lx\n",
296 (unsigned long) tx4927_ccfgptr->ccfg);
297 } else {
298 int pciclk_setting = *tx4927_pci_clk_ptr;
299 pciclkin = 0;
300 pciclk = 66666666;
301 pciclk_setting &= ~TX4927_PCI_CLK_MASK;
302 pciclk_setting |= TX4927_PCI_CLK_66;
303 *tx4927_pci_clk_ptr = pciclk_setting;
304 TOSHIBA_RBTX4927_SETUP_DPRINTK
305 (TOSHIBA_RBTX4927_SETUP_PCI66,
306 "PCICLK: pci_clk:%02x\n", *tx4927_pci_clk_ptr);
307 }
308
309 udelay(10000);
310
311 /* clear PCIC reset */
312 tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST;
313 /* clear PCI reset */
314 *tx4927_pcireset_ptr = 0;
315
316 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI66,
317 "+\n");
318 }
319 #endif /* TX4927_SUPPORT_PCI_66 */
320
print_pci_status(void)321 void print_pci_status(void)
322 {
323 printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus);
324 printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus);
325 }
326
fake_pci_dev(struct pci_channel * hose,int top_bus,int busnr,int devfn)327 static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
328 int top_bus, int busnr, int devfn)
329 {
330 static struct pci_dev dev;
331 static struct pci_bus bus;
332
333 dev.bus = &bus;
334 dev.sysdata = hose;
335 dev.devfn = devfn;
336 bus.number = busnr;
337 bus.ops = hose->pci_ops;
338
339 if (busnr != top_bus)
340 /* Fake a parent bus structure. */
341 bus.parent = &bus;
342 else
343 bus.parent = NULL;
344
345 return &dev;
346 }
347
348 #define EARLY_PCI_OP(rw, size, type) \
349 static int early_##rw##_config_##size(struct pci_channel *hose, \
350 int top_bus, int bus, int devfn, int offset, type value) \
351 { \
352 return pci_##rw##_config_##size( \
353 fake_pci_dev(hose, top_bus, bus, devfn), \
354 offset, value); \
355 }
356
EARLY_PCI_OP(read,byte,u8 *)357 EARLY_PCI_OP(read, byte, u8 *)
358 EARLY_PCI_OP(read, dword, u32 *)
359 EARLY_PCI_OP(write, byte, u8)
360 EARLY_PCI_OP(write, dword, u32)
361
362 static int __init tx4927_pcibios_init(int busno, struct pci_channel *hose)
363 {
364 u32 pci_devfn;
365 int devfn_start = 0;
366 int devfn_stop = 0xff;
367 unsigned int id;
368
369 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
370 "-\n");
371
372 if (hose->first_devfn)
373 devfn_start = hose->first_devfn;
374 if (hose->last_devfn)
375 devfn_stop = hose->last_devfn;
376
377 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
378 early_read_config_dword(hose, busno, busno, pci_devfn,
379 PCI_VENDOR_ID, &id);
380
381 if (id == 0xffffffff) {
382 continue;
383 }
384
385 if (id == 0x94601055) {
386 u8 v08_64;
387 u32 v32_b0;
388 u8 v08_e1;
389 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
390 char *s = " sb/isa --";
391 #endif
392
393 TOSHIBA_RBTX4927_SETUP_DPRINTK
394 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
395 s);
396
397 early_read_config_byte(hose, busno, busno,
398 pci_devfn, 0x64, &v08_64);
399 early_read_config_dword(hose, busno, busno,
400 pci_devfn, 0xb0, &v32_b0);
401 early_read_config_byte(hose, busno, busno,
402 pci_devfn, 0xe1, &v08_e1);
403
404 TOSHIBA_RBTX4927_SETUP_DPRINTK
405 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
406 ":%s beg 0x64 = 0x%02x\n", s, v08_64);
407 TOSHIBA_RBTX4927_SETUP_DPRINTK
408 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
409 ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
410 TOSHIBA_RBTX4927_SETUP_DPRINTK
411 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
412 ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
413
414 /* serial irq control */
415 v08_64 = 0xd0;
416
417 /* serial irq pin */
418 v32_b0 |= 0x00010000;
419
420 /* ide irq on isa14 */
421 v08_e1 &= 0xf0;
422 v08_e1 |= 0x0d;
423
424 TOSHIBA_RBTX4927_SETUP_DPRINTK
425 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
426 ":%s mid 0x64 = 0x%02x\n", s, v08_64);
427 TOSHIBA_RBTX4927_SETUP_DPRINTK
428 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
429 ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
430 TOSHIBA_RBTX4927_SETUP_DPRINTK
431 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
432 ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
433
434 early_write_config_byte(hose, busno, busno,
435 pci_devfn, 0x64, v08_64);
436 early_write_config_dword(hose, busno, busno,
437 pci_devfn, 0xb0, v32_b0);
438 early_write_config_byte(hose, busno, busno,
439 pci_devfn, 0xe1, v08_e1);
440
441 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
442 {
443 early_read_config_byte(hose, busno, busno,
444 pci_devfn, 0x64,
445 &v08_64);
446 early_read_config_dword(hose, busno, busno,
447 pci_devfn, 0xb0,
448 &v32_b0);
449 early_read_config_byte(hose, busno, busno,
450 pci_devfn, 0xe1,
451 &v08_e1);
452
453 TOSHIBA_RBTX4927_SETUP_DPRINTK
454 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
455 ":%s end 0x64 = 0x%02x\n", s, v08_64);
456 TOSHIBA_RBTX4927_SETUP_DPRINTK
457 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
458 ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
459 TOSHIBA_RBTX4927_SETUP_DPRINTK
460 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
461 ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
462 }
463 #endif
464
465 TOSHIBA_RBTX4927_SETUP_DPRINTK
466 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
467 s);
468 }
469
470 if (id == 0x91301055) {
471 u8 v08_04;
472 u8 v08_09;
473 u8 v08_41;
474 u8 v08_43;
475 u8 v08_5c;
476 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
477 char *s = " sb/ide --";
478 #endif
479
480 TOSHIBA_RBTX4927_SETUP_DPRINTK
481 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
482 s);
483
484 early_read_config_byte(hose, busno, busno,
485 pci_devfn, 0x04, &v08_04);
486 early_read_config_byte(hose, busno, busno,
487 pci_devfn, 0x09, &v08_09);
488 early_read_config_byte(hose, busno, busno,
489 pci_devfn, 0x41, &v08_41);
490 early_read_config_byte(hose, busno, busno,
491 pci_devfn, 0x43, &v08_43);
492 early_read_config_byte(hose, busno, busno,
493 pci_devfn, 0x5c, &v08_5c);
494
495 TOSHIBA_RBTX4927_SETUP_DPRINTK
496 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
497 ":%s beg 0x04 = 0x%02x\n", s, v08_04);
498 TOSHIBA_RBTX4927_SETUP_DPRINTK
499 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
500 ":%s beg 0x09 = 0x%02x\n", s, v08_09);
501 TOSHIBA_RBTX4927_SETUP_DPRINTK
502 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
503 ":%s beg 0x41 = 0x%02x\n", s, v08_41);
504 TOSHIBA_RBTX4927_SETUP_DPRINTK
505 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
506 ":%s beg 0x43 = 0x%02x\n", s, v08_43);
507 TOSHIBA_RBTX4927_SETUP_DPRINTK
508 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
509 ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
510
511 /* enable ide master/io */
512 v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
513
514 /* enable ide native mode */
515 v08_09 |= 0x05;
516
517 /* enable primary ide */
518 v08_41 |= 0x80;
519
520 /* enable secondary ide */
521 v08_43 |= 0x80;
522
523 /*
524 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
525 *
526 * This line of code is intended to provide the user with a work
527 * around solution to the anomalies cited in SMSC's anomaly sheet
528 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
529 *
530 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
531 */
532 v08_5c |= 0x01;
533
534 TOSHIBA_RBTX4927_SETUP_DPRINTK
535 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
536 ":%s mid 0x04 = 0x%02x\n", s, v08_04);
537 TOSHIBA_RBTX4927_SETUP_DPRINTK
538 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
539 ":%s mid 0x09 = 0x%02x\n", s, v08_09);
540 TOSHIBA_RBTX4927_SETUP_DPRINTK
541 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
542 ":%s mid 0x41 = 0x%02x\n", s, v08_41);
543 TOSHIBA_RBTX4927_SETUP_DPRINTK
544 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
545 ":%s mid 0x43 = 0x%02x\n", s, v08_43);
546 TOSHIBA_RBTX4927_SETUP_DPRINTK
547 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
548 ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
549
550 early_write_config_byte(hose, busno, busno,
551 pci_devfn, 0x5c, v08_5c);
552 early_write_config_byte(hose, busno, busno,
553 pci_devfn, 0x04, v08_04);
554 early_write_config_byte(hose, busno, busno,
555 pci_devfn, 0x09, v08_09);
556 early_write_config_byte(hose, busno, busno,
557 pci_devfn, 0x41, v08_41);
558 early_write_config_byte(hose, busno, busno,
559 pci_devfn, 0x43, v08_43);
560
561 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
562 {
563 early_read_config_byte(hose, busno, busno,
564 pci_devfn, 0x04,
565 &v08_04);
566 early_read_config_byte(hose, busno, busno,
567 pci_devfn, 0x09,
568 &v08_09);
569 early_read_config_byte(hose, busno, busno,
570 pci_devfn, 0x41,
571 &v08_41);
572 early_read_config_byte(hose, busno, busno,
573 pci_devfn, 0x43,
574 &v08_43);
575 early_read_config_byte(hose, busno, busno,
576 pci_devfn, 0x5c,
577 &v08_5c);
578
579 TOSHIBA_RBTX4927_SETUP_DPRINTK
580 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
581 ":%s end 0x04 = 0x%02x\n", s, v08_04);
582 TOSHIBA_RBTX4927_SETUP_DPRINTK
583 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
584 ":%s end 0x09 = 0x%02x\n", s, v08_09);
585 TOSHIBA_RBTX4927_SETUP_DPRINTK
586 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
587 ":%s end 0x41 = 0x%02x\n", s, v08_41);
588 TOSHIBA_RBTX4927_SETUP_DPRINTK
589 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
590 ":%s end 0x43 = 0x%02x\n", s, v08_43);
591 TOSHIBA_RBTX4927_SETUP_DPRINTK
592 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
593 ":%s end 0x5c = 0x%02x\n", s, v08_5c);
594 }
595 #endif
596
597 TOSHIBA_RBTX4927_SETUP_DPRINTK
598 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
599 s);
600 }
601
602 }
603
604 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
605 "+\n");
606
607 return (busno);
608 }
609
610 extern struct resource pci_io_resource;
611 extern struct resource pci_mem_resource;
612
tx4927_pci_setup(void)613 void tx4927_pci_setup(void)
614 {
615 static int called = 0;
616 extern unsigned int tx4927_get_mem_size(void);
617
618 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
619
620 #ifndef TX4927_SUPPORT_PCI_66
621 if (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66)
622 printk("PCI 66 current unsupported\n");
623 #endif
624
625 mips_memory_upper = tx4927_get_mem_size() << 20;
626 mips_memory_upper += KSEG0;
627 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
628 "0x%08lx=mips_memory_upper\n",
629 mips_memory_upper);
630 mips_pci_io_base = TX4927_PCIIO;
631 mips_pci_io_size = TX4927_PCIIO_SIZE;
632 mips_pci_mem_base = TX4927_PCIMEM;
633 mips_pci_mem_size = TX4927_PCIMEM_SIZE;
634
635 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
636 "0x%08lx=mips_pci_io_base\n",
637 mips_pci_io_base);
638 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
639 "0x%08lx=mips_pci_io_size\n",
640 mips_pci_io_size);
641 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
642 "0x%08lx=mips_pci_mem_base\n",
643 mips_pci_mem_base);
644 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
645 "0x%08lx=mips_pci_mem_size\n",
646 mips_pci_mem_size);
647 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
648 "0x%08lx=pci_io_resource.start\n",
649 pci_io_resource.start);
650 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
651 "0x%08lx=pci_io_resource.end\n",
652 pci_io_resource.end);
653 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
654 "0x%08lx=pci_mem_resource.start\n",
655 pci_mem_resource.start);
656 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
657 "0x%08lx=pci_mem_resource.end\n",
658 pci_mem_resource.end);
659 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
660 "0x%08lx=mips_io_port_base",
661 mips_io_port_base);
662
663 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
664 "setup pci_io_resource to 0x%08lx 0x%08lx\n",
665 pci_io_resource.start,
666 pci_io_resource.end);
667 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
668 "setup pci_mem_resource to 0x%08lx 0x%08lx\n",
669 pci_mem_resource.start,
670 pci_mem_resource.end);
671
672 if (!called) {
673 printk
674 ("TX4927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
675 (unsigned short) (tx4927_pcicptr->pciid >> 16),
676 (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
677 (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
678 (!(tx4927_ccfgptr->
679 ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
680 "Internal");
681 called = 1;
682 }
683 printk("%s PCIC --%s PCICLK:",toshiba_name,
684 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
685 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
686 int pciclk = 0;
687 switch ((unsigned long) tx4927_ccfgptr->
688 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
689 case TX4927_CCFG_PCIDIVMODE_2_5:
690 pciclk = tx4927_cpu_clock * 2 / 5;
691 break;
692 case TX4927_CCFG_PCIDIVMODE_3:
693 pciclk = tx4927_cpu_clock / 3;
694 break;
695 case TX4927_CCFG_PCIDIVMODE_5:
696 pciclk = tx4927_cpu_clock / 5;
697 break;
698 case TX4927_CCFG_PCIDIVMODE_6:
699 pciclk = tx4927_cpu_clock / 6;
700 break;
701 }
702 printk("Internal(%dMHz)", pciclk / 1000000);
703 } else {
704 int pciclk = 0;
705 int pciclk_setting = *tx4927_pci_clk_ptr;
706 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
707 case TX4927_PCI_CLK_33:
708 pciclk = 33333333;
709 break;
710 case TX4927_PCI_CLK_25:
711 pciclk = 25000000;
712 break;
713 case TX4927_PCI_CLK_66:
714 pciclk = 66666666;
715 break;
716 case TX4927_PCI_CLK_50:
717 pciclk = 50000000;
718 break;
719 }
720 printk("External(%dMHz)", pciclk / 1000000);
721 }
722 printk("\n");
723
724
725
726 /* GB->PCI mappings */
727 tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
728 tx4927_pcicptr->g2piogbase = mips_pci_io_base |
729 #ifdef __BIG_ENDIAN
730 TX4927_PCIC_G2PIOGBASE_ECHG
731 #else
732 TX4927_PCIC_G2PIOGBASE_BSDIS
733 #endif
734 ;
735
736 tx4927_pcicptr->g2piopbase = 0;
737
738 tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
739 tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
740 #ifdef __BIG_ENDIAN
741 TX4927_PCIC_G2PMnGBASE_ECHG
742 #else
743 TX4927_PCIC_G2PMnGBASE_BSDIS
744 #endif
745 ;
746 tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
747
748 tx4927_pcicptr->g2pmmask[1] = 0;
749 tx4927_pcicptr->g2pmgbase[1] = 0;
750 tx4927_pcicptr->g2pmpbase[1] = 0;
751 tx4927_pcicptr->g2pmmask[2] = 0;
752 tx4927_pcicptr->g2pmgbase[2] = 0;
753 tx4927_pcicptr->g2pmpbase[2] = 0;
754
755
756 /* PCI->GB mappings (I/O 256B) */
757 tx4927_pcicptr->p2giopbase = 0; /* 256B */
758
759
760 #ifdef TX4927_SUPPORT_COMMAND_IO
761 tx4927_pcicptr->p2giogbase = 0 | TX4927_PCIC_P2GIOGBASE_TIOEN |
762 #ifdef __BIG_ENDIAN
763 TX4927_PCIC_P2GIOGBASE_TECHG
764 #else
765 TX4927_PCIC_P2GIOGBASE_TBSDIS
766 #endif
767 ;
768 #else
769 tx4927_pcicptr->p2giogbase = 0;
770 #endif
771
772 /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
773 tx4927_pcicptr->p2gm0plbase = 0;
774 tx4927_pcicptr->p2gm0pubase = 0;
775 tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
776 #ifdef __BIG_ENDIAN
777 TX4927_PCIC_P2GMnGBASE_TECHG
778 #else
779 TX4927_PCIC_P2GMnGBASE_TBSDIS
780 #endif
781 ;
782
783 /* PCI->GB mappings (MEM 16MB) -not used */
784 tx4927_pcicptr->p2gm1plbase = 0xffffffff;
785 #ifdef CONFIG_TX4927BUG_WORKAROUND
786 /*
787 * TX4927-PCIC-BUG: P2GM1PUBASE must be 0
788 * if P2GM0PUBASE was 0.
789 */
790 tx4927_pcicptr->p2gm1pubase = 0;
791 #else
792 tx4927_pcicptr->p2gm1pubase = 0xffffffff;
793 #endif
794 tx4927_pcicptr->p2gmgbase[1] = 0;
795
796 /* PCI->GB mappings (MEM 1MB) -not used */
797 tx4927_pcicptr->p2gm2pbase = 0xffffffff;
798 tx4927_pcicptr->p2gmgbase[2] = 0;
799
800
801 /* Enable Initiator Memory 0 Space, I/O Space, Config */
802 tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
803 tx4927_pcicptr->pciccfg |=
804 TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
805 TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
806
807
808 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
809 tx4927_pcicptr->pcicfg1 = 0;
810
811 if (tx4927_pcic_trdyto >= 0) {
812 tx4927_pcicptr->g2ptocnt &= ~0xff;
813 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
814 //printk("%s PCIC -- TRDYTO:%02lx\n",toshiba_name,
815 // tx4927_pcicptr->g2ptocnt & 0xff);
816 }
817
818 /* Clear All Local Bus Status */
819 tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
820 /* Enable All Local Bus Interrupts */
821 tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
822 /* Clear All Initiator Status */
823 tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
824 /* Enable All Initiator Interrupts */
825 tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
826 /* Clear All PCI Status Error */
827 tx4927_pcicptr->pcistatus =
828 (tx4927_pcicptr->pcistatus & 0x0000ffff) |
829 (TX4927_PCIC_PCISTATUS_ALL << 16);
830 /* Enable All PCI Status Error Interrupts */
831 tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
832
833 /* PCIC Int => IRC IRQ16 */
834 tx4927_pcicptr->pcicfg2 =
835 (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
836
837 if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
838 /* XXX */
839 } else {
840 /* Reset Bus Arbiter */
841 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
842 /* Enable Bus Arbiter */
843 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
844 }
845
846 tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
847 PCI_COMMAND_MEMORY |
848 #ifdef TX4927_SUPPORT_COMMAND_IO
849 PCI_COMMAND_IO |
850 #endif
851 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
852
853 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
854 ":pci setup complete:\n");
855 //tx4927_dump_pcic_settings();
856
857 {
858 struct pci_channel *p;
859 int busno;
860
861 busno = 0;
862 for (p = mips_pci_channels; p->pci_ops != NULL; p++) {
863 busno = tx4927_pcibios_init(busno, p) + 1;
864 }
865 }
866
867 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
868 }
869
870 #endif /* CONFIG_PCI */
871
toshiba_rbtx4927_restart(char * command)872 void toshiba_rbtx4927_restart(char *command)
873 {
874 printk(KERN_NOTICE "System Rebooting...\n");
875
876 /* enable the s/w reset register */
877 reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);
878
879 /* wait for enable to be seen */
880 while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
881 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
882
883 /* do a s/w reset */
884 reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);
885
886 /* do something passive while waiting for reset */
887 cli();
888 while (1)
889 asm_wait();
890
891 /* no return */
892 }
893
toshiba_rbtx4927_halt(void)894 void toshiba_rbtx4927_halt(void)
895 {
896 printk(KERN_NOTICE "System Halted\n");
897 cli();
898 while (1) {
899 asm_wait();
900 }
901 /* no return */
902 }
903
toshiba_rbtx4927_power_off(void)904 void toshiba_rbtx4927_power_off(void)
905 {
906 toshiba_rbtx4927_halt();
907 /* no return */
908 }
909
toshiba_rbtx4927_nmi(struct pt_regs * regs)910 void toshiba_rbtx4927_nmi (struct pt_regs *regs)
911 {
912 extern void show_code(unsigned int *pc);
913 extern void show_runqueue(void);
914 extern void show_stack(unsigned int *sp);
915 extern void show_state_nolock(void);
916 extern void show_trace(long *sp);
917
918 bust_spinlocks(1);
919 printk("\ncurrent = %d:%s\n",current->pid,current->comm);
920 show_regs(regs);
921 printk("Process %s (pid: %d, stackpage=%08lx)\n",
922 current->comm, current->pid, (unsigned long) current);
923 show_stack((unsigned int *)regs->regs[29]);
924 show_trace((long *)regs->regs[29]);
925 show_code((unsigned int *)regs->cp0_epc);
926 bust_spinlocks(0);
927 }
928
toshiba_rbtx4927_nmi_handler_setup(void)929 void __init toshiba_rbtx4927_nmi_handler_setup (void)
930 {
931 extern void tx4927_nmi_handler (void);
932 unsigned long vec[2];
933
934 vec[0] = 0x08000000 |
935 (0x03ffffff & ((unsigned long)tx4927_nmi_handler >> 2));
936 vec[1] = 0;
937
938 /*
939 * Our firmware (PMON in this case) has a NMI hook that
940 * jumps to 0x80000220. We locate our NMI handler there.
941 */
942 memcpy((void *)(KSEG0 + 0x220), &vec, 0x8);
943 }
944
toshiba_rbtx4927_setup(void)945 void __init toshiba_rbtx4927_setup(void)
946 {
947 extern void (*board_nmi_handler_setup)(void);
948 vu32 cp0_config;
949
950 printk("CPU is %s\n", toshiba_name);
951
952 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
953 "-\n");
954
955 /* f/w leaves this on at startup */
956 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
957 ":Clearing STO_ERL.\n");
958 clear_c0_status(ST0_ERL);
959
960 /* enable caches -- HCP5 does this, pmon does not */
961 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
962 ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
963 cp0_config = read_c0_config();
964 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
965 write_c0_config(cp0_config);
966
967 /* set up the NMI handler */
968 board_nmi_handler_setup = toshiba_rbtx4927_nmi_handler_setup;
969
970 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
971 {
972 extern void dump_cp0(char *);
973 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
974 }
975 #endif
976
977 /* setup irq stuff */
978 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
979 ":Setting up tx4927 pic.\n");
980 TX4927_WR(0xff1ff604, 0x00000400); /* irq trigger */
981 TX4927_WR(0xff1ff608, 0x00000000); /* irq trigger */
982
983 /* setup serial stuff */
984 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
985 ":Setting up tx4927 sio.\n");
986 TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
987 TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
988
989 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
990 "+\n");
991
992
993
994 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
995 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
996 ":mips_io_port_base=0x%08lx\n",
997 mips_io_port_base);
998
999 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
1000 ":Resource\n");
1001 ioport_resource.start = 0;
1002 ioport_resource.end = 0xffffffff;
1003 iomem_resource.start = 0;
1004 iomem_resource.end = 0xffffffff;
1005
1006
1007 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
1008 ":ResetRoutines\n");
1009 _machine_restart = toshiba_rbtx4927_restart;
1010 _machine_halt = toshiba_rbtx4927_halt;
1011 _machine_power_off = toshiba_rbtx4927_power_off;
1012
1013
1014 #ifdef CONFIG_BLK_DEV_IDEPCI
1015 {
1016 TOSHIBA_RBTX4927_SETUP_DPRINTK
1017 (TOSHIBA_RBTX4927_SETUP_SETUP,
1018 ":ide_ops=&std_ide_ops(modified)\n");
1019 ide_ops = &std_ide_ops;
1020 }
1021 #else
1022 {
1023 TOSHIBA_RBTX4927_SETUP_DPRINTK
1024 (TOSHIBA_RBTX4927_SETUP_SETUP,
1025 ":ide_ops=<NOT_CONFIG>\n");
1026 }
1027 #endif
1028
1029 #ifdef CONFIG_FB
1030 {
1031 conswitchp = &dummy_con;
1032 }
1033 #endif
1034
1035
1036
1037
1038 #ifdef CONFIG_PCI
1039
1040 /* PCIC */
1041 /*
1042 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
1043 * PCIDIVMODE[12:11]'s initial value are given by S9[4:3] (ON:0, OFF:1).
1044 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
1045 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
1046 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
1047 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
1048 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
1049 */
1050 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
1051 "ccfg is %lx, DIV is %x\n",
1052 (unsigned long) tx4927_ccfgptr->
1053 ccfg, TX4927_CCFG_PCIDIVMODE_MASK);
1054
1055 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
1056 "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
1057 (unsigned long) tx4927_ccfgptr->
1058 ccfg & TX4927_CCFG_PCI66,
1059 (unsigned long) tx4927_ccfgptr->
1060 ccfg & TX4927_CCFG_PCIMIDE,
1061 (unsigned long) tx4927_ccfgptr->
1062 ccfg & TX4927_CCFG_PCIXARB);
1063
1064 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
1065 "PCIDIVMODE is %lx\n",
1066 (unsigned long) tx4927_ccfgptr->
1067 ccfg & TX4927_CCFG_PCIDIVMODE_MASK);
1068
1069 switch ((unsigned long) tx4927_ccfgptr->
1070 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
1071 case TX4927_CCFG_PCIDIVMODE_2_5:
1072 case TX4927_CCFG_PCIDIVMODE_5:
1073 tx4927_cpu_clock = 166000000; /* 166MHz */
1074 break;
1075 default:
1076 tx4927_cpu_clock = 200000000; /* 200MHz */
1077 }
1078
1079 /* CCFG */
1080 /* enable Timeout BusError */
1081 if (tx4927_ccfg_toeon)
1082 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
1083
1084 /* SDRAMC fixup */
1085 #ifdef CONFIG_TX4927BUG_WORKAROUND
1086 /*
1087 * TX4927-BUG: INF 01-01-18/ BUG 01-01-22
1088 * G-bus timeout error detection is incorrect
1089 */
1090 if (tx4927_ccfg_toeon)
1091 tx4927_sdramcptr->tr |= 0x02000000; /* RCD:3tck */
1092 #endif
1093
1094 #ifdef TX4927_SUPPORT_PCI_66
1095 tx4927_pci66_setup();
1096 #endif
1097
1098 tx4927_pci_setup();
1099
1100
1101 {
1102 u32 id = 0;
1103 early_read_config_dword(&mips_pci_channels[0], 0, 0, 0x90,
1104 PCI_VENDOR_ID, &id);
1105 if (id == 0x94601055) {
1106 tx4927_using_backplane = 1;
1107 printk("backplane board IS installed\n");
1108 } else {
1109 printk("backplane board NOT installed\n");
1110 }
1111 }
1112 #endif
1113
1114
1115 /* this is only done if backplane board installed, so must wait for pci */
1116 #ifdef CONFIG_PC_KEYB
1117 {
1118 if (tx4927_using_backplane) {
1119 extern struct kbd_ops std_kbd_ops;
1120 kbd_ops = &std_kbd_ops;
1121 TOSHIBA_RBTX4927_SETUP_DPRINTK
1122 (TOSHIBA_RBTX4927_SETUP_SETUP,
1123 ":kbd_ops=&std_kbd_ops\n");
1124 } else {
1125 TOSHIBA_RBTX4927_SETUP_DPRINTK
1126 (TOSHIBA_RBTX4927_SETUP_SETUP,
1127 ":kbd_ops=<NO_BACKPLANE>\n");
1128 }
1129 }
1130 #else
1131 {
1132 TOSHIBA_RBTX4927_SETUP_DPRINTK
1133 (TOSHIBA_RBTX4927_SETUP_SETUP,
1134 ":kbd_ops=<NOT_CONFIG>\n");
1135 }
1136 #endif
1137
1138 /* this is on ISA bus behind PCI bus, so need PCI up first */
1139 #ifdef CONFIG_TOSHIBA_FPCIB0
1140 {
1141 if (tx4927_using_backplane) {
1142 TOSHIBA_RBTX4927_SETUP_DPRINTK
1143 (TOSHIBA_RBTX4927_SETUP_SETUP,
1144 ":fpcibo=yes\n");
1145
1146 TOSHIBA_RBTX4927_SETUP_DPRINTK
1147 (TOSHIBA_RBTX4927_SETUP_SETUP,
1148 ":smsc_fdc37m81x_init()\n");
1149 smsc_fdc37m81x_init(0x3f0);
1150
1151 TOSHIBA_RBTX4927_SETUP_DPRINTK
1152 (TOSHIBA_RBTX4927_SETUP_SETUP,
1153 ":smsc_fdc37m81x_config_beg()\n");
1154 smsc_fdc37m81x_config_beg();
1155
1156 TOSHIBA_RBTX4927_SETUP_DPRINTK
1157 (TOSHIBA_RBTX4927_SETUP_SETUP,
1158 ":smsc_fdc37m81x_config_set(KBD)\n");
1159 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
1160 SMSC_FDC37M81X_KBD);
1161 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
1162 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
1163 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
1164 1);
1165
1166 smsc_fdc37m81x_config_end();
1167 TOSHIBA_RBTX4927_SETUP_DPRINTK
1168 (TOSHIBA_RBTX4927_SETUP_SETUP,
1169 ":smsc_fdc37m81x_config_end()\n");
1170 } else {
1171 TOSHIBA_RBTX4927_SETUP_DPRINTK
1172 (TOSHIBA_RBTX4927_SETUP_SETUP,
1173 ":fpcibo=not_found\n");
1174 }
1175 }
1176 #else
1177 {
1178 TOSHIBA_RBTX4927_SETUP_DPRINTK
1179 (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
1180 }
1181 #endif
1182
1183
1184 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
1185 "+\n");
1186 }
1187
1188 void __init
toshiba_rbtx4927_time_init(void)1189 toshiba_rbtx4927_time_init(void)
1190 {
1191 #ifdef CONFIG_DS1742
1192 extern void rtc_ds1742_init(unsigned long base);
1193 extern void rtc_ds1742_wait(void);
1194 extern struct rtc_ops ds1742_rtc_ops;
1195 u32 c1;
1196 u32 c2;
1197 #endif
1198
1199 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
1200
1201 #ifdef CONFIG_DS1742
1202
1203 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1204 ":rtc_ds1742_init()-\n");
1205 rtc_ds1742_init(RBTX4927_IOC_NVRAMB_ADDR);
1206 rtc_ops = &ds1742_rtc_ops;
1207
1208 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1209 ":rtc_ds1742_init()+\n");
1210
1211 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1212 ":Calibrate mips_hpt_frequency-\n");
1213 rtc_ds1742_wait();
1214
1215 /* get the count */
1216 c1 = read_c0_count();
1217
1218 /* wait for the seconds to change again */
1219 rtc_ds1742_wait();
1220
1221 /* get the count again */
1222 c2 = read_c0_count();
1223
1224 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1225 ":Calibrate mips_hpt_frequency+\n");
1226 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1227 ":c1=%12u\n", c1);
1228 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1229 ":c2=%12u\n", c2);
1230
1231 /* this diff is as close as we are going to get to counter ticks per sec */
1232 mips_hpt_frequency = abs(c2 - c1);
1233 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1234 ":f1=%12u\n", mips_hpt_frequency);
1235
1236 /* round to 1/10th of a MHz */
1237 mips_hpt_frequency /= (100 * 1000);
1238 mips_hpt_frequency *= (100 * 1000);
1239 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1240 ":f2=%12u\n", mips_hpt_frequency);
1241
1242 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_INFO,
1243 ":mips_hpt_frequency=%uHz (%uMHz)\n",
1244 mips_hpt_frequency,
1245 mips_hpt_frequency / 1000000);
1246 #else
1247 mips_hpt_frequency = 100000000;
1248 #endif
1249
1250 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
1251
1252 }
1253
toshiba_rbtx4927_timer_setup(struct irqaction * irq)1254 void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
1255 {
1256 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1257 "-\n");
1258 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1259 "+\n");
1260 }
1261